US20010011775A1

US20010011775A1 - Interconnect structure of semiconductor device

Info

Publication number: US20010011775A1
Application number: US09/440,710
Authority: US
Inventors: Katsuya Izumi
Original assignee: Individual
Current assignee: Renesas Electronics Corp
Priority date: 1998-11-17
Filing date: 1999-11-16
Publication date: 2001-08-09
Anticipated expiration: 2019-11-16
Also published as: KR100347082B1; US6323556B2; JP2000150599A; JP3230667B2; KR20000035508A

Abstract

An interconnect structure of a semiconductor device comprising: a semiconductor substrate; a plurality of interconnects including a subject interconnect; a plurality of interlayer dielectric films disposed between the adjacent interconnects; and a concave or convex portion formed on the surface of the semiconductor device corresponding to the desired portion of the subject interconnect is disclosed. When some deficiency is generated on the subject interconnect, the deficiency can be detected by measuring the corresponding concave or convex portion on the surface of the semiconductor for prompt inspection because the concave or convex portion is connected to the subject interconnect.

Description

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to an interconnect structure of a semiconductor device, more in detail, to the interconnect structure of the semiconductor device which can be easily observed when the interconnect structure is inspected by employing an electron beam inspection apparatus.

(b) Description of the Related Art

Since, with development of miniaturization and high integration of a semiconductor device, components of the semiconductor device including its interconnects are miniaturized and complicated, the inspection of the components becomes more and more difficult. Depending on the inspection techniques, the semiconductor device is operated during the inspection, wherein a non-destructive inspection of the components of the semiconductor device is conducted.

An electron beam inspection apparatus (hereinafter referred to as EB tester) is conventionally employed for non-destructive inspection of the components of the semiconductor device under the operation.

The EB tester utilizes the principle that an amount of secondary electrons generated at the position of measurement, the secondary electrons being generated upon irradiation of electron beams on the position of measurement of the semiconductor device under the operation, is proportional to the potential at the position of measurement. In the EB tester known as a non-contact inspection apparatus, the electron beams are irradiated on an interconnect of the semiconductor device to be inspected under vacuum, and a potential or a voltage of the interconnect is measured by means of the energy level of the secondary electrons generated from the irradiated part. The EB tester is frequently employed for inspecting the interior of the semiconductor device.

When, for example, a local damage or destruction is generated on a MOSFET, current is concentrated to the damaged or destructed part to produce a photon, the damaged or destructed part can be specified by detecting the photon by employing the EB tester.

The EB tester measures the amount of the secondary electrons having kinetic energy as low as several electron volts radiated from the position of measurement of the semiconductor device after conversion of the amount of the secondary electrons into a corresponding voltage. The EB tester usually has functions of observing secondary electron images and of measuring waveforms.

The function of observing the secondary electron images includes a function of observing a real time image while irradiating successive beams on the position of measurement of the semiconductor device and another function of observing a stroboscope image while irradiating a primary electron beam. In the function of measuring the waveforms, waveforms are obtained by irradiating a pulse beam having a variable phase to the position of measurement of the semiconductor device for radiation of secondary electrons and measuring the respective phases by employing a feedback loop with a spectrometer.

In the observation, a higher potential region of the secondary electrons obtained by the EB tester is shown as a dark side on a screen and a lower potential region is shown as a bright side, the higher potential region is shown as a high level. In the measurement, if unevenness exists on the surface of the semiconductor device during the observation with the EB tester, a secondary electron image reflecting the unevenness is obtained because the irradiated primary electron undergoes diffused reflection.

The interconnect structure of a semiconductor device is generally multi-layered with the miniaturization and the higher integration of the semiconductor device as shown in FIGS. 1A and 1B.

The

interconnect structure

11 shown in FIGS. 1A and 1B includes a first layer subject interconnect 14 overlying an undercoat dielectric film 12 and to be subjected to the measurement. The interconnect structure 11 also includes other first layer interconnects 14-1, 14-2, 14-3 and 14-4 extending parallel to the subject interconnect 14, a second layer interconnect 16 extending perpendicular to and overlying the first layer subject interconnect 14, and a third layer interconnect 18 extending right above the first layer subject interconnect 14 and having a width larger than that of the first layer subject interconnect 14.

A first interlayer

dielectric film

20 is formed between the first layer subject interconnect 14 and the second layer interconnect 16. A second interlayer dielectric film 22 is formed between the second layer interconnect 16 and the third layer interconnect 18, and a protection film 24 is formed on the third layer interconnect 18.

The electron beam is generally directly irradiated to the position of measurement in the EB tester. In this respect, a problem arises that the potential of the first layer subject interconnect 14 or the position of deficiency cannot be specified when the first layer subject interconnect 14 in the above interconnect structure 11 is observed by employing the EB tester.

A first reason is as follows. Since the third layer interconnect 18 having a larger interconnect width overlies the first layer subject interconnect 14 in the multi-layered interconnect structure as shown in FIG. 1B, irradiation of the electron beam from the EB tester on the first layer subject interconnect 14 is blocked by the third layer interconnect 18. Accordingly, the potential of the first layer subject interconnect 14 cannot be correctly measured.

Even when the width of the

third layer interconnect

18 is not large, judgement whether the secondary electrons originate from the first layer subject interconnect 14 or the third layer interconnect 18 is difficult, and accordingly, the correct measurement of the first layer subject interconnect 14 cannot be conducted similarly to the case of the third layer interconnect 18 having the large width.

A second reason is as follows. In the measurement employing the EB tester, the interconnect path under the interlayer dielectric film is monitored by utilizing unevenness of the interlayer dielectric film. However, in the present semiconductor devices, the interlayer dielectric film on the interconnect of the multi-layered structure is generally polished for flattening. This make it difficult to effectively observe the interconnect covered by the interlayer dielectric film by employing the EB tester.

A third reason is as follows. When another first layer subject interconnect 14-2 has a higher potential, and the first layer subject interconnect 14 and the other first layer sub-interconnects 14-1, 14-3 and 14-4 have a lower potential, the potential of another first layer subject interconnect 14-2 is displayed as a bright side and the potentials of the first layer subject interconnect 14 and the other first layer interconnects 14-1, 14-3 and 14-4 are displayed as a bright side. Since the flattened surface makes it difficult to observe the lower potential interconnects, it is difficult to specify the interconnect from which the bright side originates among the first layer subject interconnect 14 and the first layer interconnects 14-1, 14-2, 14-3 and 14-4.

SUMMARY OF THE INVENTION

In view of the foregoing, an object of the present invention is to provide an interconnect structure of a semiconductor device having a configuration for easy observation by employing an EB tester and easy position identification.

The present invention provides a semiconductor device comprising a semiconductor substrate, a plurality of interconnect layers overlying said semiconductor substrate and including a top interconnect layer, a plurality of interlayer dielectric films each disposed between adjacent two of said interconnect layers, a top dielectric film disposed on said top interconnect layer, said top dielectric film having a plurality of convex or concave portions each disposed substantially right above a portion of a corresponding interconnect of at least one of said interconnect layers.

In accordance with the interconnect structure of the semiconductor device of the present invention, since the concave portion or the convex portion which corresponds to the subject interconnect is formed on the surface of the semiconductor device, the position of the subject interconnect can be easily specified by measuring the concave portion or the convex portion with the EB tester.

Therefore, a defective portion of the semiconductor device can be promptly detected because the state of the interconnect of the semiconductor device under operation can be easily and non-destructively observed with the EB tester.

An extension as used herein includes an extension part, a plug and a relay pad.

The above and other objects, features and advantages of the present invention will be more apparent from the following description.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is a top plan view showing an interconnect structure of a conventional semiconductor device, and FIG. 1B is a vertical sectional view taken along a line A-A of FIG. 1A. [0025]
FIG. 2A is a top plan view showing an interconnect structure of a semiconductor device of Embodiment 1, FIG. 2B is a vertical sectional view taken along a line B-B of FIG. 2A, and FIG. 2C is a vertical sectional view showing a modified example of the interconnect structure of FIG. 2B. [0026]
FIG. 3A is a top plan view showing an interconnect structure of a semiconductor device of Embodiment 2, FIG. 3B is a vertical sectional view taken along a line C-C of FIG. 3A, and FIG. 3C is a vertical sectional view showing a modified example of the interconnect structure of FIG. 3B. [0027]
FIG. 4A is a top plan view showing an interconnect structure of a semiconductor device of Embodiment 3, FIG. 4B is a vertical sectional view taken along a line D-D of FIG. 4A, and FIG. 4C is a vertical sectional view showing a modified example of the interconnect structure of FIG. 4B. [0028]
FIG. 5A is a top plan view showing an interconnect structure of a semiconductor device of Embodiment 4, and FIG. 5B is a vertical sectional view taken along a line E-E of FIG. 5A. [0029]
FIG. 6A is a top plan view showing an interconnect structure of a semiconductor device of Embodiment 5, FIG. 6B is a vertical sectional view taken along a line F-F of FIG. 6A and FIG. 6C is a vertical sectional view showing a modified example of the interconnect structure of FIG. 6B. [0030]

PREFERRED EMBODIMENTS OF THE INVENTION

The term “subject interconnect” as used in the present invention means an interconnect to be subjected to measurement of the potential. In the embodiments described hereinafter, the subject interconnect is disposed as a bottom layer interconnect, and the number of the interconnects from the subject interconnect to the uppermost interconnect is not restricted. If, for example, the number of the interconnects is five, the subject interconnect may be a first layer interconnect or a fourth layer interconnect. The material of the subject interconnect is not restricted, and an aluminum metal, a copper metal, an aluminum alloy, a copper alloy and polysilicon may be employed. [0031]
Now, the present invention is more specifically described with reference to accompanying drawings. [0032]

Embodiment 1

The [0033] interconnect structure 10 of Embodiment 1 shown in FIGS. 2A and 2B includes an undercoat dielectric film 12, a first layer subject interconnect 14 overlying the undercoat dielectric film 12, a second layer interconnect 16 extending perpendicular to and overlying the first layer subject interconnect 14, and a third layer interconnect 18 extending right above the first layer subject interconnect 14 and having a width larger than that of the first layer subject interconnect 14.
A first [0034] interlayer dielectric film 20 is formed between the first layer subject interconnect 14 and the second layer interconnect 16. A second interlayer dielectric film 22 is formed between the second layer interconnect 16 and the third layer interconnect 18, and a protection film 24 is formed on the third layer interconnect 18 and the second interlayer dielectric film 22.
Even if the first [0035] layer subject interconnect 14 in the interconnect structure 10 of Embodiment 1 is subjected to measurement with an EB tester, the electron beam cannot be efficiently irradiated and the secondary beam is blocked by the third layer interconnect 18 from reaching to the EB tester because the first layer subject interconnect 14 is covered by the third layer interconnect 18.
In order to avoid this disadvantage, a [0036] dummy interconnect 26 connected with the first layer subject interconnect 14 penetrates the first and the second interlayer dielectric films 20 and 22 in the interconnect structure 10 of Embodiment shown in FIGS. 2A and 2B. As an inspected part of the first layer subject interconnect 14, an inspection pad 28 is provided on the second interlayer dielectric film 22, which is located apart from the third layer interconnect 18.
As shown in FIG. 2A, the [0037] dummy interconnect 26 includes an extension part 30 disposed right below the inspection pad 28, which is branched and extending from the first layer subject interconnect 14, and a relay pad 32 formed on the first interlayer dielectric film 20 right above the extension part 30. The size of the relay pad 32 may be that which can be in contact with the plug. The relay pad is arbitrarily arranged and is formed in a region having a low interconnect density formed on the undercoat interlayer dielectric film. This provides suitable layouts for each of the interconnects of the respective layers.
The [0038] relay pad 32 is connected to the extension part 30 through a first plug 34 penetrating the first interlayer dielectric film 20. The inspection pad 28 is connected to the relay pad 32 through a second plug 36 penetrating the second interlayer dielectric film 22.
The [0039] extension part 30 is made of the same material, for example, an aluminum alloy as that of the first layer subject interconnect 14 and is formed therewith in the same interconnect formation step, so is the relay pad 32 as that of the second layer interconnect 16, and so is the inspection pad 28 as that of the third layer interconnect 18.
In accordance with the [0040] interconnect structure 10 of Embodiment 1, the measurement of the potential or voltage of the first layer subject interconnect 14 which has been hardly performed in the conventional semiconductor device can be conducted by monitoring the unevenness of the protection layer 24 with the EB tester to observe the inspection pad 28.
In a modified [0041] structure 10 a of Embodiment 1 shown in FIG. 2C having a modified dummy interconnect 26 a, the inspection pad 28 and the extension part 30 may be connected with each other by a plug 200 penetrating the first interlayer dielectric film 20 and the second interlayer dielectric film 22 without forming the relay pad. Also in this structure 10 a, the interconnect structure having a function similar to that of the structure having the relay pad can be obtained.

Embodiment 2

An [0042] interconnect structure 40 of Embodiment 2 shown in FIGS. 3A and 3B includes an undercoat dielectric film 42, a first layer subject interconnect 44 overlying the undercoat dielectric film 42, a second layer interconnect 46 extending perpendicular to and overlying the first layer subject interconnect 44, a third layer interconnect 48 extending parallel to and not right above the first layer subject interconnect 44, a fourth layer interconnect 50 extending parallel to the second layer interconnect 46 and a fifth layer interconnect 52 extending parallel to the third layer interconnect 48.
First, second, third and fourth interlayer [0043] dielectric films 54, 56, 58 and 60 are formed between the corresponding adjacent interconnects, and a protection film 62 is formed on the fifth layer interconnect 52.
Even if the first [0044] layer subject interconnect 44 in the interconnect structure 40 of Embodiment 2 is observed with the EB tester, existence of the first layer subject interconnect 44 cannot be detected by monitoring the unevenness of the protection layer 62 and the first interlayer dielectric film 54 because the first layer subject interconnect 44 extends deep in the first interlayer dielectric film 54. Accordingly, an electron beam cannot be irradiated.
In order to avoid this disadvantage, a [0045] dummy interconnect 64 connected with the first layer subject interconnect 44 penetrates the first to the fourth interlayer dielectric films 54, 56, 58 and 60 in the interconnect structure 40 of Embodiment 2 shown in FIGS. 3A and 3B. As an inspected part of the first layer subject interconnect 44, an inspection pad 66 is present on the fourth interlayer dielectric film 60 right above the first layer subject interconnect 44.
As shown in FIG. 3B, the [0046] dummy interconnect 64 has a first relay pad 68 formed on the first interlayer dielectric film 54 right above the first layer subject interconnect 44, a second relay pad 70 formed on the second interlayer dielectric film 56 right above the first relay pad 68, and a third relay pad 72 formed on the third interlayer dielectric film 58 right above the second relay pad 70.
The first [0047] layer subject interconnect 44, the first, the second and the third relay pads 68, 70 and 72 are connected to the first, the second and the third relay pad 68, 70 and 72 and the inspection pad 66 immediately above by plugs 74, 76, 78 and 80, respectively.
The [0048] relay pads 68, 70 and 72 and the inspection pad 66 may be made of the same interconnect materials, for example, an aluminum alloy as those of the second layer interconnect 46, the third layer interconnect 48, the fourth layer interconnect 50 and the fifth layer interconnect 52, respectively, and these can be formed in the same interconnect formation steps.
In accordance with the [0049] interconnect structure 40 of Embodiment 2, the measurement of the potential or voltage of the first layer subject interconnect 44 which has not been performed can be conducted by observing the inspection pad 66 by employing the EB tester.
In a modified [0050] structure 40 a of Embodiment 2 shown in FIG. 3C having a modified dummy interconnect 64 a, the inspection pad 66 and the first layer subject interconnect 44 may be connected with each other by a plug 201 penetrating the first interlayer dielectric film 54, the second interlayer dielectric film 56 and the third interlayer dielectric film 58 and the fourth interlayer dielectric film 60 without forming the relay pad. Also in this structure 40 a, the interconnect structure having a function similar to that of the structure having the relay pad can be obtained.

Embodiment 3

Even if an interconnect structure includes the first [0051] layer subject interconnect 14, the second layer interconnect 16 and the third layer interconnect 18 similarly to Embodiment 1, Embodiment 1 cannot be sometimes applied thereto. A case in which interconnect densities of the second and the third interconnects are high and the dummy interconnect of Embodiment 1 cannot be formed at a desired position corresponds to the above interconnect structure. Especially, when the number of layers of the interconnects is large, the dummy interconnects 26 and 64 of Embodiments 1 and 2 may be hardly formed.
An interconnect structure of Embodiment 3 can be suitably employed even when the interconnect structures of Embodiments 1 and 2 cannot be applied. [0052]
An [0053] interconnect structure 90 of Embodiment 3 shown in FIGS. 4A and 4B includes an undercoat dielectric film 12, a first layer subject interconnect 14 overlying the undercoat dielectric film 12, a second layer interconnect 16 extending perpendicular to and overlying the first layer subject interconnect 14, and a third layer interconnect 18 extending right above the first layer subject interconnect 14 and having a width larger than that of the first layer subject interconnect 14.
A first [0054] interlayer dielectric film 20 is formed between the first layer subject interconnect 14 and the second layer interconnect 16. A second interlayer dielectric film 22 is formed between the second layer interconnect 16 and the third layer interconnect 18, and a protection film 24 is formed on the third layer interconnect 18.
Since the first [0055] layer subject interconnect 14 is hardly observed with the EB tester in the interconnect structure 90 of Embodiment 3 similarly to Embodiment 1, a dummy interconnect 92 penetrating the first and the second interlayer dielectric films 20 and 22 to pull up part of the first layer subject interconnect 14 onto the second interlayer dielectric film 22. As an inspected part of the first layer subject interconnect 14, an inspection lengthy interconnect 94 is present on the second interlayer dielectric film 22, which is not so near to the third layer interconnect 18.
The [0056] dummy interconnect 92 divides the first layer subject interconnect 14 at a required position, and the both opposite portions of the divided first layer subject interconnects 14 are bent at right angles to the same horizontal direction to form two elongated ends 96 and 98 which are then connected to the inspection lengthy interconnect 94 on the second interlayer dielectric film 22.
The [0057] dummy interconnect 92 includes relay pads 100 and 102 formed on the first interlayer dielectric film 20 right above the respective elongated ends 96 and 98 of the first layer subject interconnects 14 as shown in FIG. 4B. The relay pads 100 and 102 are connected to the respective elongated ends 96 and 98 of the first layer subject interconnects 14 through two first plugs 104 and 106, respectively. The inspection lengthy interconnect 94 is connected to the relay pads 100 and 102 through two second plugs 108 and 110 penetrating the second interlayer dielectric film 22, respectively.
The [0058] relay pads 100 and 102 may be made of the same interconnect material, for example, an aluminum alloy as that of the second layer interconnect 16 and may be simultaneously formed therewith in the same interconnect formation step, and so is the inspection lengthy interconnect 94 as that of the third layer interconnect 18.
In accordance with the [0059] interconnect structure 90 of Embodiment 3, the measurement of the potential or voltage of the first layer subject interconnect 14 which has been hardly performed can be conducted by monitoring the unevenness of the protection layer 24 with the EB tester to observe the inspection lengthy interconnect 94.
In a modified [0060] structure 90 a of Embodiment 3 shown in FIG. 4C having a modified dummy interconnect 92 a, the inspection lengthy interconnect 94 and the elongated ends 96 and 98 may be connected with each other by two plugs 202 and 203 penetrating the first interlayer dielectric film 20 and the second interlayer dielectric film 22 without forming the relay pad. Also in this structure 90 a, the interconnect structure having a function similar to that of the structure having the relay pad can be obtained.

Embodiment 4

The parallel first layer interconnects [0061] 14, 14-1, 14-2, 14-3 and 14-4 may be densely formed as shown in FIG. 1 in a certain interconnect structure of the semiconductor device in which no interconnects are present right above the five first layer interconnects during the observation with the EB tester. Even if one or more interconnects which are brightly displayed among the five first layer interconnects can be observed, identification which interconnect among the five is brightly displayed is difficult because no unevenness of the surface makes invisible the interconnects darkly displayed.
Embodiment 4 is an interconnect structure responding to the above problem. [0062]
An [0063] interconnect structure 120 of Embodiment 4 shown in FIGS. 5A and 5B includes an undercoat dielectric film 42, a first layer subject interconnect 44 overlying the undercoat dielectric film 42, first layer sub-interconnects 44-1, 44-2, 44-3 and 44-4 extending parallel to the first layer subject interconnect 44, a second layer interconnect 46 extending perpendicular to and overlying the first layer subject interconnect 44, a third layer interconnect 48 extending parallel to the first layer subject interconnect 44, a fourth layer interconnect 50 extending parallel to the second layer subject interconnect 46, and a fifth layer interconnect 52 extending parallel to the third layer interconnect 48.
First, second, third and fourth interlayer [0064] dielectric films 54, 56, 58 and 60 are formed between the corresponding adjacent interconnects, and convex portions 204, 204-1, 204-2, 203-3 and 203-4 are formed on the fourth interlayer dielectric film 60 corresponding to the fist layer interconnects 44, 44-1, 44-2, 44-3 and 44-4. A protection film 62 is formed on the fifth layer interconnect 52.
The formation of the convex portions on the fourth [0065] interlayer dielectric film 60 makes another convex portions 206, 206-1, 206-2, 206-3 and 206-4 on the surface of the semiconductor device or of the protection film 62 corresponding to the fist layer interconnects 44, 44-1, 44-2, 44-3 and 44-4.
Since the positions of the fist layer interconnects [0066] 44, 44-1, 44-2, 44-3 and 44-4 during the observation with the EB tester can be recognized by the convex portions 206, 206-1, 206-2, 206-3 and 206-4 on the surface of the semiconductor device, identification which interconnect is brightly displayed can be easily performed when one of the five first interconnects are brightly displayed.

Embodiment 5

An interconnect structure of Embodiment 5 can respond to when a problem arises that the potential of the bottom layer interconnect is hardly measured. This problem occurs when the number of the secondary electrons radiated from the bottom layer to be observed is reduced to the excessive small number after the secondary electrons permeates the plurality of the interlayer dielectric films to reach to the surface of the semiconductor device in Embodiment 4. [0067]
As shown in FIGS. 6A and 6B, the [0068] interconnect structure 130 of Embodiment 5 includes dummy interconnects 140, 140-1, 140-2, 140-3 and 140-4 added to the interconnect structure 120 of FIGS. 5A and 5B. The dummy interconnects 140, 140-1, 140-2, 140-3 and 140-4 penetrate first, second, third and fourth interlayer dielectric films 54, 56, 58 and 60 to be connected to first layer interconnects 44, 44-1, 44-2, 44-3 and 44-4, respectively. Inspection pads 150, 150-1, 150-2, 150-3 and 150-4 are formed right above the first layer interconnects 44, 44-1, 44-2, 44-3 and 44-4, respectively, as inspected parts thereof.
The dummy interconnects [0069] 140, 140-1, 140-2, 140-3 and 140-4 include first relay pads 68, 68-1, 68-2, 68-3 and 68-4 right above the first layer interconnects 44, 44-1, 44-2, 44-3 and 44-4, respectively.
The first layer interconnects [0070] 44, 44-1, 44-2, 44-3 and 44-4 are connected to the first relay pads 68, 68-1, 68-2, 68-3 and 68-4 through first plugs 74, 74-1, 74-2, 74-3 and 74-4, respectively. The first relay pads 68, 68-1, 68-2, 68-3 and 68-4 are connected to inspection pads 150, 150-1, 150-2, 150-3 and 150-4 through second plugs 80, 80-1, 80-2, 80-3 and 80-4.
The [0071] first relay pads 68, 68-1, 68-2, 68-3 and 68-4 and the inspection pads 150, 150-1, 150-2, 150-3 and 150-4 may be made of the same interconnect material, for example, an aluminum alloy as those of the second layer interconnect 46 and the third layer interconnect 48, and can be simultaneously formed therewith in the same interconnect formation step.
Since [0072] concave portions 207, 207-1, 207-2, 207-3 and 207-4 are formed on the fourth interlayer dielectric film 60 corresponding to the first layer interconnects 44, 44-1, 44-2, 44-3 and 44-4, respectively, in the interconnect structure 130 of Embodiment 5, another concave portions 208, 208-1, 208-2, 208-3 and 208-4 are formed on the surface of the semiconductor device or of the protection film 62 corresponding to the first layer interconnects 44, 44-1, 44-2, 44-3 and 44-4. The concave portions formed on the surface of the semiconductor device have a similar function to that of the convex portions formed on the surface of the semiconductor device in Embodiment 4, that is, the function of easily specify the subject interconnect.
The [0073] interconnect structure 130 of Embodiment 5 has an effect of easily distinguish the potential of the subject interconnect to be observed during the observation with the EB tester because the first layer interconnects 44, 44-1, 44-2, 44-3 and 44-4 are shifted to the inspection pads 150, 150-1, 150-2, 150-3 and 150-4 near the surface of the semiconductor device and thereby the reduction of the number of the secondary electrons in the interlayer dielectric film is lowered compared with Embodiment 4.
As shown in FIG. 6C, the [0074] inspection pads 150, 150-1, 150-2, 150-3 and 150-4 and the first layer interconnects 44, 44-1, 44-2, 44-3 and 44-4 may be connected with each other by plugs 205, 205-1, 205-2, 205-3 and 205-4 penetrating the first interlayer dielectric film 54 and the second interlayer dielectric film 56 without forming the relay pad. Also in this structure 130 a, the interconnect structure having a function similar to that of the structure having the relay pad can be obtained.
In Embodiment 5, the inspection pad can be shifted onto a higher layer, and a structure of connecting the first layer subject interconnect to the inspection pad can be modified to those of Embodiments 1 and 3. [0075]
Although the above Embodiments have been described to have the structure including the specified number of the interconnects, the number is not restricted thereto and arrangement of the interconnects is not limited to those of the Embodiments. [0076]
Since the above embodiments are described only for examples, the present invention is not limited to the above embodiments and various modifications or alternations can be easily made therefrom by those skilled in the art without departing from the scope of the present invention. [0077]

Claims

What is claimed is:

1. A semiconductor device comprising a semiconductor substrate, a plurality of interconnect layers overlying said semiconductor substrate and including a top interconnect layer, a plurality of interlayer dielectric films each disposed between adjacent two of said interconnect layers, a top dielectric film disposed on said top interconnect layer, said top dielectric film having a plurality of convex or concave portions each disposed substantially right above a portion of a corresponding interconnect of at least one of said interconnect layers.

2. A semiconductor device comprising a semiconductor substrate, a plurality of interconnect layers overlying said semiconductor substrate and including a top interconnect layer, a plurality of interlayer dielectric films each disposed between adjacent two of said interconnect layers, a top dielectric film disposed on said top interconnect layer, a plurality of dummy interconnects each disposed for a corresponding interconnect of at least one of said interconnect layers, each of said dummy interconnects including an inspection pad disposed on one of said interlayer dielectric films overlying said at least one of said interconnect layers and an extension connected between said inspection pad and said corresponding interconnect.

3. The semiconductor device as defined in

claim 2

, wherein said top dielectric film has a convex or concave portion disposed substantially right above said inspection pad.

4. The semiconductor device as defined in

claim 2

, wherein said inspection pad and said top interconnect layer are formed as a common layer.

5. The semiconductor device as defined in

claim 2

, wherein said extension part includes a relay pad disposed on one of said interlayer dielectric films between said inspection pad and said corresponding interconnect.

6. The semiconductor device as defined in

claim 5

, further comprising an extension part which is formed with the corresponding interconnect as a common layer.

7. A semiconductor device comprising a semiconductor substrate, a plurality of interconnect layers overlying said semiconductor substrate and including a top interconnect layer, a plurality of interlayer dielectric films each disposed between adjacent two of said interconnect layers, a top dielectric film disposed on said top interconnect layer, a plurality of dummy interconnects each connected to a corresponding interconnect of at least one of said interconnect layers through an extension, each of said dummy interconnects being disposed on one of said interlayer dielectric film adjacent to said top dielectric film.

8. The semiconductor device as defined in

claim 7

, wherein said extension includes a relay pad disposed on one of said interlayer dielectric film.