JP2008177282A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for confirming a detective location within a short period of time during physical analysis in the in-line defect inspecting process of a semiconductor device. <P>SOLUTION: A principal wiring part separator 1, a wiring central part separator 2, and a wiring end part separator 3 are respectively arranged to a principal wiring part, a wiring central part, and a wiring end part of a test pattern and these separators 1, 2 and 3 loaded to the test pattern are defined as indices for confirming coordinate locations of a defect at the time of observing the defect. For example, the wiring central part separator 2 is formed in a structure subject to observation as a wiring pattern by exposing the second wiring layer 4 at the front surface by the length L of separator and the other wiring central part is formed in a structure not subject to observation as the wiring pattern by electrically connecting the wiring end part from the principal wiring part via a first wiring layer 5. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique that is effective when applied to an inspection process for diagnosing an electrical failure such as an in-line defect that occurs in the manufacturing process of a semiconductor device.

  For example, a wiring defect detection circuit consisting of wiring with a large capacity with a semiconductor substrate and wiring with a small capacity with a semiconductor substrate is formed on one surface of a semiconductor wafer for wiring defect detection, and an electron beam is scanned across these wirings. Japanese Patent Laid-Open No. 11-330181 (Patent Document 1) describes a technique for detecting a short-circuited portion of both wirings by measuring the amount of secondary electrons generated from these wirings.

  Further, a test pattern of an electric circuit manufacturing process having a meandering wiring resistance failure detection pattern and a through-hole conduction failure detection pattern which is disposed in a gap between the wiring resistance failure detection pattern and electrically insulated. Japanese Unexamined Patent Publication No. 2002-26100 (Patent Document 2) describes a method of providing a semiconductor product in a partial region in a semiconductor substrate.

  A contact chain including a first conductivity type substrate, a dielectric layer on the substrate, a plurality of contact means and two probe pads, wherein the contact means is electrically connected to the first conductivity type first doped layer. Japanese Patent No. 3654434 (Patent Document 3) describes a method for measuring the total contact resistance by measuring a probe pad when the substrate structure is provided and the substrate is not connected to the first doped layer. .

A step of moving to a first field associated with the first group of test structures, the first field including a portion of the first group of test structures; and scanning the first field. Determining whether or not there is a defect in the first group of test structures and, if it is determined that there is a defect in the first group of test structures, repeatedly moving to a plurality of regions Japanese Patent Application Publication No. 2004-501505 (Patent Document 4) describes a sample inspection method including a step of scanning a plurality of regions and determining a specific position in a test structure of a first group.
Japanese Unexamined Patent Publication No. 11-330181 (paragraphs [0017] to [0021], FIG. 2) JP 2002-26100 A (paragraph [0018], FIG. 1) Japanese Patent No. 3654434 (paragraphs [0018] to [0021], FIGS. 3 and 4) JP-T-2004-501505 (paragraphs [0048] to [0057], FIG. 3)

  In the test pattern design and defect inspection using the same, in the various devices used in the defect inspection, for example, grasping of the defect position performed by a scanning electron microscope, a focused ion beam device, a probe measuring device, a transmission electron microscope, etc. Specifically, a great deal of time is spent on counting the number of patterns for confirming the defect position. For example, the defect position is confirmed by counting the number of patterns from the end of the pattern group to the position of the defect to be physically analyzed. For this reason, if the number of patterns is mistaken, another defect existing in the vicinity or a normal part that is not a defect is physically analyzed, and a problem that a desired defect occurrence factor cannot be investigated arises.

  In physical analysis, for example, when taking an image of a defect with a scanning electron microscope, as a measure to ensure that the target defect is not mistaken, observe at a very low magnification until a characteristic pattern near the defect can be confirmed. At the same time, a characteristic pattern and a defect are imaged in the same field of view, and an enlarged image of the defect is also captured. However, when this measure is adopted, in addition to counting the number of patterns, it is necessary to perform operations such as imaging of defect images and creation of materials indicating defect positions, and the time required for defect analysis is further increased.

  Also, in the physical analysis of electrical defects called potential contrast defects, the image contrast decreases depending on the observation conditions or magnification of the analyzer, so that the defects themselves disappear and the physical location of the defects cannot be determined. There is a problem that it becomes impossible, or even if it can be specified, it takes time to count the number of patterns remarkably.

  An object of the present invention is to provide a technique capable of confirming the position of a failure portion in a short time during physical analysis in an in-line defect inspection process of a semiconductor device.

  Another object of the present invention is to provide a technique capable of detecting or observing a potential contrast defect with high sensitivity in an in-line defect inspection process of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  1. A method of manufacturing a semiconductor device according to the present invention includes a step of inspecting a defect generated in a manufacturing process of a semiconductor device by a test pattern, and a lower wiring and a first plug connected to the lower wiring on the main surface of the semiconductor substrate. And a test pattern in which a plurality of chain structure patterns in which the upper wiring connected to the first plug and the second plug connected to the upper wiring are repeated are formed, and the same layer as the upper wiring is formed in the wiring central portion of the test pattern. The separators formed by the wirings are arranged at regular intervals, and both ends of the region where the separators in the central part of the wiring are not formed are electrically connected via the same layer wiring as the lower wirings, A separator is used as an index for checking the position of the defect.

  2. A manufacturing method of a semiconductor device according to the present invention is the above-described 1. In the semiconductor device manufacturing method described above, a dummy pattern is formed using a wiring in the same layer as the upper wiring in a region where the separator is not formed.

  3. A manufacturing method of a semiconductor device according to the present invention is the above-described 1. In the semiconductor device manufacturing method described above, the separator is arranged in accordance with the inspection comparison interval of the inline defect inspection apparatus.

  4). A method of manufacturing a semiconductor device according to the present invention includes a step of inspecting a defect generated in a manufacturing process of a semiconductor device by a test pattern, and a lower wiring and a first plug connected to the lower wiring on the main surface of the semiconductor substrate. A test pattern in which a plurality of chain structure patterns in which upper wiring connected to the first plug and second plug connected to the upper wiring are repeated is formed, and the first plug, the second plug or the chain structure pattern A built-in potential contrast defect is formed by deleting a part of the lower wiring, and the detection rate of the built-in potential contrast defect is measured using an in-line defect inspection apparatus. The device state of the inline defect inspection apparatus is grasped, and the inspection conditions of the inline defect inspection apparatus are adjusted.

  5. The method of manufacturing a semiconductor device according to the present invention is the above-mentioned 4. In the semiconductor device manufacturing method described above, the inline defect inspection apparatus is an electron beam inspection apparatus.

  6). The method of manufacturing a semiconductor device according to the present invention is the above-mentioned 5. In the semiconductor device manufacturing method described above, the inspection conditions of the electron beam inspection apparatus are irradiation energy, electron beam current, and charging control voltage.

  7. A method of manufacturing a semiconductor device according to the present invention includes a step of inspecting a defect generated in a manufacturing process of a semiconductor device by a test pattern, and a lower wiring and a first plug connected to the lower wiring on the main surface of the semiconductor substrate. And a test pattern in which a plurality of chain structure patterns in which the upper wiring connected to the first plug and the second plug connected to the upper wiring are repeated are formed, and the same layer as the upper wiring is formed in the wiring central portion of the test pattern. The separators formed by the wirings are arranged at regular intervals, and both ends of the region where the separators in the central part of the wiring are not formed are electrically connected via the same layer wiring as the lower wirings, In addition, the first plug, the second plug, or a part of the lower wiring in the chain structure pattern in the region other than the central portion of the wiring is deleted to create a region other than the central portion of the wiring A potential contrast defect is formed, the detection rate of the built-in potential contrast defect is measured using an in-line defect inspection device, and the device state of the in-line defect inspection device is grasped from the detection rate of the built-in potential contrast defect. After adjusting the inspection conditions of the defect inspection apparatus, the position of the defect is confirmed using the separator as an index.

  8). The method of manufacturing a semiconductor device according to the present invention is the above-mentioned 7. In the semiconductor device manufacturing method described above, the inline defect inspection apparatus is an electron beam inspection apparatus.

  9. The manufacturing method of a semiconductor device according to the present invention is the above-mentioned 8. In the semiconductor device manufacturing method described above, the inspection conditions of the electron beam inspection apparatus are irradiation energy, electron beam current, and charging control voltage.

  10. The method of manufacturing a semiconductor device according to the present invention is the above-mentioned 7. In the semiconductor device manufacturing method described above, after the position of the defect is confirmed using a separator, a fiducial mark is formed in the vicinity of the defect.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the in-line defect inspection process of the semiconductor device, the position of the failure location can be confirmed in a short time during physical analysis. Further, in the in-line defect inspection process of the semiconductor device, the potential contrast defect can be detected or observed with high sensitivity.

  In this embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Some or all of the modifications, details, supplementary explanations, and the like are related.

  Further, in this embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified, or in principle limited to a specific number in principle. The number is not limited to the specific number, and may be a specific number or more. Further, in the present embodiment, it is needless to say that the constituent elements (including element steps and the like) are not necessarily indispensable, unless otherwise specified and clearly considered essential in principle. Yes. Similarly, in this embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise considered in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

  In the drawings used in the present embodiment, hatching may be added even in a plan view for easy understanding of the drawings. In this embodiment, the term “wafer” mainly refers to a Si (Silicon) single crystal wafer. However, not only that, but also an SOI (Silicon On Insulator) wafer and an integrated circuit are formed thereon. It refers to an insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
A basic configuration of the test pattern according to the first embodiment will be described with reference to FIGS. FIG. 1 is a plan view of a principal part of a test pattern according to the first embodiment, FIG. 2 is a wiring pattern observed with the test pattern according to the first embodiment, and FIGS. 3A and 3B are the present embodiment, respectively. The low-magnification image of the test pattern and the enlarged SEM (Scanning Electron Microscope) image in the vicinity of the defect part, which are shown in FIGS. It is the low-magnification image of the test pattern for demonstrating the conventional counting method of the number of separators which the inventor examined, and the enlarged SEM image near a defect part.

  As shown in FIG. 1, separators (basic wiring section separator 1, wiring central section separator 2, and wiring end that can confirm the positions of fault diagnosis locations in the basic wiring section, wiring central section, and wiring end section of the test pattern, respectively. A partial separator 3) is arranged. The wiring center portion separator 2 exposes the second wiring layer 4 on the surface by the length of the separator length L. In the other wiring center portion, the wiring end portion is connected to the wiring end via the first wiring layer 5. It is electrically connected to the part. For this reason, the other wiring central portion is in a state of being hidden from the surface of the second wiring layer 4 and is not observed as a wiring pattern. The separator length L is, for example, 10 μm, and the interval between the separator arrangement pitches P is, for example, 100 patterns. These various separators 1, 2, and 3 mounted on the test pattern serve as indexes for confirming the coordinate position of the defect when observing the defect.

  An example of the wiring pattern in the vicinity of the wiring center separator 2 observed from the surface of the second wiring layer 4 is shown in FIG. Only one second wiring layer 4 can be observed in the wiring center separator 2 at the interval of the separator arrangement pitch P in FIG. In the vicinity of the wiring center separator 2, the area where the wiring pattern does not exist continues over a wide range. Therefore, in the test pattern manufacturing process, for example, the CMP (Chemical Mechanical Polishing) polishing amount depending on the difference in pattern occupation density The difference may occur. Therefore, in the test pattern, it is desirable to arrange the dummy pattern 6 made of the second wiring layer 4 so that a difference in pattern occupation density does not occur.

  As described above, by arranging the various separators 1, 2, and 3 in the test pattern, it is possible to quickly search in which position the target defect exists in the defect observation or physical analysis. For example, as shown in FIG. 3A, the wiring center separator 2 can be observed even at a low magnification. When the wiring center separator 2 is arranged, for example, every 100 wiring patterns, the 15th wiring counted from the end of the test pattern corresponds to the 1500 actual wiring patterns. As shown in FIG. 3B, it can be confirmed that the defect position existing in the vicinity of the 1500th line is the 1499th from the relative position with respect to the 15th line of the wiring center separator 2.

  On the other hand, in the conventional method examined by the present inventor, as shown in FIG. 3 (c), since there is no separator, the number 1499 from the end of the test pattern is counted, and it is confirmed that there is a defect at that position. Must be confirmed when. At the same time as counting from the end of the test pattern, it is necessary to capture the low-magnification image shown in FIG. 3C and the enlarged SEM image shown in FIG. 3D as a schematic diagram for confirming the defect position. is there. If you do not perform these operations and specify the defect location using only the defect coordinate data, problems such as performing a probe measurement at the wrong position, performing a cross-sectional analysis at the wrong position, or evaluating different defects during physical analysis Will occur.

  However, as in the first embodiment, by mounting the separator on the test pattern, by counting 15 separators with low magnification observation, the defect position can be confirmed immediately, and with high magnification observation. Using the separator as an index, the position where the defect exists can be confirmed from the relative position. Even when counting with high magnification observation, as illustrated, every 100 separators are arranged, so it is not necessary to count the number of patterns of 100 or more at the maximum in order to confirm the defect position. Furthermore, by mounting the separator not only on the central part of the wiring but also on the main wiring part and the wiring end part, it is possible to easily confirm the defective position regardless of the position of the test pattern. As described above, according to the first embodiment, it is possible to reduce the time spent for the defect position confirmation work as compared with the conventional method.

  Since the main wiring part separator 1 and the wiring end separator 3 are arranged at the end of the test pattern, they can be excluded from the inspection area in the inline defect inspection. Further, since the wiring center separators 2 are arranged at a constant pitch, it is possible to inspect by setting only the wiring center part as an inspection area. The wiring center part is set as a non-inspection area. It is also possible to inspect by setting the wiring portion and the wiring end portion in one inspection region. Therefore, when performing inline defect inspection, it is possible to obtain a pattern configuration that enables inspection without causing disturbance of the image comparison pitch due to the arrangement of the separator, and in inline defect inspection and physical analysis. Test patterns that can be shared can be provided.

  Next, the basic wiring portion and via chain of the test pattern according to the first embodiment will be described with reference to FIGS. FIGS. 4A and 4B are a plan view and a cross-sectional view of the main part of the main wiring portion of the test pattern according to the first embodiment, respectively, and FIG. 5 is an enlarged view of the via chain of the test pattern according to the first embodiment. FIG. 6 is a plan view of a main part taken along the line AA ′ of FIG.

  As shown in FIGS. 4A and 4B, the test pattern has a main wiring portion including the main wirings 4a and 5a of the second wiring layer 4 and the first wiring layer 5, and the second wiring of the main wiring portion. The layer 4 (main wiring 4a) is formed in a predetermined region at constant intervals, and is connected to the first wiring layer 5 (main wiring 5a) via a plurality of first via plugs (first via plug group) 7. Furthermore, the first wiring layer 5 (main wiring 5a) of the basic wiring portion is formed in a predetermined region at a constant interval, and is connected to the semiconductor substrate 10 via a plurality of contact plugs (contact plug group) 8 and the p-type diffusion layer 9. ing. An example of the material of the contact plug 8 is tungsten. The contact plug 8 is embedded in the connection hole 11 via a barrier conductor film (for example, a laminated film in which a titanium nitride film is deposited on a titanium film) 12 covering the inner wall of the connection hole 11. Thus, the main wirings 4a and 5a are grounded in order to stabilize the image contrast when observing a potential contrast defect described later. Further, in order to obtain sufficient wiring capacity for the main wiring itself, for example, the width of the first wiring layer 5 (main wiring 5a) of the main wiring portion is 5.0 μm, and the width of the second wiring layer 4 (main wiring 4a) is It is set to 6.8 μm.

  A via chain configured to connect to the second wiring layer 4, the first via plug 7, the first wiring layer 5, the first via plug 7, and the second wiring layer 4 extending in a strip shape is formed from the main wiring portion. . FIG. 4A illustrates a double via structure in which two first via plugs 7 are connected to the first connection portion with the main wiring.

  As shown in FIGS. 5 and 6, the first wiring layer 5 constituting the via chain is made of a copper wiring formed by, for example, a single damascene method, and the second wiring layer 4 is formed by, for example, a dual damascene method. It consists of copper wiring. Under the copper wiring, for example, barrier conductor films 13a and 13b formed by laminating a tantalum nitride film and a tantalum film from the lower layer are formed, and a copper seed layer is formed between the copper wiring and the barrier conductor films 13a and 13b. Has been. The first liner film 14 formed below the first wiring layer 5 is, for example, a SiCN film (dielectric constant 5.0, film thickness 50 nm), and the second liner film 15 formed above the first wiring layer 5 is, for example, The SiCN film (dielectric constant 5.0, film thickness 30 nm) and the second interlayer insulating film 17 forming the wiring groove 16 for embedding the first wiring layer 5 are silicate glass (dielectric constant 4.3, film thickness 150 nm). is there. The third liner film 18 formed below the second wiring layer 4 includes, for example, a SiCO film (dielectric constant 4.5, film thickness 30 nm), wiring grooves 19 and connection holes 20 for embedding the second wiring layer 4 and the like. The third interlayer insulating film 21 to be formed is a SiOC film (dielectric constant 3.0, film thickness 440 nm). Note that the second interlayer insulating film 17 and the third interlayer insulating film are used to prevent poisoning (the generation of amine-based gas from the SiOC film, which is an interlayer insulating film having a low dielectric constant, causing poor photolithography resolution). The liner film between the films 21 has a two-layer structure in which the second liner film 15 and the third liner film 18 are stacked.

  In addition, since the interface between the second wiring layer 4 and the first via plug 7 can be sharply controlled without causing the shape collapse by the etching technique, there is no gap between the second wiring layer 4 and the first via plug 7. A manufacturing method of processing the wiring groove 19 by stopping the etching time without providing an etching stopper film was implemented, and the manufacturing process could be simplified. In addition, the various materials described in the first embodiment are materials used for manufacturing an actual test pattern for verifying and confirming the function of the test pattern. You may change thickness etc. suitably. For example, an etching stopper film is formed at the interface between the second wiring layer 4 and the first via plug 7, the second wiring layer 4 is composed of copper wiring formed by a single damascene method, and the copper wiring is aluminum wiring. Even if the conductor film 12 is formed of a laminated film in which a titanium film and a titanium nitride film are deposited from the lower layer, and the first via plug 7 is changed to a tungsten film, the basic function of the test pattern is not greatly changed.

  Next, a test pattern manufacturing method according to the first embodiment will be described with reference to cross-sectional views of relevant parts shown in FIGS.

  First, as shown in FIG. 7A, a high-concentration p-type diffusion layer 9 is formed by implanting p-type impurities into the surface of a semiconductor substrate 10 made of, for example, silicon single crystal. Subsequently, a first interlayer insulating film 22 whose surface is flattened is formed on the main surface of the semiconductor substrate 10, and then a contact plug 8 (FIG. 4) is formed at a predetermined position of the main wiring portion. Thereafter, a first liner film 14 and a second interlayer insulating film 17 are sequentially formed on the main surface of the semiconductor substrate 10.

  Next, the first wiring layer 5 is formed by a single damascene method. First, after forming a wiring groove 16 in a predetermined region of the second interlayer insulating film 17 and the first liner film 14 by dry etching using a resist pattern as a mask, a barrier conductor film 13a is formed on the main surface of the semiconductor substrate 10. To do. Subsequently, a copper seed layer is formed on the barrier conductor film 13a by a CVD method or a sputtering method, and a copper plating film is further formed on the copper seed layer by an electrolytic plating method. The inside of the wiring groove 16 is buried with a copper plating film. Subsequently, the copper plating film, the copper seed layer, and the barrier conductor film 13a in regions other than the wiring groove 16 are removed by CMP to form the first wiring layer 5 using the copper film as a main conductive material.

  Next, the second wiring layer 4 is formed by a dual damascene method. First, the second liner film 15, the third liner film 18, the third interlayer insulating film 21, the hard mask film 23, and the antireflection film 24 are sequentially formed on the main surface of the semiconductor substrate 10. Subsequently, a resist pattern 25 for forming a wiring groove is formed on the antireflection film 24. Subsequently, as shown in FIG. 7B, the antireflection film 24 and the hard mask film 23 are etched by dry etching using the resist pattern 25 for wiring trench formation as a mask.

  Next, as shown in FIG. 8A, after removing the resist pattern 25 for forming the wiring trench, an antireflection film 26 is formed on the main surface of the semiconductor substrate 10, and a connection hole is formed on the antireflection film 26. A resist pattern 27 for formation is formed. Subsequently, as shown in FIG. 8B, the third interlayer insulating film 21 is processed by dry etching using the resist pattern 27 for forming the connection hole as a mask. At this time, the third liner film 18 functions as an etching stopper.

  Next, as shown in FIG. 9A, after removing the resist pattern 27 for forming the connection hole and the antireflection film 26, wiring is performed on the third interlayer insulating film 21 by dry etching using the hard mask film 23 as a mask. A groove 19 is formed. At this time, since the third interlayer insulating film 21 does not have an etching stopper film serving as a boundary between the wiring groove 19 and the connection hole 20, the etching is controlled by stopping the time. Subsequently, the hard mask film 23 is removed as shown in FIG. 9B, and further, the third liner film 18 and the second liner film 15 under the connection hole 20 are dry-etched as shown in FIG. 9C. Remove. As a result, the copper film of the first wiring layer 5 is exposed at the bottom of the connection hole 20. The continuity test between the connection hole 20 and the first wiring layer 5 can be performed at this stage when the copper film of the first wiring layer 5 is exposed at the bottom of the connection hole 20. This continuity inspection can be performed using, for example, an electron beam inspection apparatus. That is, if the connection hole 20 is non-conductive due to insufficient etching, this portion can be detected as a potential contrast defect. The electron beam inspection apparatus will be described in detail in a second embodiment to be described later.

  Next, a second wiring layer 4 having a copper film as a main conductive material is formed inside the connection hole 20 and the wiring groove 19. A connecting member that connects the second wiring layer 4 and the first wiring layer 5 that is the lower layer wiring is formed integrally with the second wiring layer 4. First, the barrier conductor film 13 b is formed on the main surface of the semiconductor substrate 10 including the insides of the connection holes 20 and the wiring grooves 19. The barrier conductor film 13b is, for example, a laminated film in which titanium nitride is stacked on a titanium film. Subsequently, a copper seed layer is formed on the barrier conductor film 13b by a CVD method or a sputtering method, and a copper plating film is further formed on the copper seed layer by an electrolytic plating method. The insides of the connection holes 20 and the wiring grooves 19 are filled with the copper plating film. Subsequently, the copper plating film, the copper seed layer, and the barrier conductor film 13b in regions other than the connection hole 20 and the wiring groove 19 are removed by CMP to form the second wiring layer 4 using the copper film as a main conductive material. When the second wiring layer 4 is formed, a test pattern is inspected using an electron beam inspection apparatus. After the second wiring layer 4 is formed, a liner film, for example, a liner film in which a SiCO film (dielectric constant 4.5, film thickness 30 nm) is stacked on a SiCN film (dielectric constant 5.0, film thickness 30 nm). May be further formed to test the test pattern, and the same effect can be obtained.

  According to the first embodiment, the following effects can be obtained.

  (1) The effects obtained by providing the test pattern with separators (basic wiring section separator 1, wiring center section separator 2, and wiring end section separator 3) and the reason why the effects are obtained are as follows.

  The main wiring section separator 1 can be used as an index (marker) for confirming the position of a defect generated in the vicinity of the main wiring 4a. This is because the boundary between the main wiring 4a and the wiring pattern connected from the main wiring 4a is a rectangle wider than the width of the second wiring layer 4 constituting the wiring pattern, and this is used as the main wiring section separator 1. This is because it is possible to easily confirm the shape of the main wiring section separator 1 even at a low magnification, and it is possible to collectively count the unit of the separator arrangement pitch P.

  The wiring center separator 2 is arranged near the middle between the main wiring part separator 1 and the wiring end separator 3 and is used as an index (mark) for checking the position of a defect generated near the center of the test pattern. Can do. The wiring center separator 2 has a structure in which the second wiring layer 4 is extended by the separator length L for each separator arrangement pitch P, and the other parts are extended as a whole by extending the first wiring layer 5 by the separator length L. The second wiring layer 4 can be confirmed only by the wiring center separator 2. Therefore, by counting the second wiring layer 4 of the wiring center portion separator 2 by observation at a low magnification, only the unit of the separator arrangement pitch P can be counted.

  The wiring end separator 3 can be used as an index (mark) for confirming the position of a defect generated near the end of the test pattern. This is because the wiring end portion has a rectangular shape wider than the width of the second wiring layer 4 constituting the wiring pattern, and this is used as the wiring end separator 3 so that the shape of the wiring end separator 3 can be easily formed even at a low magnification. This is because it is possible to confirm the above and to collectively count the unit of the separator arrangement pitch P.

  (2) The reason why the separator is arranged so as not to interfere with the in-line defect inspection and can be shared with the physical analysis is as follows.

  Since the main wiring portion separator 1 and the wiring end portion separator 3 are arranged at the end portion of the test pattern, they can be out of the inspection area in the in-line defect inspection. Even when the main wiring portion separator 1 and the wiring end separator 3 are put in the inspection region, by setting the inspection pitch (interval for comparing inspection images) to be equal to or an integer multiple of the separator arrangement pitch P, Inspection can be performed without causing inconvenience. Generally, apparatuses that can set the inspection pitch as a range from 4 pixels to 128 pixels (that is, a range from 0.1 μm to 12.8 μm), or a range from 1 μm to 30 μm, are the mainstream. Therefore, by arranging the separator arrangement pitch P at an equal interval in the range of, for example, 1 μm to 30 μm, it is possible to include the main wiring part separator 1 and the wiring end part separator 3 in the inspection region and perform inline defect inspection. .

  Similarly, by setting the inspection pitch within the range of 1 μm to 30 μm, the wiring center separator 2 can be inspected even if the wiring center separator 2 is placed in the inspection region. Since the wiring center separators 2 are arranged at a constant pitch, it is possible to separately inspect the width of the separator length L shown in FIG. 1 as an inspection region. Even when the separator arrangement pitch P is set to be longer than 30 μm in order to reduce the counting time in the physical analysis, if the width of the separator length L is set in the non-inspection area, an inspection recipe is created in the inspection apparatus. Therefore, it is possible to set an inspection area and a non-inspection area without requiring much time, and to perform an in-line defect inspection without any trouble. At the same time, the wiring center separator 2 serves as an index for confirming the defect position even in the physical analysis, and can be used as a shared test pattern that works effectively.

  (3) In the test pattern manufacturing method, without forming the etching stopper film between the first via plug 7 and the second wiring layer 4, the wiring groove 19 and the connection hole 20 are formed by the dual damascene method. The manufacturing cost can be reduced by simplifying the process, and the disconnection probability between the first via plug 7 and the second wiring layer 4 can be reduced.

  (4) In the basic wiring portion of the test pattern, the second wiring layer 4 is connected to the first wiring layer 5 via the first via plug 7, and the first wiring layer 5 is further connected to the p-type diffusion layer via the contact plug 8. 9 is connected to a semiconductor substrate 10 having 9 on its surface. Accordingly, the main wiring portion is equivalent to the fact that both the first wiring layer 5 and the second wiring layer 4 are electrically grounded, and when the potential contrast defect is detected and observed using the electron beam inspection apparatus. Electrons can be constantly supplied from the grounded semiconductor substrate 10, and a high-contrast and stable potential contrast image can be obtained.

  (5) In the test pattern, by arranging the dummy pattern 6 made of the second wiring layer 4 around the wiring center separator 2, the wiring density difference is caused in the CMP process when the second wiring layer 4 is processed. The wiring center separator 2 can be manufactured without generating defects peculiar to CMP such as pattern disappearance, pattern defect, scratch (polishing scratch) or shape defect of the wiring center separator 2.

  (6) In the test pattern, by setting the widths of the main wirings 4a and 5a to 5.0 μm or more, it is possible to prevent the resolution of the main wirings 4a and 5a due to photolithography failure or the generation of foreign matter. Further, by adopting a double via structure at the initial connection between the main wirings 4a and 5a and the via chain, even if the wiring width at the connection boundary between the main wirings 4a and 5a and the via chain greatly changes, the photolithography solution It is possible to take protective measures against a disconnection caused by a change in image characteristics or a non-conduction occurring at the end of a via region.

(Embodiment 2)
A basic configuration of the built-in potential contrast defect mounted on the test pattern according to the second embodiment will be described with reference to FIGS. 10 is a plan view of the principal part of the built-in potential contrast defect according to the second embodiment, FIG. 11 is an enlarged plan view of the built-in potential contrast defect according to the second embodiment, and FIG. 12 is a line AA ′ in FIG. 13 is an enlarged plan view of another example of the built-in potential contrast defect according to the second embodiment, and FIG. 14 is a sectional view taken along the line AA ′ of FIG. Reference numeral 16 denotes a potential contrast of a wiring pattern having a built-in potential contrast defect when inspected by the electron beam inspection apparatus according to the second embodiment.

  As shown in FIGS. 10, 11 and 12, the built-in potential contrast defect has a structure in which the two first via plugs 7 are deleted from the test pattern. In FIG. 11, the deleted first via plug 7 is indicated by a dotted line. Further, as shown in FIGS. 13 and 14, the built-in potential contrast defect may have a structure in which the two first wiring layers 5 are deleted from the test pattern. In FIG. 13, the deleted first wiring layer 5 is indicated by a dotted line. Main interconnections 4 a and 5 a are connected from contact plug 8 to semiconductor substrate 10 through p-type diffusion layer 9, as in the first embodiment.

  When the test pattern is inspected using the electron beam inspection apparatus, as shown in FIG. 15, the potential contrast changes from the disconnection portion from which the two first via plugs 7 are removed to the wiring end portion. 28 can be detected.

  FIG. 16 shows a change in potential contrast from the main wiring portion to the wiring end portion, which appears when the built-in potential contrast defect 28 is formed. Since the second wiring layer 4 and the first wiring layer 5 are electrically connected via the first via plug 7, the wiring center separator 2 is connected to the wiring end portion by the disconnection state generated in the vicinity of the main wiring portion. It can be transmitted faithfully to the potential contrast.

  Although depending on the pattern size or surrounding material, the length that causes this potential contrast change is empirically less than 1.5 mm for copper wiring and less than about 3.0 mm for aluminum wiring. It is desirable to set. If the length is longer than that, the wiring capacitance is substantially equivalent to the ground at a location away from the disconnection, and the potential contrast gradually recovers and returns to the normal potential contrast as the distance from the disconnection increases. In the second embodiment, the two first via plugs 7 (or the two first wiring layers 5) are deleted in the disconnection portion. However, one first via plug 7 (or one first wiring layer 5) is deleted. May be deleted. However, in this case, the change appearing in the potential contrast becomes difficult to understand.

  Next, an inspection condition setting method using a built-in potential contrast defect mounted on a test pattern will be described with reference to FIGS. 17 is a schematic diagram of an electron beam inspection apparatus used as an inline defect inspection apparatus in the second embodiment, and FIG. 18 is an inspection condition for a built-in potential contrast defect inspected by the electron beam inspection apparatus according to the second embodiment. FIG. 19 is a graph showing the relationship between the potential contrast and the inspection conditions according to the second embodiment, and FIG. 20 illustrates a conventional method for inspecting a potential contrast defect examined by the present inventor. FIG. 21 is a diagram for explaining the problems of the conventional method for inspecting a potential contrast defect examined by the present inventor. FIG. 21A shows the detection rate of actual defects when the inspection conditions are set. (B) is a graph showing the relationship between the detection signal and the type of defect, (c) to (e) are distribution diagrams of defects on the semiconductor wafer, and FIG. 22 is created according to the second embodiment. Position is a process diagram illustrating a method of inspecting contrast defects.

  For the inspection of the built-in potential contrast defect in the second embodiment, an electron beam inspection apparatus shown in FIG. 17 was used. In the figure, 51 is an electron beam inspection device, 52 is an electron gun, 53 is a sample (semiconductor wafer), 54 is a reflector, 55 is a secondary electron detector, 56 is a secondary electron detection signal conversion circuit, and 57 is an image. An observation monitor, 58 is a secondary electron first image drawing circuit, 59 is a secondary electron second image drawing circuit, 60 is a comparison operation circuit, 61 is a defect determination processing circuit, 62 is an anode electrode, 63 is a lead electrode, 64 Is a condenser lens, 65 is an incident electron beam, 66 is a blanking deflector, 67 is a diaphragm, 68 is an E × B deflector, 69 is a scanning deflector, 70 is an objective lens, 71 is a sample height detector, 72x, 72y is an XY stage, 74 is a sample stage, 75 is a light source, 76 is an optical lens, 77 is a CCD camera, 78 is a condenser lens power supply, 79 is a scanning signal generator, 80 is an objective lens power supply, and 81 is a sample height measuring instrument. 82 Location monitor measuring machine, 83 the control unit circuit, 84 is a charge control electrode.

  As shown in FIG. 17, an incident electron beam (primary electron) 65 accelerated to 10 keV is incident from an electron gun 52 provided in an electron beam inspection apparatus 51 toward a sample 53, for example, a semiconductor wafer, disposed immediately below. However, in order to avoid electron beam damage to the surface of the sample 53 at the time of incidence, a negative voltage (−9.7 keV to −7.0 keV) is applied to the surface of the sample 53 by a retarding power source. Therefore, the incident electron beam 65 is decelerated in the vicinity of the surface of the sample 53, and irradiation energy of 0.3 keV to 3.0 keV is incident on the surface of the sample 53. The electron beam current value on the surface of the sample 53 can be set in the range of 30 nA to 150 nA.

  When the incident electron beam 65 is irradiated onto the surface of the sample 53 with the above irradiation energy, secondary electrons are generated from the surface of the sample 53. The secondary electron detector 55 captures the secondary electrons and processes them in a form converted into electrical signals by the secondary electron detection signal conversion circuit 56. In addition, by applying a positive voltage to the charge control electrode 84 provided immediately above the sample 53 so that the secondary electrons can be easily captured, the secondary electrons are pulled out to the detector 55 side, or conversely to the charge control electrode 84. The secondary electrons can be pushed back to the surface side of the sample 53 by applying a negative voltage. The charge control electrode 84 has a structure capable of applying a voltage (charge control voltage) of −6.0 kV to +6.0 kV.

  FIGS. 18A, 18B and 18C show potential contrasts obtained when the test conditions (inspection conditions A, B and C) of the electron beam inspection apparatus are changed and the test pattern is imaged. Typical inspection conditions are irradiation energy at the stage where primary electrons emitted from the electron gun of the electron beam inspection apparatus are irradiated onto the semiconductor wafer, and electron beam current at that stage.

  As inspection conditions used in the second embodiment, irradiation energy of 0.3 keV to 3.0 keV, electron beam current of 30 nA to 150 nA, and charging control voltage of −6.0 kV to +6.0 kV can be exemplified as setting ranges. . In general, an inspection condition is set by a combination of these three parameters. As shown in FIGS. 18A, 18B, and 18C, an inspection condition A having a low contrast by the combination of parameters, There are an inspection condition B for high contrast and an inspection condition C for contrast disappearance.

  FIG. 19 shows the potential contrast in the inspection conditions A, B, and C. As the potential contrast increases, the built-in potential contrast defect can be detected with high sensitivity. Here, it can be seen that the inspection condition B is the optimum condition. As described above, by changing the irradiation energy, the electron beam current, and the charging control voltage as parameters, it is possible to set a highly sensitive inspection condition using the built-in potential contrast defect.

  Next, a conventional inspection condition setting method studied by the present inventor will be described with reference to a process diagram shown in FIG.

  First, electron optical conditions (inspection conditions) are set (step A1). Here, the three parameters of irradiation energy, electron beam current, and charging control voltage are temporarily set with the electro-optical conditions used so far as the starting conditions. Next, before inspecting the entire surface of the semiconductor wafer, an inspection threshold (inspection sensitivity) is arbitrarily set using the electron optical conditions set in step A1, and a trial inspection is performed in a small area (step A2). Thereby, it is confirmed whether or not the electron optical conditions and the inspection threshold are appropriate. Here, if no actual defect is detected, the inspection threshold value is further adjusted to the high sensitivity side, and the trial inspection is performed again (step A3). If a real defect is not detected even with high sensitivity, the small area to be inspected may be changed.

  When a real defect is detected in the trial inspection in the small region, the electron optical condition is searched for using the detected real defect so as to obtain a higher image contrast (step A4). When the optimum electron optical conditions (the optimum combination of irradiation energy, electron beam current, and charging control voltage) are found, the inspection threshold is set so that no false alarm (pseudo defect) occurs, and the trial inspection is performed again (process) A5). If the detection rate of false information (pseudo defects) detected together with the actual defect is high, the inspection sensitivity is lowered and the detection rate of the actual defect is increased or adjusted so that only the actual defect is detected (step A6). . Thereafter, the entire surface of the semiconductor wafer is inspected (large area inspection) (step A7), and a series of inspection work is completed.

  However, in the conventional inspection condition setting method, there are many work steps, and there is a problem that it takes a lot of time to create the optimum inspection condition. In addition, since the optimum inspection conditions are set using actual defects, the conventional inspection condition setting method is not a technique that can set inspection conditions with high sensitivity in any apparatus state. Hereinafter, the basis will be described with reference to FIG.

  FIG. 21A is a graph showing a state in which the defect detection function of the inspection apparatus has changed over time. Although the actual defect detection rate cannot actually be measured correctly, it is assumed that the ideal state is 100%. At this time, in the ideal state, as shown in FIG. 21B, defect types from defect A to defect F exist in the semiconductor wafer in each inspection signal I, and the defect distribution is shown in FIG. Assume that As shown in FIG. 21 (a), the detection rate of actual defects in the same inspection apparatus decreased to 40% in the period β from the state in which an inspection apparatus had an actual defect detection rate of 80% in the period α. Assume a case. Since the inspection recipe created by setting the inspection conditions in the period α can detect a weak detection signal, the inspection threshold can be set on the high sensitivity side as shown in FIG. Inspection threshold value α) indicated by a broken line, which is described as “condition setting in period α”. When the same semiconductor wafer is inspected using this inspection recipe, the defect F is missed as shown in FIG. 21D, but the defects A to E can be detected.

  However, since the inspection recipe created by setting the inspection conditions in the period β shown in FIG. 21A has a bad apparatus state, the weak detection signal is buried in the noise component, and the inspection shown in FIG. The inspection sensitivity must be set at the threshold value β (inspection threshold value β in the broken line portion indicated as “condition setting in period β”). For this reason, only the defect C and the defect E having large detection signals can be detected, and the inspection result shown in FIG. As described above, it has been found that the above-described problems occur in the conventional inspection condition setting method.

  However, if the built-in potential contrast defect is mounted in the test pattern in advance, since the detection signal intensity of the defect and the coordinates where the defect exists are known, it is possible to determine the current state of the inspection apparatus. It can be grasped as a unified indicator. Next, an inspection condition setting method using a built-in potential contrast defect according to the second embodiment, which can solve the problems of the conventional inspection condition setting method, will be described with reference to the process diagram shown in FIG. .

  First, the stage on which the semiconductor wafer is mounted is moved directly under the electron beam of the electron beam inspection apparatus shown in FIG. Then, the electro-optic condition is searched up to the condition (optimum electro-optic condition) at which the highest contrast image is obtained using the built-in potential contrast defect (step B1). When the optimum electron optical condition is obtained, the inspection threshold value is changed under the optimum electron optical condition, and the inspection threshold value is adjusted so that the detection rate of the built-in potential contrast defect becomes 100% (step B2). . When the target detection rate is reached, a trial inspection is performed in a small area for confirmation (step B3). When the detection rate of false information (pseudo defects) detected together with actual defects in this trial inspection is high, the inspection threshold is adjusted to the low sensitivity side and the trial inspection is performed again (step B4). When only actual defects or a predetermined false alarm rate is reached, inspection (large area inspection) is performed on the entire surface of the semiconductor wafer (step B5), and a series of inspection operations is completed.

  In the inspection condition setting method according to the second embodiment shown in FIG. 22, in addition to the reduction in the number of steps, a built-in potential contrast defect is used, so that the current apparatus state and defect detection state are always maintained. It can be grasped as the detection rate of the potential contrast defect by making what level. In addition, as in the conventional inspection condition setting method, without performing the inefficient operation of continuing the test inspection until the actual defect is detected, the process immediately moves to the place of the built-in potential contrast defect, and the inspection condition There is an advantage that the setting work can be started.

  Next, a method for checking the defect detection sensitivity using the built-in potential contrast defect will be described with reference to FIG. FIG. 23 is a schematic diagram for explaining a method for managing the detection sensitivity of a built-in potential contrast defect according to the second embodiment, and FIG. 23A is a graph showing the transition of the detection rate of the built-in potential contrast defect. ) To (d) are distribution diagrams of detected built-in potential contrast defects on the semiconductor wafer.

  In the conventional inspection method for defect detection sensitivity investigated by the present inventors, a silicon nitride film is formed on a silicon substrate, and a shape defect is processed by an etching technique. Both the electron beam inspection apparatus and the electron beam inspection apparatus used this built-in pattern defect. However, the main purpose of the electron beam inspection apparatus is to detect an electrical defect called a potential contrast defect as described above, and the conventional defect detection sensitivity inspection method detects a built-in pattern defect. Even if the sensitivity can be inspected, the detection sensitivity of the potential contrast defect is not inspected. In this respect, the inspection of the detection sensitivity of the potential contrast defect can be said to be in an uninspected state.

  However, by using the test pattern on which the built-in potential contrast defect illustrated in FIG. 10 is mounted, it is possible to check the detection sensitivity of the potential contrast defect that has not been performed so far. The inspection method is shown in FIG.

  FIG. 23 shows an example of a method for checking the detection sensitivity of a potential contrast defect using a test pattern having a built-in potential contrast defect. Actually, in the semiconductor wafer, four built-in potential contrast defects are mounted at predetermined intervals on a predetermined position of one chip for 153 chips (a total of 612 built-in defects in the semiconductor wafer). Equipped with potential contrast defect).

  FIG. 23A shows the transition of the detection rate of the built-in potential contrast defect. When all the built-in potential contrast defects are detected, the detection rate Di of the built-in potential contrast defects is 100%, and the distribution is as shown in FIG. Here, in the inspection recipe, the vicinity of a predetermined built-in potential contrast defect portion is set as an inspection region. Using this inspection recipe, an in-line defect inspection apparatus, for example, the electron beam inspection apparatus shown in FIG. Perform an inspection. A value obtained by dividing the number of detections of only the built-in potential contrast defect obtained from the inspection data based on the coordinates of the built-in potential contrast defect by the total number of the built-in potential contrast defect is defined as a detection rate. As an actual example, when 550 built-in potential contrast defects are detected on the entire surface of the semiconductor wafer, the detection rate Di of the built-in potential contrast defects is 89.9% when divided by a total of 612.

  With the above method, the detection sensitivity check result can be graphed as shown in FIG. Here, in the period γ, the defect distribution shown in FIG. 23B with the detection rate Di = 89%, and in the period δ, the defect distribution shown in FIG. 23C with the detection rate Di = 73%. A device state relating to the detection sensitivity of the device can be created and grasped as a change in detection rate of potential contrast defects.

  For example, when the management value of the detection rate of the built-in potential contrast defect is 80%, the management value is out of the period δ that is less than 80%, and measures such as adjusting the sensitivity of the inspection apparatus are taken. I will do it. After the adjustment, in the period ε, the detection rate Di = 100%, and the defect distribution shown in FIG. Can do.

  Next, a fault diagnosis method using a test pattern for diagnosing electrical faults equipped with built-in potential contrast defects for adjusting potential contrast defects to be observed at high contrast during physical analysis This will be described with reference to FIGS. FIGS. 24 to 26 are schematic diagrams showing an example of a procedure for confirming a potential contrast defect position in physical analysis in a short time using the separator of the present invention described in the first embodiment, and FIG. Is a process diagram of the above procedure, and FIG. 28 is a process diagram of a procedure for confirming a potential contrast defect position in the conventional physical analysis studied by the present inventors.

  First, inspection is performed using an inline defect inspection apparatus, for example, the electron beam inspection apparatus shown in FIG. 17 and the test pattern presented in the first embodiment, and a built-in potential contrast defect is detected (step of FIG. 27). C1). Here, it can be exemplified that the inspection conditions of the electron beam type inspection apparatus can be adjusted within the range of irradiation energy of 0.3 keV to 3.0 keV and the electron beam current value of 30 nA to 150 nA. In the second embodiment, a device in which a charge control electrode is mounted on the structure of the electron beam inspection device shown in FIG. 17 is used, and the charge control voltage at that time is in the range of −6.0 kV to +6.0 kV. It is possible to exemplify that adjustment is possible.

  Next, as shown in FIG. 24A, among the detected potential contrast defects, defect observation is performed on the potential contrast defect 32 to be subjected to physical analysis, and the potential contrast defect 32 and the vicinity of the physical analysis target defect are observed. The positional relationship with an existing separator (hereinafter referred to as a target separator) 31 is grasped (step C2 in FIG. 27).

  Next, as shown in FIG. 24B, low-magnification SEM observation or OM (Optical Microscope) observation is performed to count the target separator 31 from the end of the inspection region (step C3 in FIG. 27). ). For example, it is confirmed that the number of target separators 31 existing in the vicinity of the potential contrast defect 32 of the physical analysis target shown in FIG. To do. 24 (a) and 24 (b) can be adjusted in the same range of irradiation energy, electron beam current value, and charging control voltage by the electron beam inspection apparatus. In addition, the potential contrast defect 32 can be observed with an electron beam current of 1 nA. After confirming that the target separator 31 is the fifteenth, the semiconductor wafer is unloaded from the electron beam inspection apparatus.

  Next, as shown in FIG. 24 (c), the semiconductor wafer is loaded into a processing apparatus such as a focused ion beam apparatus (FIB) and counted up to the 15th separator by low-magnification observation. The portion of the target separator 31 is enlarged, and the positional relationship between the target separator 31 and the potential contrast defect 32 is confirmed again (step C4 in FIG. 27).

  Next, as shown in FIG. 25A, a reference mark (hereinafter referred to as fiducial mark 33) is attached so that the position where the physical analysis is performed can be more clearly confirmed (step C5 in FIG. 27). At this time, the sample is cut into a groove shape with a Ga ion beam or the like. Although the shape of processing is arbitrary, in this Embodiment 2, it was set as "x mark" of the length of 200 micrometers of one side and the groove width of 6 micrometers as shown to Fig.25 (a). Further, the lateral fiducial mark 33 is set to “−”, and is processed by changing the width in three steps of, for example, a width of 6 μm, a width of 3.6 μm, and a width of 0.26 μm as the potential contrast defect 32 is approached. . Examples of the setting range of the focused ion beam apparatus include an acceleration voltage of 10 to 40 keV, a processing current of 10 pA to 100 pA, and an observation current of 1 pA. The resolution at the time of observation can be up to about 6 nm.

  24 (c) and 25 (a) (steps C4 and C5 in FIG. 27), a scanning electron microscope such as a length measurement SEM (CD-SEM) or a review SEM (defect observation SEM) is used as an auxiliary. May be. In the case of length measurement SEM observation, an irradiation energy of about 0.5 keV to 1.0 keV and an electron beam current value of about 10 pA can be exemplified. In the case of a review SEM, an irradiation energy of 1 keV and an electron beam current of about 50 pA can be exemplified. Instead of the fiducial mark 33 shown in the second embodiment, carbon contamination generated by irradiating an electron beam for a long time may be used as a mark for confirming the position of the potential contrast defect 32. Note that these operations can be performed using a dual beam FIB / SEM apparatus in which a focused ion beam apparatus and a scanning electron microscope are integrated.

  Next, as shown in FIG. 25B, after the fiducial mark 33 is processed, the vicinity of the potential contrast defect 32 is observed at a high magnification in the focused ion beam apparatus to confirm that there is no problem in the processing. . At this time, when observing with a SIM (Scanning Ion Microscope) image, the surface of the sample is positively charged by the irradiation of the Ga ion beam, so that the potential contrast defect 32 of disconnection or non-conduction failure is observed with a higher contrast than that of the SEM image. can do. Thereafter, the semiconductor wafer in the focused ion beam apparatus is unloaded.

  From here, physical analysis is actually started. After unloading the semiconductor wafer from the focused ion beam apparatus, the semiconductor wafer is cut into approximately 20 mm square pieces in order to load the sample to the probe measurement apparatus (microdevice characteristic evaluation apparatus). After the fragmentation, as shown in FIG. 25 (c), the sample is loaded into the probe measuring apparatus, and the positional relationship between the target separator 31 and the fiducial mark 33 in the optical microscope image (OM image) of the probe measuring apparatus is determined. As shown in FIG. 26A, the SEM is shifted to a high-magnification image, and the vicinity of the target separator 31 is enlarged and probe measurement of the potential contrast defect 32 is performed (step C6 in FIG. 27).

  At this time, examples of the SEM image observation condition setting range include an acceleration voltage of 0.5 keV to 5.0 keV and a current value of 10 pA to 100 pA. At the time of implementation by the present inventor, for example, observation and measurement were performed using observation conditions of an acceleration voltage of 2 keV and a current value of 26 pA. In the observation of the SEM image under this condition, the potential contrast defect 32 disappeared. However, since the position of the potential contrast defect 32 from the target separator 31 was grasped, the probe measurement could be performed without any trouble.

In FIG. 26A, current-voltage measurement is performed using a tungsten probe 34 having a tip radius of about 50 nm. For example, it was possible to measure the resistance value of the first via plug of the test pattern, and it was possible to obtain a resistance value of about 100Ω at a normal via plug location and about 10 ¹¹ Ω (100 GΩ) at a non-conductive via plug location.

  Although it has been described that the potential contrast defect 32 has disappeared under the above-described conditions of the probe measuring apparatus (micro device characteristic evaluation apparatus), a scanning electron microscope such as a review SEM apparatus is used at the stage of FIG. When the potential contrast defect 32 is observed using the wiring layer, the wiring layer may be observed dark and the potential contrast defect 32 may be observed brightly. FIG. 26 (b) shows a schematic diagram thereof. This phenomenon is called “contrast reversal” and indicates that the sample surface is in a negatively charged state. Even in the case of FIG. 26B, the position of the potential contrast defect 32 can be easily specified using the target separator 31 at the time of implementation, and the physical analysis can be performed satisfactorily.

  In addition, since the built-in potential contrast defect is included in the small piece even during the physical analysis described above, when the potential contrast of the actual defect is lowered, the electron having a high contrast at the position of the built-in potential contrast defect in FIG. After adjusting the optical conditions by changing the conditions within the variable range of each device, it is possible to observe the potential contrast defect of the physical analysis object with higher contrast by moving to the position of the actual defect.

  Thereafter, the sample is unloaded from the probe measuring device, and the collected sample is thinned and mounted on a transmission electron microscope (TEM) as shown in FIG. (Step C7 in FIG. 27). FIG. 26C shows a cross-sectional observation example of the non-conductive via plug.

  Next, in order to confirm the effect of the above method, a conventional method studied by the present inventor will be described with reference to FIG. 3 and FIG. FIG. 28 is a process diagram of the conventional method.

  First, defect inspection is performed using a conventional test pattern in which a separator as shown in FIG. 3C is not mounted and the electron beam inspection apparatus exemplified in FIG. 17 (step D1 in FIG. 28). . Here, the physical analysis procedure for the potential contrast defect is shown. However, as in the case of FIG. 27, it is possible to analyze a foreign substance or a pattern defect in the same procedure.

  Next, the number of patterns from the potential contrast defect position to the end of the region of the test pattern is counted (step D2 in FIG. 28). This work is done later through different devices when performing physical analysis using various physical analysis devices, and because the sample is fragmented, the defect coordinate data obtained by the inspection device is shared between each device This is an operation for making it possible to correctly confirm the potential contrast defect position by counting the number of patterns. FIG. 3C shows an example in which the number of 1499 patterns from the edge of the test pattern region to the potential contrast defect position is counted by an electron beam inspection apparatus.

  Next, a high-magnification SEM image (FIG. 3D), a low-magnification SEM image, and an OM (optical microscope) image are captured using an electron beam inspection apparatus, and the potential contrast defect position is confirmed during physical analysis. 28 (for example, information describing information such as each image and the potential contrast defect position included in the image, the number of patterns from the edge of the test pattern region to the potential contrast defect), and the like (step shown in FIG. 28). D3). Here, the optical microscope image is captured by the CCD camera by moving the sample stage on which the semiconductor wafer is mounted directly under the light source installed beside the lens barrel of the electron beam inspection apparatus shown in FIG. It is possible to capture as a video.

  This conventional method of counting the number of patterns is to reach the potential contrast defect position even if a low-magnification SEM image and OM image are prepared so that the state of the surrounding pattern arrangement can be confirmed by the above method. However, since there is only a method by counting the number of patterns, in terms of shortening the analysis time and counting accuracy, the actual number is limited to several hundreds, and the potential contrast that has actually occurred near the center of the test pattern It is difficult to perform physical analysis of defects, and physical analysis can be performed only on potential contrast defects generated at the end of the test pattern.

  In the subsequent processes, physical analysis will proceed with each of the focused ion beam apparatus (or scanning electron microscope), probe measurement apparatus (micro device characteristic evaluation apparatus), and transmission electron microscope. However, after counting the number of test patterns with the focused ion beam device (step D4 in FIG. 28) and processing the fiducial mark 33 (step D5 in FIG. 28), the sample is fragmented and transferred to the probe measuring device. Even at this stage, it is necessary to count the number of test patterns (step D6 in FIG. 28). After all, in the process diagram shown in FIG. 28, pattern counting is performed in the process D2, the process D4, and the process D6, and the pattern from the edge of the test pattern to the potential contrast defect position is always at least once in each apparatus. The work of counting will occur. Here, the work of counting the number of 1499 patterns as shown in FIG. 3C in each step is a major factor in increasing the physical analysis time. After the above conventional method has been completed, the transmission electron microscope sample is prepared and the cross section of the defect is observed (step D7 in FIG. 28), and the series of physical analysis operations is completed.

  Here, the main points of the second embodiment will be compared using the conventional method described above and FIG. In the conventional method, as shown in FIG. 3C, it takes a long time to count 1499 patterns from the end of the test pattern, and the possibility of counting errors increases. Further, in the defect analysis near the center of the test pattern, even when expanding to the potential contrast defect position, there is no pattern serving as an index around, so a low-magnification SEM image and OM image for confirming the potential contrast defect position in advance. It was necessary to prepare a potential error defect position for physical analysis so as not to be misidentified.

  Therefore, in order to reduce the time spent on these in effect, defects existing at the end of the test pattern are often selected for physical analysis, for example, a defect occurring near the center of the test pattern. There has been a situation where it is impossible to extract a potential contrast defect as a physical analysis target from a desired potential contrast defect position.

  However, by mounting the separator according to the present invention on the test pattern, it is possible to reduce the time spent for pattern counting in units of the separator arrangement pitch P. In addition, since the number of separators can be easily counted even at low magnification observation, for example, the potential contrast defect position shown in FIG. 3C can be obtained only by counting the separator as illustrated in FIG. Immediately, the vicinity of the potential contrast defect can be reached. Then, when the separator arrangement pitch P is set to the number of 100 patterns by the high-magnification SEM image shown in FIG. 3 (b) in an enlarged manner, it exists to the right by one of the fifteenth separators. It can be easily confirmed in a short time that the 1499th position is a defect position.

  According to the second embodiment, the following effects can be obtained.

  (1) The built-in potential contrast defect 28 as shown in FIG. 16 can be manufactured by the structure of FIG. As shown in FIGS. 10 to 12, the built-in potential contrast defect 28 is obtained by removing the first via plug 7, thereby causing the second wiring layer 4, the first via plug 7, the first wiring layer 5, and the p-type in FIG. 4. The electron supply path of the semiconductor substrate 10 having the diffusion layer 9 is interrupted. Therefore, the via chain from the removed portion to the end portion from which the first via plug 7 of FIG. 10 is removed is in an electrically floating state (floating state). For example, when the electron beam inspection apparatus shown in FIG. As shown in FIG. 4, a potential contrast change portion can be intentionally generated. The built-in potential contrast defect 28 can be manufactured in the same manner by removing the first wiring layer 5 as shown in FIGS.

  (2) By mounting the built-in potential contrast defect 28 at a predetermined interval at the separator position, as shown in FIG. 16, for example, FIG. It is possible to easily grasp the mounting position of the built-in potential contrast defect 28 using the electron beam inspection apparatus shown.

  (3) By mounting the built-in potential contrast defect 28 shown in FIG. 10, for example, an inspection for creating an inspection recipe for detecting a potential contrast defect using the electron beam inspection apparatus shown in FIG. Conditions can be easily set. As shown in FIG. 18, this is because the built-in potential contrast defect 28 is used to change the setting of the inspection conditions of the electron beam inspection apparatus, thereby creating the built-in potential contrast among the inspection conditions A, B and C. This is because the optimum inspection condition can be set by selecting the inspection condition of FIG. 18B in which the image contrast of the defect 28 is the highest, that is, the inspection condition B of FIG. Here, the inspection condition refers to a condition determined by a combination of parameters of each electron optical condition such as irradiation energy, electron beam current, and charging control voltage.

  (4) By mounting the built-in potential contrast defect 28 shown in FIG. 10, the apparatus state relating to the detection sensitivity of the electron beam inspection apparatus shown in FIG. It is also possible to check as shown in FIG. This is because, by grasping in advance the total number of built-in potential contrast defects 28 on the entire surface of the semiconductor wafer, the number of built-in potential contrast defects 28 actually detected is divided by the total number of built-in potential contrast defects 28. This is because the detection rate of the built-in potential contrast defect 28 can be calculated.

  (5) At the physical analysis stage shown in FIG. 3 and FIGS. 24 to 26, using the separator shown in the first embodiment, the trouble of counting the number of patterns each time the sample is observed and measured between the apparatuses. Can be greatly reduced. This is because it is only necessary to count the number of separators with the separator arrangement pitch P as a unit. At this time, depending on the analysis device, the potential contrast defect frequently disappears or the contrast becomes low. However, as shown in FIG. 10, the built-in potential contrast defect 28 whose defect coordinates are known in advance is used. By observing the target defect after changing the observation conditions of the target device and setting the conditions for high contrast, it is possible to observe the potential contrast defect with high contrast under the optimal observation conditions for each target analysis device. . In addition, since the potential contrast defect to be analyzed can be observed with high contrast, the measurement of the potential contrast defect position grasped by the separator and the confirmation of the potential contrast defect position by processing of the fiducial mark can be performed more reliably. The potential contrast defect position to be analyzed can be visually confirmed.

  (6) The effects described above have been described by exemplifying the first wiring layer 5, the first via plug 7, and the second wiring layer 4. However, the third wiring layer, the wiring layer above it, Since it is possible to carry out the same reason for the via plug and the upper via plug, the same effect can be confirmed. In addition, it can be easily guessed that the separator and the built-in potential contrast defect 28 shown in the present invention can be manufactured without a via chain structure. The separator, the fiducial mark 33, the built-in potential contrast defect 28, and the test pattern are examples, and the material, shape, manufacturing method, execution procedure, and the like are not limited to the second embodiment. Modifications and improvements can be made without departing from the content.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The method for manufacturing a semiconductor device of the present invention can be used in a defect inspection process performed in the process of manufacturing a semiconductor device.

It is a principal part top view of the test pattern by this Embodiment 1. FIG. It is a wiring pattern observed with the test pattern by this Embodiment 1. FIG. (A) and (b) are a low-magnification image of a test pattern and an enlarged SEM image in the vicinity of a defect portion, respectively, for explaining the method of counting the number of separators according to the first embodiment, and (c) and (d) are books, respectively. It is the low-magnification image of the test pattern for demonstrating the conventional counting method of the number of separators which the inventor examined, and the enlarged SEM image near a defect part. (A) And (b) is the principal part top view and principal part sectional drawing of the basic wiring part of the test pattern by this Embodiment 1, respectively. 6 is an enlarged plan view of a via chain of a test pattern according to the first embodiment. FIG. It is principal part sectional drawing in the AA 'line of FIG. FIG. 6 is a main-portion cross-sectional view of the semiconductor device showing the test pattern manufacturing method according to the first embodiment; FIG. 6 is a main-portion cross-sectional view of the semiconductor device showing the test pattern manufacturing method according to the first embodiment; FIG. 6 is a main-portion cross-sectional view of the semiconductor device showing the test pattern manufacturing method according to the first embodiment; It is a principal part top view of the built-in potential contrast defect by this Embodiment 2. FIG. It is an enlarged plan view of a built-in potential contrast defect according to the second embodiment. It is principal part sectional drawing in the AA 'line of FIG. It is an enlarged plan view of another example of the built-in potential contrast defect according to the second embodiment. It is principal part sectional drawing in the AA 'line of FIG. This is a potential contrast of a wiring pattern having a built-in potential contrast defect when inspected by the electron beam inspection apparatus according to the second embodiment. This is a potential contrast of a wiring pattern having a built-in potential contrast defect when inspected by the electron beam inspection apparatus according to the second embodiment. It is the schematic of the electron beam type | mold inspection apparatus used in this Embodiment 2. FIG. This is a potential contrast when the inspection condition of the built-in potential contrast defect inspected by the electron beam inspection apparatus according to the second embodiment is changed. It is a graph which shows the relationship between the electric potential contrast by this Embodiment 2, and test | inspection conditions. It is process drawing explaining the inspection method of the conventional real defect which this inventor examined. It is a figure explaining the problem of the inspection method of the conventional actual defect which this inventor examined, Comprising: (a) is a graph figure which shows the detection rate of an actual defect when setting inspection conditions, (b) is detection The graph which shows the relationship between a signal and the kind of defect, (c)-(e) is a distribution map of the defect on a semiconductor wafer. It is process drawing explaining the inspection method of the built-in potential contrast defect by this Embodiment 2. FIG. It is a figure explaining the management method of the detection sensitivity of the built-in potential contrast defect by this Embodiment 2, Comprising: (a) is a graph which shows transition of the detection rate of a built-in potential contrast defect, (b)-(d ) Is a distribution map of detected built-in potential contrast defects on a semiconductor wafer. It is a principal part schematic diagram which shows from the in-line test | inspection of the built-in potential contrast defect by this Embodiment 2 to a physical analysis. It is a principal part schematic diagram which shows from the in-line test | inspection of the built-in potential contrast defect by this Embodiment 2 to a physical analysis. It is a principal part schematic diagram which shows from the in-line test | inspection of the built-in potential contrast defect by this Embodiment 2 to a physical analysis. It is process drawing explaining the flow from an in-line inspection regarding a potential contrast defect by this Embodiment 2 to a physical analysis. It is process drawing explaining the flow from the in-line test | inspection regarding the conventional potential contrast defect which this inventor examined to physical analysis.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Main wiring part separator 2 Wiring center part separator 3 Wiring edge part separator 4 2nd wiring layer 4a Main wiring 5 1st wiring layer 5a Main wiring 6 Dummy pattern 7 1st via plug 8 Contact plug 9 P type diffused layer 10 Semiconductor substrate ( Silicon substrate)
11 connection hole 12, 13a, 13b barrier conductor film 14 first liner film 15 second liner film 16 wiring groove 17 second interlayer insulating film 18 third liner film 19 wiring groove 20 connection hole 21 third interlayer insulating film 22 first Interlayer insulating film 23 Hard mask film 24 Antireflection film 25 Resist pattern 26 Antireflection film 27 Resist pattern 28 Built-in potential contrast defect 29 Semiconductor wafer 30 Notch 31 Target separator 32 Potential contrast defect 33 Fiducial mark 34 Probe 51 Electron beam type Inspection device 52 Electron gun 53 Sample (semiconductor wafer)
54 Reflector 55 Secondary Electron Detector 56 Secondary Electron Detection Signal Conversion Circuit 57 Image Observation Monitor 58 Secondary Electron First Image Drawing Circuit 59 Secondary Electron Second Image Drawing Circuit 60 Comparison Calculation Circuit 61 Defect Determination Processing Circuit 62 Anode electrode 63 Extraction electrode 64 Condenser lens 65 Incident electron beam 66 Blanking deflector 67 Aperture 68 E × B deflector 69 Scanning deflector 70 Objective lens 71 Sample height detector 72x, 72y XY stage 74 Sample stage 75 Light source 76 Optical Lens 77 CCD camera 78 Condenser lens power supply 79 Scanning signal generator 80 Objective lens power supply 81 Sample height measuring device 82 Position monitor length measuring device 83 Control unit circuit 84 Charging control electrode L Separator length P Separator arrangement pitch

Claims (5)

A method for manufacturing a semiconductor device comprising a step of inspecting a defect generated in a manufacturing process of a semiconductor device by a test pattern,
A chain structure pattern in which a lower wiring, a first plug connected to the lower wiring, an upper wiring connected to the first plug, and a second plug connected to the upper wiring are repeated on the main surface of the semiconductor substrate. Is formed, a separator formed by wiring in the same layer as the upper wiring is arranged at a certain interval in the wiring central portion of the test pattern, and the separator in the wiring central portion is formed. Both ends of the region that is not electrically connected via the wiring in the same layer as the lower wiring,
A method of manufacturing a semiconductor device, wherein the separator is used as an index for checking the position of the defect. A method for manufacturing a semiconductor device comprising a step of inspecting a defect generated in a manufacturing process of a semiconductor device by a test pattern,
A chain structure pattern in which a lower wiring, a first plug connected to the lower wiring, an upper wiring connected to the first plug, and a second plug connected to the upper wiring are repeated on the main surface of the semiconductor substrate. Is formed, a built-in potential contrast defect is formed by deleting a part of the first plug, the second plug or the lower wiring of the chain structure pattern,
Measure the detection rate of the built-in potential contrast defect using an in-line defect inspection device, grasp the device state of the in-line defect inspection device from the detection rate of the built-in potential contrast defect, and inspect the inspection conditions of the in-line defect inspection device A method for manufacturing a semiconductor device, characterized in that: A method for manufacturing a semiconductor device comprising a step of inspecting a defect generated in a manufacturing process of a semiconductor device by a test pattern,
A chain structure pattern in which a lower wiring, a first plug connected to the lower wiring, an upper wiring connected to the first plug, and a second plug connected to the upper wiring are repeated on the main surface of the semiconductor substrate. Is formed, a separator formed by wiring in the same layer as the upper wiring is arranged at a certain interval in the wiring central portion of the test pattern, and the separator in the wiring central portion is formed. Both ends of the region that is not electrically connected via the wiring in the same layer as the lower wiring,
Further, by removing a part of the first plug, the second plug or the lower wiring in the chain structure pattern in a region other than the central portion of the wiring, a potential contrast defect is created in a region other than the central portion of the wiring. Formed,
The detection rate of the built-in potential contrast defect is measured using an in-line defect inspection device, the device state of the in-line defect inspection device is grasped from the detection rate of the built-in potential contrast defect, and the inspection conditions of the in-line defect inspection device After the adjustment, the position of the defect is confirmed using the separator as an index.   4. The method of manufacturing a semiconductor device according to claim 2, wherein the in-line defect inspection apparatus is an electron beam inspection apparatus.   4. The method of manufacturing a semiconductor device according to claim 3, wherein a fiducial mark is formed in the vicinity of the defect after the position of the defect is confirmed using the separator as an index.

Images