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US10924094B1 - Pulse width modulation control circuit and control method of pulse width modulation signal - Google Patents

Pulse width modulation control circuit and control method of pulse width modulation signal Download PDF

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Publication number
US10924094B1
US10924094B1 US16/558,333 US201916558333A US10924094B1 US 10924094 B1 US10924094 B1 US 10924094B1 US 201916558333 A US201916558333 A US 201916558333A US 10924094 B1 US10924094 B1 US 10924094B1
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Prior art keywords
pulse width
synchronization signal
width modulation
count value
display
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US20210036693A1 (en
Inventor
Yueh-Chang Chen
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Power Forest Technology Corp
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Power Forest Technology Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop

Definitions

  • the present invention relates to a signal generating device and in particular relates to a pulse width modulation control circuit and a control method of a pulse width modulation signal.
  • a power conversion device is generally used for realizing conversion among power supplies by switching a power transistor switch by virtue of a pulse width modulation (PWM) signal.
  • PWM pulse width modulation
  • the PWM signal is generally generated by virtue of a PWM signal control device. While an integrated circuit can be miniaturized if the circuit design of the PWM signal control device can be further improved to be simpler under the condition that the PWM signal control device is subjected to integrated circuit (IC) integration, so that the circuit area of the electronic product can be greatly reduced.
  • IC integrated circuit
  • the present invention provides a pulse width modulation control circuit and a control method of a pulse width modulation signal so that the circuit area used by the pulse width modulation control circuit can be effectively reduced.
  • the pulse width modulation control circuit comprises a phase-locked loop clock generating circuit, a counter circuit and a comparison circuit.
  • the phase-locked loop clock generating circuit generates a phase-locked loop clock according to a synchronization signal.
  • the counter circuit is coupled to the phase-locked loop clock generating circuit and generates a count value according to the phase-locked loop clock. The count value is reset according to a transition point of the synchronization signal.
  • the comparison circuit is coupled to the counter circuit and is used for generating a pulse width modulation signal. The comparison circuit compares the count value with a duty ratio set value and sets the pulse width modulation signal to a high level while the count value is less than the duty ratio set value.
  • the pulse width modulation control circuit further comprises an edge detector, coupled to the phase-locked loop clock generating circuit and the counter circuit and detecting a rising edge of the synchronization signal to generate a reset signal, and the counter circuit resets the count value according to the reset signal.
  • the edge detector comprises a D flip flop, a phase inverter and an AND gate.
  • the data input end of the D flip flop receives the synchronization signal
  • the clock input end of the D flip flop receives the phase-locked loop clock.
  • the input end of the phase inverter is coupled to the data output end of the D flip flop.
  • the first input end of the AND gate receives the synchronization signal
  • the second input end of the AND gate is coupled to the output end of the phase inverter
  • the output end of the AND gate outputs the reset signal.
  • the counter circuit periodically resets the count value at the transition point of the synchronization signal.
  • the synchronization signal is a vertical synchronization signal.
  • the count value is reset according to the rising edge of the synchronization signal.
  • the present invention further provides a control method of a pulse width modulation signal, comprising the following steps: generating a phase-locked loop clock according to a synchronization signal; generating a count value according to the phase-locked loop clock, where the count value is reset according to a transition point of the synchronization signal; comparing the count value with a duty ratio set value; judging whether the count value is less than the duty ratio set value or not; if the count value is less than the duty ratio set value, setting the pulse width modulation signal to a high level; and if the count value is not less than the duty ratio set value, setting the pulse width modulation signal to a low level.
  • control method of the pulse width modulation signal comprises: detecting a rising edge of the synchronization signal to generate a reset signal; and resetting the count value according to the reset signal.
  • control method of the pulse width modulation signal comprises: periodically resetting the count value at the transition point of the synchronization signal.
  • the synchronization signal is a vertical synchronization signal.
  • the count value is reset according to the rising edge of the synchronization signal.
  • the counter circuit is capable of generating the count value according to the phase-locked loop clock and resetting the count value according to the transition point of the synchronization signal, so that circuits for resetting the count value can be saved, and furthermore, the circuit area used by the pulse width modulation control circuit can be effectively reduced.
  • FIG. 1 is a schematic diagram of a pulse width modulation control circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of an edge detector according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of waveforms of a synchronization signal, a delayed signal, a phase-inverted signal, a count value, a phase-locked loop clock and a reset signal according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a pulse width modulation control circuit according to another embodiment of the present invention.
  • FIG. 5 is a schematic diagram of waveforms of a synchronization signal, a count value and a phase-locked loop clock according to an embodiment of the present invention.
  • FIG. 6 is a flow diagram of a control method of a pulse width modulation signal according to an embodiment of the embodiment.
  • FIG. 1 is a schematic diagram of a pulse width modulation control circuit according to an embodiment of the present invention, refer to FIG. 1 .
  • the pulse width modulation control circuit comprises a phase-locked loop clock generating circuit 102 , a counter circuit 104 , a comparison circuit 106 and an edge detector 108 .
  • the counter circuit 104 is coupled to the phase-locked loop clock generating circuit 102 , the comparison circuit 106 and the edge detector 108 .
  • the phase-locked loop clock generating circuit 102 is capable of receiving a synchronization signal Sync 1 and generating a phase-locked loop clock Clk 1 according to the synchronization signal Sync 1 , where the synchronization signal Sync 1 may be, for example, a vertical synchronization signal, however, it is not limited thereto.
  • the counter circuit 104 is capable of counting according to the phase-locked loop clock to generate a count value C 1 .
  • the edge detector 108 is capable of detecting a transition point (for example, a rising edge, however, it is not limited thereto, and a falling edge may also be detected in parts of embodiments) of the synchronization signal Sync 1 to generate a reset signal Sr 1 to the counter circuit 104 , so that the counter circuit 104 resets the count value C 1 according to the reset signal Sr 1 .
  • the comparison circuit 106 is used for generating a pulse width modulation signal PWM 1 according to the count value C 1 and a duty ratio set value.
  • the pulse width modulation signal output by the comparison circuit 106 when the count value C 1 is less than the duty ratio set value is at a high level, while the pulse width modulation signal PWM 1 output by the comparison circuit 106 when the count value C 1 is not less than the duty ratio set value is at a low level.
  • the comparison circuit 106 can be made to output the pulse width modulation signal PWM 1 converted between the high level and the low level under the coordination of resetting the count value C 1 by utilizing the reset signal Sr 1 generated by the edge detector 108 .
  • the duty ratio of the pulse width modulation signal PWM 1 is decided by the duty ratio set value.
  • the pulse width modulation signal PWM 1 may be, for example, transmitted to a driving circuit for driving a backlight module of a display, since the synchronization signal Sync 1 may be the vertical synchronization signal, the backlight module can be made to provide a backlight source in a display period of each frame by resetting the count value C 1 according to the synchronization signal Sync 1 and cooperating with the appropriate duty ratio set value, so that a screen is displayed.
  • a register circuit for storing periodic data of the pulse width modulation signal and a comparator circuit for comparing the periodic data with the count value in a known technology can be omitted, and the circuit area used by the pulse width modulation control circuit can be effectively reduced.
  • the edge detector 108 can be as shown in FIG. 2
  • the edge detector 108 can, for example, comprise a D flip flop 202 , a phase inverter 204 and an AND gate 206 .
  • the data input end D of the D flip flop 202 receives the synchronization signal Sync 1
  • the clock input end of the D flip flop 202 receives the phase-locked loop clock Clk 1
  • the data output end Q of the D flip flop 202 is coupled to the input end of the phase inverter 204
  • one input end of the AND gate 206 receives the synchronization signal Sync 1
  • the other input end of the AND gate 206 is coupled to the output end of the phase inverter 204 .
  • the D flip flop 202 is capable of sampling the synchronization signal Sync 1 according to the phase-locked loop clock Clk 1 to output a delayed signal DS 1 , as shown in FIG. 3 , the delayed signal DS 1 delays the phase-locked loop clock Clk 1 for one periodic time relative to the synchronization signal Sync 1 .
  • the phase inverter 204 performs phase inversion processing on the delayed signal DS 1 to output a phase-inverted signal DSB 1
  • the AND gate 206 performs AND operation on the synchronization signal Sync 1 and the phase-inverted signal DSB 1 to output a reset signal Sr 1 . As shown in FIG.
  • the reset signal Sr 1 is capable of realizing transition when the transition point (the rising edge of the synchronization signal Sync 1 in the embodiment) of the synchronization signal Sync 1 appears so as to trigger the counter circuit 104 to reset the count value.
  • the count value may be reset to 0 by the reset signal Sr 1 when the counter circuit 104 counts from 0 to 10.
  • FIG. 4 is a schematic diagram of a pulse width modulation control circuit according to another embodiment of the present invention.
  • the counter circuit 104 generates the count value according to the phase-locked loop clock Clk 1 and periodically automatically resets the count value.
  • the reset period of the counter circuit 104 may be set to be same as the period of the synchronization signal Sync 1 , for example, the count value can be reset when the rising edge of the synchronization signal Sync 1 appears.
  • the time when the counter circuit 104 counts from 0 to 7 is a time point that the rising edge of the synchronization signal Sync 1 appears.
  • the counter circuit 104 can automatically return to 0 to re-accumulate the count value, and thus, the circuit area used by the pulse width modulation control circuit can be further reduced without resetting the counter circuit 104 by virtue of the edge detector 108 .
  • the implementation details of the phase-locked loop clock generating circuit 102 and the comparison circuit 106 are similar to those of the above embodiments, and therefore, the descriptions thereof are omitted herein.
  • FIG. 6 is a flow diagram of a control method of a pulse width modulation signal according to an embodiment of the embodiment, refer to FIG. 6 .
  • a control method of a pulse width modulation signal comprises the following steps: firstly, generating a phase-locked loop clock according to a synchronization signal (step S 602 ); next, generating a count value according to the phase-locked loop clock, where the count value is reset according to a transition point of the synchronization signal (step S 604 ).
  • the mode of resetting the count value may be, for example, to detect a rising edge of the synchronization signal to generate a reset signal and reset the count value according to the reset signal, and in parts of embodiments, the count value may also be reset in a mode of periodically resetting the count value at a transition point (for example the rising edge) of the synchronization signal; then, comparing the count value with a duty ratio set value (step S 606 ) to judge whether the count value is less than the duty ratio set value or not (step S 608 ); if the count value is less than the duty ratio set value, setting the pulse width modulation signal to a high level (step S 610 ); and if the count value is not less than the duty ratio set value, setting the pulse width modulation signal to a low level (step S 612 ), where the duty ratio of the pulse width modulation signal can be regulated by regulating the duty ratio set value.
  • the counter circuit is capable of generating the count value according to the phase-locked loop clock and resetting the count value according to the transition point of the synchronization signal, so that circuits for resetting the count value can be saved, and furthermore, the circuit area used by the pulse width modulation control circuit can be effectively reduced.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Liquid Crystal Display Device Control (AREA)
US16/558,333 2019-07-31 2019-09-03 Pulse width modulation control circuit and control method of pulse width modulation signal Active US10924094B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW108127300A TWI695585B (zh) 2019-07-31 2019-07-31 脈波寬度調變控制電路以及脈波寬度調變信號的控制方法
TW108127300 2019-07-31

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TWI779967B (zh) * 2021-12-14 2022-10-01 瑞昱半導體股份有限公司 具有適應性比較機制的比較電路及其運作方法
TWI782841B (zh) * 2021-12-30 2022-11-01 新唐科技股份有限公司 用於透過脈波調變信號進行控制的電路系統的事件偵測控制器與方法
CN114978128B (zh) * 2022-07-29 2022-12-30 广东曜芯科技有限公司 脉冲宽度调制波形的控制方法和装置

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TWI435546B (zh) 2004-08-23 2014-04-21 微晶片科技公司 用於產生一相位補償脈波寬度調變(pwm)信號之裝置與方法
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US8786540B2 (en) 2007-07-18 2014-07-22 Ams Ag Circuit arrangement and method for driving segmented LED backlights in particular
US9390659B2 (en) 2007-07-18 2016-07-12 Ams Ag Circuit configuration and method for controlling particularly segmented LED background illumination
US20090184742A1 (en) 2008-01-23 2009-07-23 Microchip Technology Incorporated Externally Synchronizing Multiphase Pulse Width Modulation Signals
US20110204810A1 (en) * 2010-02-25 2011-08-25 Msilica Inc Apparatus, circuit and method for automatic phase-shifting pulse width modulated signal generation
US20130082747A1 (en) 2011-09-29 2013-04-04 Microchip Technology Incorporated Variable frequency ratiometric multiphase pulse width modulation generation
TWI556583B (zh) 2011-09-29 2016-11-01 微晶片科技公司 同步多頻率脈衝寬度調變產生器
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Also Published As

Publication number Publication date
US20210036693A1 (en) 2021-02-04
TWI695585B (zh) 2020-06-01
CN112311359B (zh) 2023-11-14
CN112311359A (zh) 2021-02-02
TW202107848A (zh) 2021-02-16

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