TWM606202U - Semiconductor test chip having electric connection pad with adjustable energy state - Google Patents

Abstract

A semiconductor test chip with an electrical connection pad with adjustable energy state is used for the reliability test of semiconductor components. It includes a semiconductor substrate and at least one test chip disposed on the semiconductor substrate, the at least one test chip has a top surface away from the semiconductor substrate, and an electrical connection pad exposed from the top surface, the electrical connection pad having A metal layer and an energy state layer formed on the surface of the metal layer, wherein the energy state layer is combined with the metal layer and has a different energy gap from the metal layer.

Description

Semiconductor test chip with electrical connection pad with adjustable energy state

The present invention relates to a semiconductor test wafer, in particular to a semiconductor test wafer used for wire bonding reliability testing.

With the development of semiconductor process technology, the size of semiconductor wafers has also become smaller. Among them, wire bonding is an important technology that enables the external electrical connection of the miniaturized semiconductor chips. Therefore, how to ensure the reliability of the bonding of the semiconductor chips is an important issue that the related industry actively pays attention to.

The metal layer of the semiconductor chip for external electrical connection is generally composed of aluminum or copper. However, aluminum or copper is easy to adsorb foreign ions in the external environment, and the adsorbed foreign ions (such as chloride ions, nitrogen ions, etc.) because the surface energy state is different from that of the metal layer, it is easy to cause corrosion of the metal layer or the metal layer. The reaction forms an intermetallic compound. Therefore, when the metal layer is subsequently used for wire bonding or soldering copper bumps for external electrical connection, and packaged to form a semiconductor device, the heterogeneous ions adsorbed on the metal layer will increase over time to the metal Corrosion caused by the layer, or cause the Galvanic corrosion between the metal layer and the bonding/copper bump to become more and more serious, thereby affecting the conductivity of the metal layer, or affecting the adhesion of the bonding/copper bump and the metal layer Due to its performance, the bonding/copper bumps will peel off or fall off during the use of semiconductor components, which will adversely affect the reliability of the components.

Therefore, in order to ensure the reliability and yield of semiconductor chips, semiconductor components are generally tested for the reliability of wire bonding before packaging. However, since the reliability test needs to simulate different environmental conditions and requires a long time to test, the related test is extremely time-consuming.

Therefore, the objective of the present invention is to provide a semiconductor test chip with an electrical connection pad with adjustable energy state for conducting wire bonding reliability testing.

Therefore, the semiconductor test wafer of the present invention includes a semiconductor substrate and at least one test wafer.

The at least one test chip is disposed on the semiconductor substrate and includes a top surface away from the semiconductor substrate, and an electrical connection pad exposed from the top surface, the electrical connection pad having a metal layer, and a metal layer formed on the metal layer The energy state layer of the surface layer, wherein the energy state layer is combined with the metal layer and has an energy gap different from the metal layer.

The effect of the present invention is to use plasma or corrosive gas to perform surface treatment on the metal layer of the semi-finished semiconductor element for external electrical connection, and form an energy state layer with a different energy gap from the metal layer on the metal layer, and The energy state layer can be used to simulate the oxidation and corrosion damage conditions of the semiconductor element in different environments, thereby speeding up the reaction when the semiconductor test wafer is used for reliability testing, so as to reduce the reliability testing time.

The related technical content, features and effects of the present invention will be clearly presented in the following detailed description of the embodiments with reference to the drawings. In addition, it should be noted that the drawings of the present invention only show the structural and/or positional relationship between the elements, and are not related to the actual size of each element.

The new type semiconductor test chip with adjustable energy state electrical connection pad is used for wire bonding reliability test.

Referring to FIGS. 1 and 2, an embodiment of the new semiconductor test chip with adjustable energy state electrical connection pads includes a semiconductor substrate 2 and a plurality of test chips 3.

The semiconductor substrate 2 can be selected from III-IV groups such as silicon, compound semiconductors (such as silicon carbide (SiC)), gallium arsenide (GaAs), indium phosphide (InP), or zinc oxide (ZnO), cadmium telluride ( CdTe) and other group II-VI semiconductor materials.

The test chips 3 are arranged on the semiconductor substrate 2 in an array arrangement. For example, the test chips 3 may be arranged on the semiconductor substrate 2 in a 9x9 array, and each test chip 3 has a top surface exposed to the outside.的At least one electrical connection pad 34.

Each test chip 3 has a test circuit 31, a redistributed circuit 32 located above the test circuit 31 and electrically connected to the test circuit 31, and a dielectric layer covering the redistributed circuit 32 and having a plurality of openings 331 33, and a plurality of electrical connection pads 34. The electrical connection pads 34 are respectively connected to the redistributed circuit 32 and are exposed from one of the corresponding openings 331 of the dielectric layer 33 respectively.

In detail, the test circuit 31 has a dielectric insulating layer 311 and a metal circuit layer 312 that are alternately stacked on the semiconductor substrate 2, and most of them penetrate through the dielectric insulating layers 311 to separate the metal circuit layers. The conductive through holes 313 with different electrical connections 312 are electrically connected to different metal circuit layers 312 through the conductive through holes 313 to form different conduction loops. Among them, in order to simulate the circuit of a general functional chip, the number of layers, thickness, and electrical connection of the dielectric insulating layer 311 and the metal circuit layer 312 of the test circuit 31 can also completely simulate the circuit structure of the functional chip. In this way, it can also be borrowed The circuit test result of the test chip is fed back to the fully functional chip to adjust the circuit design of the functional chip accordingly. The aforementioned dielectric insulating layer 311 can be selected from silicon dioxide, silicon nitride, silicon oxynitride, or polymer materials, and the metal circuit layer 312 and the conductive through hole 313 can be selected from tungsten, aluminum, copper, Conductive materials such as aluminum alloy or copper alloy. Since the related manufacturing process and materials used for the test electrical structure are well-known in the semiconductor technology field, no further description will be given.

The redistribution line 32 is arranged above the test circuit 31 and is electrically connected to the test circuit 31. The dielectric layer 33 covers the redistributed circuit 32 and has a plurality of openings 331. The electrical connection pads 34 are connected to the redistributed circuit 32 and are exposed from the corresponding openings 331 of the dielectric layer 33 for subsequent use. Wire bonding or formation of solder or copper bumps, so that the metal circuit layers 312 are connected in series to form at least one independent conductive loop and can be electrically connected to the outside. The redistributed circuit 32 can be selected from conductive materials such as aluminum, aluminum alloy, copper or copper alloy, and the dielectric layer 33 can be selected from silicon dioxide, silicon nitride, silicon oxynitride, or polymer insulating materials.

Each electrical connection pad 34 has a metal layer 341 electrically connected to the redistributed line 32 and an energy state layer 342 covering at least a part of the surface of the metal layer 341. The metal layer 341 is made of materials such as aluminum, aluminum alloy, copper, or copper alloy, and is connected to the redistributed circuit 32 and can be exposed from one of the openings 331. The energy state layer 342 covers at least part of the surface of the metal layer 341, and the band gap of the energy state layer 342 can be greater or smaller than the energy gap of the metal layer 341, and has a different energy from that of the metal layer 341. Gap. Wherein, the energy state layer 342 includes a metal compound containing at least one element of halogen, nitrogen, oxygen, hydrogen, etc., and the metal compound is composed of at least one element of halogen, nitrogen, oxygen, hydrogen, etc., and the metal of the metal layer 341 From the reaction.

It should be noted that the energy state layer 342 is different in accordance with the type of the constituent material of the metal layer 341 and the gas or plasma used for processing. For example, when the material of the metal layer 341 is copper or copper alloy, the energy state layer 342 can pass through a selection of processing gases or plasma containing at least one element of halogen, nitrogen, oxygen, hydrogen, etc., and may include CuCl _x OH _y , At least one of Cu _x OH _y Cu _x N _y , Cu _x N _y OH _z , and Cu _x O _y N _z ; when the material of the metal layer 341 is aluminum or aluminum alloy, the energy state layer 342 passes through the halogen-containing The selection of the type of processing gas or plasma for at least one element of, nitrogen, oxygen, hydrogen, etc., can include AlCl _x , AlCl _x OH _y , AlOH _x , Al _x N _y , Al _x N _y OH _z , and Al _x O At least one of _y N _z .

The aforementioned energy state layer 342 can be formed on the surface of the metal layer 341 by performing surface treatment on the metal layer 341 using a selected plasma or corrosive gas.

Surface treatment is performed on the metal layer 341 through the choice of different plasmas or corrosive gases, and an energy state layer 342 with a required energy gap is formed on the metal layer 341, and an electrical connection pad with adjustable energy states can be obtained 34 semiconductor test wafers.

Refer to Table 1 and Figure 3 below. Figure 3 shows the XPS spectra of the layer 342 with different energy states obtained by treating the metal layer 341 with oxygen plasma for different times (20 to 70 seconds (sec)). Table 1 shows The result of the offset of the binding energy between the metal layer 341 (Pt) and the energy state layers 342 at the position shown by the dashed line in FIG. 3, where in order to avoid the influence of the metal layer material 341 on the XPS measurement of the energy state layer 342, 3 is platinum (Pt) as the material of the metal layer 341.

Table 1 Plasma processing time (sec.) Poor binding energy (eV) 70 +0.1 60 +0.1 50 +0.2 40 +0.3 30 +0.5 20 +0.6

From the foregoing Table 1 and FIG. 3, it can be clearly seen that after plasma treatment at different times, an energy state layer 342 with a different energy gap from the metal layer 341 can be formed on the surface of the metal layer 341. Therefore, the subsequent use of the The semiconductor test chip of the electrical connection pad 34 with adjustable energy state is wire-bonded to be used in the wire bonding reliability test of simulating different environmental conditions. The energy state layer 342 can be used to simulate the oxidation and corrosion damage of semiconductor components in different environments. , So as to speed up the reaction during the reliability test to reduce the reliability test time.

To sum up, the present invention uses plasma or corrosive gas to perform surface treatment on the metal layer 341 of the semi-finished semiconductor device, and an energy state layer 342 with a different energy gap from the metal layer 341 is formed on the metal layer 341. A semiconductor test wafer with electrical connection pads with adjustable energy states is prepared. Therefore, when the electrical connection pad 34 of the semiconductor test piece is subsequently used for wire bonding or forming copper bumps for wire bonding reliability testing, the energy state layer 342 can be used to simulate the oxidation and corrosion of semiconductor components in different environments. In order to reduce the time of reliability testing, the semiconductor test wafer can be used to accelerate the reaction of the reliability test, so it can indeed achieve the goal of new cost.

However, the above-mentioned are only examples of the present model. When the scope of implementation of the present model cannot be limited by this, all simple equivalent changes and modifications made in accordance with the patent scope of the present model application and the contents of the patent specification still belong to This new patent covers the scope.

2: Semiconductor substrate 32: re-route 3: Test chip 33: Dielectric layer 31: Test circuit 331: open 311: Dielectric insulation layer 34: Electrical connection pad 312: Metal circuit layer 341: Metal layer 313: conductive crown hole 342: Energy State Layer

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, among which: Figure 1 is a schematic diagram illustrating an embodiment of the new semiconductor test wafer; Figure 2 is a schematic side view to assist in explaining one of the test wafers of this embodiment; and Figure 3 is an XPS diagram illustrating the combined energy measurement results of different energy state layers obtained after crystal oxygen plasma treatment.

2: Semiconductor substrate

3: Test chip

31: Test circuit

311: Dielectric insulation layer

312: Metal circuit layer

313: Conductive through hole

32: re-route

33: Dielectric layer

331: open

34: Electrical connection pad

341: Metal layer

342: Energy State Layer

Claims (5)

A semiconductor test chip with an electrical connection pad with adjustable energy state, used for bonding reliability testing, including: A semiconductor substrate; and At least one test chip is disposed on the semiconductor substrate, has a top surface away from the semiconductor substrate, and an electrical connection pad exposed from the top surface, the electrical connection pad having a metal layer and a surface layer formed on the metal layer The energy state layer, wherein the energy state layer is combined with the metal layer and has a different energy gap from the metal layer. The semiconductor test wafer having an electrical connection pad with an adjustable energy state according to claim 1, wherein the energy state layer is the metal layer exposed to plasma or corrosive gas through at least one element such as halogen, nitrogen, oxygen, and hydrogen. It is obtained after gas treatment and includes metal compounds containing at least one element such as halogen, nitrogen, oxygen, and hydrogen. The semiconductor test wafer with an electrical connection pad with an adjustable energy state according to claim 2, wherein the constituent material of the metal layer is aluminum, aluminum alloy, or copper or copper alloy, and when the metal layer is copper or copper alloy, The energy state layer is selected from at least one of CuCl _x OH _y , Cu _x OH _y Cu _x N _y , Cu _x N _y OH _z , and Cu _x O _y N _z . When the metal layer is aluminum or aluminum alloy, the The energy state layer is selected from at least one of AlCl _x , AlCl _x OH _y , AlOH _x , Al _x N _y , Al _x N _y OH _z , and Al _x O _y N _z . The semiconductor test chip with electrical connection pads with adjustable energy states according to claim 1, wherein the at least one test chip further includes a test circuit and a redistributed circuit located above the test circuit and electrically connected to the test circuit , And a dielectric layer covering the redistributed circuit and having at least one opening, and the at least one electrical connection pad is connected to the redistributed circuit and is exposed from the opening. The semiconductor test chip with electrical connection pads with adjustable energy states as described in claim 4 includes a plurality of test chips arrayed on the semiconductor substrate. The test chips can be connected in series through the electrical connection pads to form at least one Independently electrically connected conductive circuit.

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