TWI731791B - Semiconductor test wafer and manufacturing method thereof - Google Patents

Abstract

A semiconductor test wafer for testing the reliability of wiring of semiconductor components, comprising a semiconductor substrate and at least one test wafer arranged on the semiconductor substrate, the at least one test wafer having a top surface opposite to the semiconductor substrate, and at least An electrical connection pad exposed from the top surface, the electrical connection pad having a metal layer and a metal compound layer formed on at least part of the surface of the metal layer, wherein the metal compound layer includes a metal oxide, and the metal The thickness of the compound layer is between 2 and 50 nm. In addition, the present invention also provides a manufacturing method of the semiconductor test wafer at the same time.

Description

Semiconductor test wafer and manufacturing method thereof

The invention relates to a semiconductor wafer and a manufacturing method thereof, in particular to a semiconductor test wafer used for wire bonding reliability testing and a manufacturing method thereof.

With the demand for lighter, thinner and smaller products in the electronics industry and the development of semiconductor technology, the size of semiconductor chips has also become more and more shrinking. Among them, wire bonding is an important technology that enables the external electrical connection of the miniaturized semiconductor chip. Therefore, how to ensure the reliability of the semiconductor chip wire bonding is an important issue that the related industry actively pays attention to.

The metal layer used to connect the semiconductor wafer with the bonding wires is generally composed of aluminum or copper. However, aluminum or copper is easily oxidized and easily adsorbs foreign ions in the external environment. Therefore, when the surface is oxidized or the metal layer that adsorbs foreign ions (such as chloride ions, nitrogen ions, etc.) is wire-bonded and packaged to make a semiconductor In the process of component use, the metal oxides and foreign ions adsorbed on the metal layer will affect the surface properties of the metal layer, or further corrode the metal layer, or affect the wire bonding metal and the metal layer. Adhesive intermetallic compounds, etc., cause the wire bonding to peel off or fall off during the use of the semiconductor device, which adversely affects the reliability of the device.

Therefore, in order to ensure the reliability and yield of the chip, semiconductor components are generally tested for the reliability of wire bonding before packaging. However, since the reliability test needs to simulate different environmental conditions and requires a long time to test, the test is extremely time-consuming.

Therefore, the purpose of the present invention is to provide a stable and high-quality semiconductor test wafer for the wire bonding reliability test of semiconductor components, so as to simulate the possibility of abnormal wire bonding reliability on the surface of the metal layer during the manufacturing process of semiconductor devices, and to assist in research and development. The personnel grasp the problem in real time to shorten the development time.

The semiconductor test wafer of the present invention includes a semiconductor substrate and at least one test wafer.

The at least one test chip is disposed on the semiconductor substrate, and includes a top surface opposite to the semiconductor substrate, and at least one electrical connection pad exposed from the top surface. The electrical connection pad includes a metal layer and a metal compound layer formed on at least part of the surface of the metal layer by atomic deposition.

In addition, another object of the present invention is to provide a method for manufacturing a semiconductor test wafer for testing the reliability of semiconductor component wiring.

Therefore, the manufacturing method of the semiconductor test wafer of the present invention includes the following steps.

First, provide a semi-finished semiconductor device. Semi-finished semiconductor components It has a semiconductor substrate and at least one chip arranged on the semiconductor substrate. The at least one chip has a test circuit, and at least one metal layer electrically connected to the test circuit and exposed from the top surface of the at least one chip.

A metal compound layer is deposited on at least part of the surface of the at least one metal layer by atomic deposition to prepare the semiconductor test wafer.

The effect of the present invention is to form a metal compound layer including metal oxide on at least part of the surface of the electrical connection pad of the semiconductor test chip for external electrical connection, and when the semiconductor test chip is used for wire bonding reliability test, Through at least one of the composition, thickness, and pattern of the metal compound layer, the surface state of the electrical connection pad of the semiconductor device, such as roughness, oxidation state, etc., and/or oxidation and corrosion damage in different environments, can be simulated. Accelerate the reaction of the reliability test using the semiconductor test wafer to reduce the reliability test time.

2: Semiconductor substrate

3: Test chip

31: Test circuit

311: Dielectric insulation layer

312: Metal circuit layer

313: Conductive through hole

32: Re-layout the line

33: Dielectric layer

331: open

34: Electrical connection pad

341: Metal layer

342: metal compound layer

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, in which: FIG. 1 is a schematic diagram illustrating an embodiment of the semiconductor test chip of the present invention; FIG. 2 is a schematic side view to assist in explanation One of the test wafers of this embodiment; FIG. 3 is a partial enlarged view to assist in explaining the electrical connection pads of this embodiment; and FIG. 4 is a TEM photograph illustrating the TEM of forming a metal compound layer on the metal layer Figure.

The related technical content, features and effects of the present invention will be clearly presented in the following detailed description of the embodiments with reference to the drawings. In addition, it should be noted that the drawings of the present invention only show the structural and/or positional relationship between the elements, and are not related to the actual size of each element.

The semiconductor test wafer of the present invention is used for wire bonding reliability test.

Referring to FIGS. 1 and 2, an embodiment of the semiconductor test wafer includes a semiconductor substrate 2 and a plurality of test wafers 3.

The semiconductor substrate 2 can be selected from silicon, compound semiconductors such as silicon carbide (SiC), or gallium arsenide (GaAs), indium phosphide (InP) and other III-IV groups, or zinc oxide (ZnO), cadmium telluride (CdTe) ) And other II-VI group semiconductor materials.

The test chips 3 are arranged on the semiconductor substrate 2 in an array arrangement. Each test chip 3 has a top surface opposite to the semiconductor substrate 2, a test circuit 31, a redistributed circuit 32 located above the test circuit 31 and electrically connected to the test circuit 31, and a redistributed circuit 32 that covers the redistributed circuit 32. The dielectric layer 33 having at least one opening 331, and the electrical connection pads 34 respectively connected to the redistributed circuit 32 and exposed from one of the openings 331 of the dielectric layer 33.

In detail, the test circuit 31 has multiple layers alternately stacked on the The dielectric insulating layer 311 and the metal circuit layer 312 on the semiconductor substrate 2 and most of the conductive through holes 313 penetrating the dielectric insulating layer 311 to make different electrical connections to the metal circuit layer 312 respectively pass through the conductive through holes 313 The holes 313 are electrically connected to different metal circuit layers 312 to form different conduction loops. Among them, in order to simulate the circuit of a general functional chip, the number of layers, thickness, and electrical connection relationship of the dielectric insulating layer 311 and the metal circuit layer 312 of the test circuit 31 can also completely simulate the circuit structure of the functional chip. The circuit test result of the test chip 3 is fed back to the fully functional chip to adjust the circuit design of the functional chip accordingly. The aforementioned dielectric insulating layer 311 can be selected from silicon dioxide, silicon nitride, silicon oxynitride, or polymer materials, and the metal circuit layer 312 and the conductive through hole 313 can be selected from tungsten, aluminum, copper, Conductive materials such as aluminum alloy or copper alloy. Since the related manufacturing process and materials used for the test circuit 31 are well-known in the semiconductor technology field, no further description is given here.

The redistribution line 32 is arranged above the test circuit 31 and is electrically connected to the test circuit 31. The dielectric layer 33 covers the redistributed circuit 32 and has a plurality of openings 331 that can expose the redistributed circuit 32. Wherein, the redistributed circuit 32 is selected from conductive materials such as tungsten, aluminum, copper, aluminum alloy, or copper alloy, and the dielectric layer 33 can be selected from silicon dioxide, silicon nitride, silicon oxynitride, or polymer materials.

The electrical connection pads 34 and the redistributed lines 32 are connected from the exposed surfaces of the openings 331 and are exposed to the outside from the corresponding openings 331 respectively for subsequent wire bonding or formation of solder or copper bumps, so that the metal circuits The layers 312 are connected in series to form at least one independent guide Electric circuit. In detail, each electrical connection pad 34 has a metal layer 341 connected to the exposed surface of the redistributed circuit 32 from the openings 331, and a metal compound layer 342 formed on at least a part of the surface of the metal layer 341. The metal layer 341 is made of materials such as aluminum, aluminum alloy, copper, or copper alloy. The metal compound layer 342 includes metal oxides, halogen-containing metal compounds, nitrogen-containing metal compounds, and oxygen-containing metal compounds. At least one.

In some embodiments, the metal compound layer 342 includes the same metal oxide as the metal atom of the metal layer 341, and the thickness of the metal compound layer 342 is between 2 nm and 50 nm. Preferably, the thickness of the metal compound layer 342 is greater than 5 nm.

In some embodiments, the thickness of the metal compound layer 342 is between 10 nm and 50 nm.

It should be noted that since the metal compound layer 342 is composed of a metal oxide, and at least one of a halogen-containing compound, a nitrogen-containing compound, and an oxygen-containing compound, the electrical connection of the electrical connection pad 34 Therefore, depending on the test requirements and objectives of the semiconductor test wafer, the composition and distribution of the metal compound layer 342 can be controlled (for example, the metal compound layer 342 can be controlled to selectively cover the metal layer 341 in full or part). For example, refer to Figures 2 and 3, Figure 2 shows that the metal compound layer 342 completely covers the surface of the metal layer 341 and has a thickness ranging from 2nm to 50nm; Figure 3 shows that the metal compound layer 342 is patterned Covering part of the surface of the metal layer 341 and having a thickness of 2nm~50nm), so that the electrical connection pad 34 can be controlled into a surface with different electrical properties and roughness, so as to be more suitable for simulating test conditions of different wire bonding reliability. In addition, it should be noted that in actual implementation, the metal compound layer 342 can also cover part of the surface of the metal layer 341 in an irregular manner, or can be further extended to cover the dielectric layer 33 as required. The structure shown in Figures 2 and 3 is limited.

Generally speaking, the metal compound layer 342 formed on the surface of the metal layer 341 will not only cause electrical changes, but also cause changes in surface roughness and surface chemical properties, which will affect subsequent wire bonding, soldering or copper bumps and the Adhesion and bonding strength of the electrical connection pad 34. However, because the thickness of the original metal oxide is generally very thin (<5nm), when using a wafer with an electrical connection pad with a very thin metal oxide on the surface to wire, and perform the wire bonding reliability evaluation test , It will take a longer inspection time to measure the effect of metal oxide on wire bonding. Therefore, the present invention controls the original surface properties and roughness of the electrical connection pad 34 through the composition of the metal compound layer 342 and the distribution and thickness of the metal compound layer 342, and can provide different surface properties/electrical properties and roughness. The test chip of the electrical connection pad 34 under the high-degree condition can be used for the bonding reliability test under different conditions and can be induced to accelerate the reaction of using the semiconductor test chip in the reliability test, thereby effectively reducing the reliability test time.

Specifically, the aforementioned metal compound layer 342 can be deposited and formed on the surface of the metal layer 341 by means of atomic deposition (ALD), and the thickness and pattern of the metal compound layer 342 can be more accurately controlled to control the electrical connection pad 34 Rough surface degree.

It should be further explained that, because the adhesion between the bonding wire/tin ball/copper bump and the electrical connection pad 34 is not only affected by the surface roughness of the electrical connection pad 34, it will also be affected by the bonding wire/tin ball/ The chemical properties of the connection interface between the copper pillar and the electrical connection pad 34 are affected. Therefore, in addition to the metal oxide, the metal compound layer 342 of the present invention may further include one of the compounds of the group A, and the compound of the group A It is formed by reacting the metal layer 341 with non-metal elements (such as halogen, nitrogen, oxygen), including halogen-containing compounds, nitrogen-containing compounds, and oxygen-containing compounds. Through the change of the composition of the metal compound layer 342, the surface of the electrical connection pad 34 can be used to simulate the oxidation and the change of the electrical connection pad 34 in different environments in addition to the change in roughness. Corrosion damage conditions can accelerate the induction reaction during the reliability test of the semiconductor test wafer, so as to reduce the reliability test time.

In some embodiments, when the metal layer 341 is made of aluminum (Al), the metal oxide of the metal compound layer 342 is aluminum oxide (Al ₂ O ₃ ), and the halogen-containing compound may be [AlF ₆ ] ^{3 -} , Or AlF ₃ , the nitrogen-containing compound can be aluminum nitride (AlN).

In other embodiments, the metal layer 341 is made of copper (Cu), and the metal oxide of the metal compound layer 342 is copper oxide (CuO) and/or cuprous oxide (Cu ₂ O). The halogen compound may be CuClx.

It should also be noted that the test chips 3 can subsequently form solder bumps on their electrical connection pads 34, and combine the solder bumps of one of the electrical connection pads 34 with the other The solder bumps of the electrical connection pads 34 are electrically connected; or the different electrical connection pads 34 are electrically connected to each other by wire bonding, so that multiple independent circuits of the test circuit 31 of the test chip 3 are electrically connected, or the Different test chips 3 are connected in series, and are a Daisy chain. Since the test chips 3 are distributed on the semiconductor substrate 2 in an array, they can be cut according to the required number of test chips 3 and electrical connection patterns (as shown by the dashed line in Figure 1) during use, which can be easier to use .

Referring to FIG. 4, FIG. 4 is a TEM photograph of a metal compound layer 342 containing aluminum oxide formed on a metal layer 341 composed of A1, in which FIG. 4(b) is a partial enlarged view of FIG. 4(a), and FIG. 4( c) is a metal compound layer 342 containing aluminum oxide and a fluorine-containing compound. It can be seen from FIG. 4 that the thickness of the metal compound layer 342 can be used to control the surface roughness of the electrical connection pad 34, and the chemical composition of the metal compound layer 342 can be changed to obtain different surface roughness and chemical energy. The state of the test wafer can be used to evaluate the reliability evaluation test of the influence of different roughness and different surface energy states on the wire bonding.

In summary, the present invention utilizes the formation of metal oxides on the surface of the metal layer 341, or may further include halogen-containing compounds and nitrogen-containing compounds obtained by reacting different non-metal elements with the metal of the metal layer 341. The metal compound layer 342 composed of at least one of, and oxygen-containing compounds, so that the surface properties of the electrical connection pad 34 can be simulated by the metal compound layer 342 to simulate the roughness of the surface of the electrical connection pad 34 on a semiconductor chip in different environments Degree, oxidation and corrosion damage, and can be in the reliability In the test, the induction reaction is accelerated to reduce the time of the reliability test, so it can indeed achieve the purpose of the invention.

However, the above are only examples of the present invention. When the scope of implementation of the present invention cannot be limited by this, all simple equivalent changes and modifications made in accordance with the scope of the patent application of the present invention and the content of the patent specification still belong to Within the scope covered by the patent of the present invention.

2: Semiconductor substrate

3: Test chip

31: Test circuit

311: Dielectric insulation layer

312: Metal circuit layer

313: Conductive through hole

32: Re-layout the line

33: Dielectric layer

331: open

34: Electrical connection pad

341: Metal layer

342: metal compound layer

Claims (13)

A semiconductor test wafer for testing the reliability of wiring of semiconductor components, comprising: a semiconductor substrate; and at least one test wafer, the at least one test wafer is arranged on the semiconductor substrate, and includes: a top surface opposite to the semiconductor substrate At least one electrical connection pad, exposed from the top surface, includes a metal layer and a metal compound layer formed on at least part of the surface of the metal layer by atomic deposition, and the metal compound layer includes the metal layer Metal oxides with the same metal atoms; and a test circuit for the at least one test chip to be electrically connected to the outside. The semiconductor test wafer according to claim 1, wherein the metal compound layer includes at least one of a halogen-containing metal compound, a nitrogen-containing metal compound, and an oxygen-containing metal compound. The semiconductor test wafer according to claim 1, wherein the thickness of the metal compound layer is between 2 nm and 50 nm. The semiconductor test chip according to claim 1, comprising a plurality of arrays of test chips distributed on the semiconductor substrate, wherein each test chip further includes a test circuit, and the test chips can be electrically connected by the test circuits. The semiconductor test chip according to claim 5, wherein each test chip further has a redistributed circuit located above the test circuit and electrically connected to the test circuit, and a redistributed circuit that covers the redistributed circuit and has at least one opening Each of the electrical connection pads is electrically connected to the redistributed circuit and exposed to the outside from the corresponding one of the openings. The semiconductor test wafer according to claim 1, wherein the metal layer and the The test circuit is electrically connected, and the metal compound layer completely covers the surface of the metal layer. The semiconductor test wafer according to claim 1, wherein the metal layer is electrically connected to the test circuit, and the metal compound layer partially covers the surface of the electrical connection pad. The semiconductor test wafer according to claim 6 or 7, wherein the metal compound layer further extends to cover the dielectric layer. A method for manufacturing a semiconductor test wafer includes: providing a semi-finished semiconductor element, the semi-finished semiconductor element having a semiconductor substrate and at least one wafer disposed on the semiconductor substrate, the at least one wafer having a test circuit, and at least one The test circuit is electrically connected to the exposed metal layer from the top surface of the at least one wafer; and a metal compound layer is deposited on at least part of the surface of the at least one metal layer by atomic deposition to prepare the semiconductor test wafer. The method for manufacturing a semiconductor test wafer according to claim 9, wherein the material of the metal compound layer includes at least one of a metal oxide, a halogen-containing metal compound, a nitrogen-containing metal compound, and an oxygen-containing metal compound. The method for manufacturing a semiconductor test wafer according to claim 9, wherein the thickness of the metal compound layer is between 2 nm and 50 nm. The method for manufacturing a semiconductor test chip according to claim 9, wherein the semi-finished semiconductor device has a plurality of arrays of chips distributed on the semiconductor substrate, each chip has a test circuit, and the chips can be electrically connected by the test circuits connection. The method for manufacturing a semiconductor test wafer according to claim 12, wherein the Each chip also has a redistributed circuit located above the test circuit and electrically connected to the test circuit, and a dielectric layer covering the redistributed circuit and having at least one opening. The electrical connection pads and the redistributed circuit They are electrically connected and exposed to the outside from the corresponding openings.

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