TWM679183U - Silicon carbide oxide semiconductor field-effect transistor - Google Patents

Abstract

A silicon carbide gold oxide semiconductor field-effect transistor includes a silicon carbide substrate, an epitaxial layer, a well region, a heavily doped region, a source, a planar gate structure, and a contact metal. The heavily doped region is located within the well region and its depth is not less than the depth of the well region. The source is disposed in the well region and above the heavily doped region, defining an upward-facing three-dimensional trench with the heavily doped region. The planar gate structure is disposed above the epitaxial layer and connected to the source. The contact metal is electrically connected to the heavily doped region and the source through the three-dimensional groove, thereby increasing the contact area and reducing the channel resistance of the source, and thus reducing the overall conduction resistance.

Description

Silicon carbide gold oxide semiconductor field-effect transistor

This invention relates to a field-effect transistor, and more particularly to a silicon carbide gold oxide field-effect transistor.

In response to the development of 5G, artificial intelligence, and other technological industries, there is a need to develop electronic devices that can support high-speed computing, high-frequency communication, and high power. However, existing silicon (Si)-based components are no longer sufficient to meet these demands. In contrast, silicon carbide (SiC) has a bandgap approximately three times that of silicon, a breakdown electric field ten times that of silicon, and a higher thermal conductivity. Therefore, silicon carbide-based electronic components exhibit better stability in high-temperature, high-voltage, or high-current operating environments.

Taking a planar SiC MOSFET as an example, the transistor's on-resistance (R _{_on} ) includes at least the source channel resistance (R _{_channel} ) and the drift resistance (R _{_drift} ). On-resistance represents the resistance between the source and drain when the transistor is in the on-state; a lower on-resistance means lower power loss during conduction. However, the current source-to-source contact resistance is still relatively high, preventing a further reduction in the overall on-resistance (R _{_on} ). Therefore, a device design is needed to further reduce the on-resistance (R _{_on} ) of SiC MOSFETs.

Therefore, the objective of this invention is to provide a silicon carbide metal-oxide-semiconductor field-effect transistor that can reduce source contact resistance.

Therefore, this novel silicon carbide gold oxide field-effect transistor includes a silicon carbide substrate, an epitaxial layer, a well region, a heavily doped region, a source, two planar gate structures, and a contact metal.

The epitaxial layer is disposed on the upper side of the silicon carbide substrate. The well region is disposed on the upper side of the epitaxial layer. The heavily doped region is located within the well region, and its depth is not less than the depth of the well region. The source electrode is disposed in the well region, located above the heavily doped region, and together with the heavily doped region, defines an upward-facing three-dimensional trench. The planar gate structures are disposed above the epitaxial layer and are respectively connected to the source electrode. The contact metal is electrically connected to the heavily doped region and the source electrode through the three-dimensional trench.

The advantage of this new design is that the contact metal electrically connects the source and the heavily doped region through the three-dimensional groove, thereby increasing the contact area and reducing the contact resistance of the source, and thus reducing the overall on-resistance of the MOSFET.

Referring to Figure 1, one embodiment of this novel silicon carbide gold oxide semiconductor field-effect transistor includes multiple transistor units 1 and an outer ring structure 2.

It should be noted that the novel silicon carbide gold-oxide-semiconductor field-effect transistor comprises multiple periodically arranged transistor units 1, but for ease of explanation, only the structure of a single transistor unit 1 is shown in Figure 2. The transistor unit 1 includes a silicon carbide substrate 11, an epitaxial layer 12, a well region 13, a heavily doped region 14, a source 15, a planar gate structure 16, a junction field-effect transistor 17, a dielectric layer 3, an ohmic contact layer 4, and a contact metal 5.

The epitaxial layer 12 is disposed on the upper side of the silicon carbide substrate 11, and its material includes silicon carbide. The well region 13 is disposed on the upper side of the epitaxial layer 12 and is formed by a portion of the epitaxial layer 12 through a first type of doping. Optionally, the first type of doping is P-type doping. The heavily doped region 14 is located within the well region 13 and is formed by a portion of the well region 13 through a first type of heavy doping. The source electrode 15 is disposed in the well region 13 and is formed by a portion of the epitaxial layer 12 through a second type of doping. It is distributed above the heavily doped region 14 and together with the heavily doped region 14 defines an upward-facing three-dimensional groove 101. Optionally, the second type of doping is N-type doping. It should be noted that Figure 2 shows that a single transistor unit 1 appears to contain two sources electrode 15, but in reality, there is only one source electrode 15, which, when viewed from the side, is distributed precisely on both sides above the heavily doped region 14.

Specifically, the doping region 14 has a top surface 141, the source electrode 15 has a top surface 151 and an inner surface 152, and the three-dimensional groove 101 is formed by the top surface 141 of the doping region 14 and the inner surface 152 of the source electrode 15.

The planar gate structure 16 is disposed above the epitaxial layer 12 and connected to the source 15. Specifically, the planar gate structure 16 has an oxide layer 161 and a polycrystalline silicon layer 162. Referring to FIG1, the junction gate field effect transistor 17 (JFET) is disposed between the epitaxial layer 12 and the planar gate structure 16, and is located between the adjacent well regions 13. It should be noted that in the single transistor unit 1 shown in Figure 2, the planar gate structure 16 appears to be one on each side, but in reality, there is half on each side. Therefore, in a single transistor unit 1, there is only one planar gate structure 16. Referring to Figure 1, the half planar gate structure 16 needs to be combined with the other half planar gate structure 16 of the adjacent transistor unit 1 to form a complete planar gate structure 16. Similarly, the calculation method for the junction field-effect transistor 17 is the same; in a single transistor unit 1, there is only one junction field-effect transistor 17.

Specifically, when the first type of doping of the well regions 13 is P-type doping, the junction field-effect transistor 17 will adopt an N-type JFET to reduce the on-resistance.

The dielectric layer 3 fills the space between the planar gate structure 16, the source electrode 15, and the contact metal 5. The dielectric layer 3 has a through hole 301 that extends downward through the three-dimensional groove 101.

The contact metal 5 extends downward through the through-hole 301 and fills the three-dimensional groove 101, and electrically connects the top surface 141 of the heavily doped region 14 and the top surface 151 and inner surface 152 of the source 15 through the three-dimensional groove 101. The ohmic contact layer 4 is disposed between the contact metal 5 and the electrical connection areas of the heavily doped region 14 and the source 15.

Referring to Figure 1, the outer ring structure 2 includes multiple edge termination rings 21 surrounding the outer side of the MOSFET cell 1. These edge termination rings 21 are of the same type 1 doping as the well regions 13, and their depth (D1) is the same as the depth (D2) of the heavily doped region 14. By adjusting the width and spacing of these edge termination rings 21, the voltage in the MOSFET cell 1 can be more evenly distributed, increasing the stability of MOSFET operation.

In this embodiment, the number of pressure rings 21 is four, but this is not the limitation in other embodiments of this embodiment, and the number of pressure rings 21 can be varied arbitrarily as needed.

Referring to Figure 3, which is a flowchart of the manufacturing method of this embodiment, including steps S1 to S10, the following descriptions are in conjunction with Figures 4 to 14.

Referring to Figure 4, in this step S1, a silicon carbide substrate 11 is provided.

In step S2, an epitaxial layer 12 is formed on the silicon carbide substrate 11. Specifically, the material of the epitaxial layer 12 includes silicon carbide.

In step S3, a first mask 71 is formed, and a portion of the epitaxial layer 12 is subjected to a first type of doping to form a well region 61. Specifically, the first type of doping is P-type doping, and the corresponding dopant is, for example, but not limited to, aluminum, boron, gallium, or beryllium.

In step S4, referring to Figure 5, a second mask 72 is formed, and then a second type of doping is performed on the middle region of the predetermined well area 61 to form a second type of doped region 62. The region in the predetermined well area 61 that has not undergone the second type of doping forms a well area 13. Then, the first mask 71 and the second mask 72 are removed. Specifically, the second type of doping is N-type doping, and the corresponding dopant is, for example, but not limited to, nitrogen or phosphorus.

The second mask 72 is formed while retaining the first mask 71, and the second mask 72 covers the top and side of the first mask 71. This allows the first type of doping and the second type of doping to be performed consecutively to define the well area predetermined area 61 and the second type of doping area 62, respectively. Finally, the first mask 71 and the second mask 72 are removed together, which has the advantage of simplifying the process steps.

In step S5, referring to Figure 6, a first-type doping region 63 is formed by performing first-type doping on the central region of the second-type doped region 62 of each transistor unit 1 through a third mask 73. At the same time, the outer periphery of the well region 13 of the outermost transistor unit 1 is simultaneously doped with first-type doping to form multiple withstand voltage rings 21. Specifically, the third mask 73 has multiple heavily doped region openings 701 and multiple withstand voltage ring openings 702. Therefore, the first type of dopants can reach the epitaxial layer 12 and the second type of dopant region 62 through the heavily doped region openings 701 and the pressure ring openings 702. Then, the third mask 73 is removed.

Thus, the regions located on either side of the first type of doped region 63 in the second type of doped region 62 form the source electrode 15. A portion of the first type of doped region 63 overlaps with the well region 13 to form a heavily doped region 14. The doping concentration of the heavily doped region 14 is higher than that of the well region 13. The depth (D1) of the pressure rings 21 is the same as the depth (D2) of the heavily doped region 14.

Alternatively, the depth (D2) of the heavily doped region 14 may be flush with the depth (D3) of the well region 13, as shown in Figure 1. Or, the depth (D2) of the heavily doped region 14 may be greater than the depth (D3) of the well region 13, as shown in Figure 2.

It should be noted that in this embodiment, the depth (D1) of the pressure ring 21, the depth (D2) of the heavily doped region 14, and the depth (D3) of the well region 13 are all calculated with reference to the top surface 151 of the source electrode 15 and in the direction towards the silicon carbide substrate 11.

Since the heavily doped region 14 and the pressure rings 21 are formed in the same step, it can be ensured that the depth of the pressure rings 21 is the same as the depth of the heavily doped region 14, and the pressure rings 21 and the heavily doped region 14 can be formed in the same process step, simplifying the process steps.

In step S6, referring to Figure 7, a planar gate structure 16 is formed above the epitaxial layer 12, and the planar gate structure 16 is connected to the source 15. Alternatively, before forming the planar gate structure 16, the junction field-effect transistor 17 can be formed on both sides of the well region 13.

In step S7, referring to Figure 8, a photoresist material 91 is coated on the upper surface of the planar gate structure 16, the first type doped region 63, and the source 15, and a pattern is formed on the photoresist material 91 using a photolithography process with a photomask 8. Specifically, the photomask 8 is a Contact Trench P+ Process Mask (CTPP Mask), mainly used to form the three-dimensional trench 101. Referring to Figure 9, an etch opening 901 is formed on the photoresist material 91. The etch opening 901 exposes the upper surface of the first type doped region 63.

Referring to Figure 10, by means of an etching process and through the etching opening 901, the portion of the first type of doped region 63 other than the heavily doped region 14 is removed, so that a three-dimensional groove 101 with the opening facing upward is formed between the source electrode 15 and the heavily doped region 14.

It must be specifically noted that steps S4 to S7 of the manufacturing method of this embodiment involve first performing a second type of doping on the middle region of the predetermined well area 61, then performing a first type of doping on the middle region of the second type of doped area 62 to form the heavily doped area 14, and finally removing the portion of the first type of doped area 63 other than the heavily doped area 14, thereby defining the range of the source electrode 15 and the heavily doped area 14. Since this process method does not require forming an island-shaped photoresist on the upper side of the middle region of the well area 61 before performing the second type of doping to form the source 15, the problem of low process yield caused by the collapse and deformation of the island-shaped photoresist can be avoided during the process.

In step S8, referring to Figure 11, a dielectric material 92 is deposited, and a fourth mask 74 is formed on the dielectric material 92. As shown in Figure 12, the through hole 301 connecting the three-dimensional trench 101 is formed in the dielectric material 92 by an etching process using the fourth mask 74. Then the fourth mask 74 is removed to form the dielectric layer 3.

In step S9, referring to Figure 13, the ohmic contact layer 4 is formed in the via 301, and the ohmic contact layer 4 covers the heavily doped region 14 and the source electrode 15.

In step S10, referring to FIG14, the contact metal 5 is formed on the dielectric layer 3. The contact metal 5 extends downward from the top surface 31 of one of the dielectric layers 3 through the through hole 301 and fills the three-dimensional groove 101, and is electrically connected to the top surface 141 of the heavily doped region 14 and the top surface 151 and inner surface 152 of the source 15 through the ohmic contact layer 4.

In summary, in this silicon carbide gold oxide MOSFET, the contact metal 5 electrically connects the source 15 and the heavily doped region 14 through the three-dimensional trench 101, thereby increasing the contact area and reducing the contact resistance of the source 15, and further reducing the overall on-resistance of the MOSFET. Therefore, this invention effectively achieves its intended purpose. Furthermore, the outer ring structure 2 ensures that the depth of the withstand voltage rings 21 is the same as the depth of the heavily doped region 14, simplifying the manufacturing process.

However, the above description is merely an embodiment of this utility model and should not be construed as limiting the scope of its implementation. Any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the patent specification shall still fall within the scope of this utility model.

1: Transistor Unit 101: Three-dimensional Groove 11: Silicon Carbide Substrate 12: Epitaxial Layer 13: Well Region 14: Heavily Doped Region 141: Top Surface 15: Source Electrode 151: Top Surface 152: Inner Surface 16: Planar Gate Structure 161: Oxide Layer 162: Polycrystalline Silicon Layer 17: Junction Field-Effect Transistor 2: Outer Ring Structure 21: Voltage Ring 3: Dielectric Layer 301: Through-Hole 31: Top Surface 4: Ohmic Contact Layer 5: Contact Metal 61: Well Region Predetermined Area 62: Type II Doped Region 63: Type I Doped Region 701: Heavy doping region opening; 702: Voltage withstand ring opening; 71: First mask; 72: Second mask; 73: Third mask; 74: Fourth mask; 8: Photomask; 901: Etching opening; 91: Photoresist material; 92: Dielectric material; D1: Depth of voltage withstand ring; D2: Depth of heavy doping region; D3: Depth of well area.

Other features and effects of this invention will be clearly shown in the embodiments with reference to the drawings, wherein: Figure 1 is a schematic diagram of one embodiment of the silicon carbide gold oxide semiconductor field-effect transistor of this invention; Figure 2 is a schematic diagram of one transistor unit of this embodiment; Figure 3 is a flowchart of the manufacturing method of this embodiment; Figure 4 is a partial cross-sectional side view of steps S1 to S3 of the manufacturing method; Figure 5 is a partial cross-sectional side view of step S4 of the manufacturing method; Figure 6 is a partial cross-sectional side view of step S5 of the manufacturing method; Figure 7 is a partial cross-sectional side view of step S6 of the manufacturing method; Figures 8 to 10 are partial cross-sectional side views of step S7 of the manufacturing method. Figures 11-12 are partial cross-sectional side views of step S8 of the manufacturing method; Figure 13 is a partial cross-sectional side view of step S9 of the manufacturing method; and Figure 14 is a partial cross-sectional side view of step S10 of the manufacturing method.

1: Transistor Unit

101: Three-dimensional ditch

11: Silicon carbide substrate

12: Epitaxial Layer

13: Well Area

14: Heavy Mixed Area

141: Top surface

15: Source

151: Top surface

152: Inner side

16: Planar gate structure

161: Oxide layer

162: Polycrystalline silicon layer

17: Junction Field-Effect Transistor

3: Dielectric layer

301: Through hole

4: Ohmic Contact Layer

5: Contact with metal

D2: Depth of the heavily mixed region

D3: Depth of the well area

Claims (7)

A silicon carbide gold oxide semiconductor field-effect transistor includes: a silicon carbide substrate; an epitaxial layer disposed on the upper side of the silicon carbide substrate; a well region disposed on the upper side of the epitaxial layer; a heavily doped region located within the well region; a source electrode disposed in the well region and distributed on the upper side of the heavily doped region, and together with the heavily doped region defining an upward-facing three-dimensional trench; a planar gate structure disposed above the epitaxial layer and connected to the source electrode; and a contact metal electrically connecting the heavily doped region and the source electrode through the three-dimensional trench. The silicon carbide gold oxide field-effect transistor as described in claim 1 further comprises at least one withstand ring surrounding the well region, wherein the depth of the at least one withstand ring is the same as the depth of the heavily doped region. The silicon carbide gold oxide field-effect transistor as described in claim 1, wherein the heavily doped region has a top surface, the source has a top surface and an inner surface, and the three-dimensional groove is formed by the top surface of the heavily doped region and the inner surface of the source. The silicon carbide gold oxide semiconductor field-effect transistor as described in claim 3, wherein the contact metal is electrically connected to the top surface of the heavily doped region and the top surface and inner surface of the source. The silicon carbide gold oxide field-effect transistor as described in claim 4 further includes an ohmic contact layer, wherein the ohmic contact layer is disposed between the contact metal and the electrically connected regions of the heavily doped region and the source. The silicon carbide gold oxide semiconductor field-effect transistor as described in claim 1 further includes a junction field-effect transistor, wherein the junction field-effect transistor is disposed between the epitaxial layer and the planar gate structure. The silicon carbide gold oxide semiconductor field-effect transistor as described in claim 1 further comprises a dielectric layer, wherein the dielectric layer fills between the planar gate structure, the source and the contact metal, the dielectric layer having a through-hole extending downward into the three-dimensional trench, the through-hole allowing the contact metal to extend downward and fill the three-dimensional trench.