CN118173603A - A vertical double-diffused power semiconductor device and a manufacturing method thereof - Google Patents
A vertical double-diffused power semiconductor device and a manufacturing method thereof Download PDFInfo
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
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- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/115—Resistive field plates, e.g. semi-insulating field plates
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- H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
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Abstract
The invention provides a vertical double-diffusion power semiconductor device and a manufacturing method thereof, wherein the device comprises: a substrate; an epitaxial layer disposed on the substrate; the epitaxial layer is provided with a groove which vertically penetrates through the epitaxial layer and extends to the substrate, and the inner wall of the groove is provided with an oxidation dielectric layer and a resistance field plate filled between the oxidation dielectric layers; the source electrode region and the P+ region are arranged in the epitaxial layer in parallel and are positioned on the top of the epitaxial layer; the channel region is arranged in the epitaxial layer and is positioned below the source electrode region and the P+ region; the source electrode is arranged on the top of the epitaxial layer and is positioned above the source electrode region, the P+ region, the oxidation dielectric layer and the resistance field plate; wherein the source electrode is electrically connected with the resistance field plate; the size of the resistance field plates which are distributed in a three-dimensional orthogonal mode is compressed in the vertical direction under the condition that the cross-sectional area of a primitive cell, an injection process and the like are not changed, and therefore the power density of the device is greatly improved.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a vertical double-diffusion power semiconductor device and a manufacturing method thereof.
Background
In the technical field of semiconductors, inspired by a Super junction technology (Super junction) based on PN junction charge balance, the in-vivo resistance field plate is found to have a PN junction-like effect, so that some active device structures based on the in-vivo resistance field plate are provided, and the active device structures have some advantages of relative PN junction superjunction performance.
For a VDMOS device, how to reduce the on-resistance of the device and improve the power density and the performance of the device are always a problem of days of old. Particularly, for a Super junction VDMOS device (Super junction structure is introduced on the basis of a traditional longitudinal double-diffusion metal oxide semiconductor), the resistor field plate can deplete impurities in the drift region, so that the effect of charge balance is achieved. However, when the power density of the device is improved by the traditional superjunction technology, the device cannot greatly reduce the on-resistance while maintaining the breakdown voltage due to the limitation of the double diffusion technology for reducing the area of the lateral cell, so that the power density under the same chip area is not high.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a vertical double-diffused power semiconductor device and a method for manufacturing the same, which are used for solving the problem that the power density and performance of the vertical double-diffused power semiconductor device cannot be improved in the prior art.
To achieve the above and other related objects, a first aspect of the present invention provides a vertical double diffusion power semiconductor device comprising: a substrate; an epitaxial layer disposed on the substrate; the epitaxial layer is provided with a groove which vertically penetrates through the epitaxial layer and extends to the substrate, and the inner wall of the groove is provided with an oxidation dielectric layer and a resistance field plate filled between the oxidation dielectric layers; the source electrode region and the P+ region are arranged in the epitaxial layer in parallel and are positioned on the top of the epitaxial layer; a channel region disposed in the epitaxial layer and below the source region and the p+ region; the source electrode is arranged on the top of the epitaxial layer and is positioned above the source region, the P+ region, the oxidation dielectric layer and the resistance field plate; wherein the source electrode is electrically connected with the resistive field plate.
In an embodiment of the present invention, a gate structure formed by a gate oxide layer and a polysilicon layer is sequentially disposed on a top surface of the epitaxial layer, and upward along a top of the epitaxial layer.
In an embodiment of the present invention, further includes: a drain electrode formed by metal evaporation under the substrate away from the epitaxial layer; and the grid electrode is a polycrystalline silicon layer at the top of the epitaxial layer and covers the channel region.
In an embodiment of the present invention, the oxide dielectric layer is respectively in contact with the channel region, the source region, and the p+ region, a plane in which the channel region, the source region, and the p+ region are parallel is parallel to the resistive field plate, and the resistive field plate is respectively perpendicular to a metal wiring direction between the channel region, the source region, and the p+ region.
In one embodiment of the present invention, the spacing between the trenches is 1-3 microns.
In one embodiment of the present invention, the trench extends to the substrate to a depth of 1-2 microns.
In one embodiment of the present invention, the resistive field plate is a semi-insulating polysilicon material.
In a second aspect, the present invention also provides a method for manufacturing a vertical double-diffused power semiconductor device, including: providing a substrate and forming an epitaxial layer on the substrate; forming a trench vertically through the epitaxial layer to the substrate; oxidizing the bottom and the side wall of the groove to form the oxidation dielectric layer, etching to remove the oxidation dielectric layer at the bottom of the groove, and filling the groove to form a semi-insulating resistance field plate; forming a channel region, a source region and a P+ region at the top of the interior of the epitaxial layer, wherein the oxidation dielectric layer is respectively contacted with the channel region, the source region and the P+ region, and the plane where the channel region, the source region and the P+ region are parallel is parallel to the resistance field plate; and depositing a passivation layer on the tops of the source region and the P+ region, and carrying out metal contact opening on the passivation layer to form a source electrode which is electrically connected with the source region and the resistance field plate respectively.
In an embodiment of the present invention, before forming the channel region, the source region, and the p+ region on top of the epitaxial layer, the method further includes:
Etching and removing semi-insulating materials except the grooves in the upper surface of the epitaxial layer, and carrying out surface planarization treatment; surface oxidation is carried out on the top of the epitaxial layer, and a gate oxide layer is formed; and growing gate polysilicon above the gate oxide layer, and performing polysilicon doping injection to form a polysilicon layer.
In an embodiment of the present invention, forming a channel region, a source region, and a p+ region on top of the epitaxial layer includes: performing first ion implantation and ion diffusion to form the channel region on the top of the interior of the epitaxial layer; performing second ion implantation of source heavy doping on the channel region close to one side of the grid electrode to form a source electrode region, wherein the source electrode region is positioned above the channel region; and performing third ion implantation and ion diffusion on the channel region at one side far away from the grid electrode to form the P+ region, wherein the P+ region is positioned above the channel region.
In an embodiment of the present invention, before depositing the passivation layer on top of the source region and the p+ region, the method further includes:
Forming a gate electrode on the polycrystalline silicon layer on the top of the epitaxial layer, wherein the gate electrode covers the channel region; the wiring direction of the gate electrode and the source electrode is perpendicular to the plane of the groove.
In an embodiment of the invention, after the source electrode is electrically connected to the resistive field plate, the method further includes:
and carrying out a back thinning process on the substrate to form a back metal contact.
As described above, the vertical double diffusion power semiconductor device and the method of manufacturing the same of the present invention have the following advantageous effects:
On the basis of a conventional MOS device, the MOS device provided by the invention carries out groove etching and filling of a resistance field plate material in the vertical direction of a polycrystalline gate (a gate oxide layer and a polycrystalline silicon layer) and a source electrode wiring; the electric field of the drift region is modulated through the resistance field plate, so that high breakdown voltage can be realized under high impurity concentration; the concentration of the resistance field plate which can be modulated is related to the width of the primary cell, the concentration of the drift region is effectively increased under the same breakdown voltage by compressing the width of the primary cell, and the on-resistance is reduced, but the size of the primary cell on a plane is limited by factors such as a process and the like; the size of the resistance field plates which are distributed in a three-dimensional orthogonal mode is compressed in the vertical direction under the condition that the cross-sectional area of a primitive cell, an injection process and the like are not changed, and therefore the power density of the device is greatly improved.
Drawings
FIG. 1 is a schematic diagram showing a three-dimensional structure of a cell of a vertical double-diffused power semiconductor device according to the present invention;
FIG. 2 is a right side view of a three-dimensional structure of a vertical double-diffused power semiconductor device according to the present invention;
FIG. 3 is a left side view of a three-dimensional structure of a vertical double-diffused power semiconductor device according to the present invention;
fig. 4 is a diagram showing the structure of an epitaxial layer in a vertical double diffusion power semiconductor device according to the present invention;
fig. 5 shows a trench structure diagram of a vertical double diffusion power semiconductor device according to the present invention;
FIG. 6 is a schematic diagram showing the structure of an oxide dielectric layer in a vertical double-diffused power semiconductor device according to the present invention;
FIG. 7 is a diagram showing the structure of a resistance field plate in a vertical double-diffused power semiconductor device according to the present invention;
Fig. 8 is a diagram showing the structure of a gate oxide layer and a polysilicon layer in a vertical double diffusion power semiconductor device according to the present invention;
fig. 9 is a view showing an ion implantation structure of each region in a vertical double diffusion power semiconductor device according to the present invention;
fig. 10 is a view showing a structure of a source electrode injection in a vertical double diffusion power semiconductor device according to the present invention;
FIG. 11 is a graph showing a first breakdown voltage simulation of a vertical double-diffused power semiconductor device according to the present invention;
FIG. 12 is a graph showing a second breakdown voltage simulation of a vertical double-diffused power semiconductor device according to the present invention;
Fig. 13 is a graph showing a third breakdown voltage simulation of a vertical double-diffused power semiconductor device according to the present invention.
Reference numerals illustrate:
1-substrate, 2-epitaxial layer, 3-trench, 4-oxide dielectric layer, 5-resistive dielectric field plate, 6-gate oxide layer, 7-polysilicon layer, 8-channel region, 9-source region, 10-P+ region, 11-source electrode
Detailed Description
The inventors found that: in the current superjunction structure device or super junction structure-like device, optimization of the contradictory relation between the breakdown voltage and the on-resistance of the device has been a bottleneck, and further reduction of the on-resistance has become more and more difficult under the condition that the breakdown voltage is kept unchanged.
Based on the above, the invention provides a vertical double-diffusion power semiconductor device and a technical scheme of a manufacturing method thereof: aiming at the fact that the super junction technology is further limited by a lateral cell area shrinking double diffusion technology, the invention provides a resistor field plate type high-power density VDMOS device design distributed in the vertical orthogonal direction and a manufacturing method thereof, which break through the key design and process design technology of the VDMOS device structure, compress the cell area in the longitudinal direction, greatly improve the modulating capability of the field plate on impurity concentration of a drift region, and form a standard-processed novel device structure and process design capability. By improving the field plate from being parallel to the direction of the cells to be vertical to the cells, the cell volume can be reduced in the vertical direction, the on-resistance can be greatly reduced while the breakdown voltage is maintained, and higher power density can be realized under the same chip area. The process development route of More than Moore combines with the modern mainstream plane process from the pure theory, can consider the development of compatible plane 2D process to 2.5D, 3D quasi-plane compatible process and IC technology, specifically surrounds the deep slot technology as the core process technology, increases half dimension or one dimension (0.5D or 1D) in theory through the structural principle to systematically further improve the performance or cost performance of the existing IC and device, and provides the possibility of increasing the potential of the performance or performance multiple or even order of magnitude systematic performance in theory.
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 13. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. The structures, proportions, sizes, etc. shown in the drawings attached hereto are for illustration purposes only and are not intended to limit the scope of the invention, which is defined by the claims, but rather by the claims.
Referring to fig. 1, a schematic three-dimensional structure of a cell of a vertical double-diffused power semiconductor device according to the present invention is shown, which includes:
A substrate 1; wherein an N-type heavily doped substrate 1 is provided, the resistivity of which is typically small, such as optionally 2.8 ohm-cm; ohm cm represents the resistance per centimeter of length. The resistivity is an index describing the conductive properties of a substance and reflects the impeding effect of the substance on current per unit length and per unit cross-sectional area.
An epitaxial layer 2 disposed on the substrate 1; for example, a lightly doped N-type epitaxial layer 2 with a certain thickness is grown on the top layer of the substrate 1 as a drift region, the resistivity of the epitaxial layer is one of the determinants of the breakdown voltage of the device, the higher the resistivity, the lower the breakdown voltage, the smaller the specific on-resistance, and the concentration of the epitaxial layer is determined according to the requirement.
A groove 3 is formed in the epitaxial layer 2, the groove 3 vertically penetrates through the epitaxial layer 2 and extends to the substrate 1, and an oxidation dielectric layer 4 and a resistance field plate 5 filled between the oxidation dielectric layers are arranged on the inner wall of the groove 3;
it should be noted that, the trench 3 is etched, where specific parameters of the trench (including the number, depth and width of the trench) need to be designed according to the working voltage of the high-voltage MOS device and according to the process implementation capability, the dimensions of the semi-insulating resistive field plate 5 and the oxide dielectric layer 4 formed in the same trench and the optimal area required by the MOS need to be considered simultaneously in the design process, and optionally, in this example, the etching depth is 35um and the width is 0.6um, the bottom is connected to the substrate, for example, the etching depth may extend vertically through the epitaxial layer to 1-2um below the substrate, so that the resistive field plate may be directly connected to the substrate, and meanwhile, the interval between the trenches is 1-3 micrometers, for example, the distances between the trenches are z=1um, z=2um, and z=3um respectively.
It should be noted that the semi-insulating resistive field plate 5 and the oxide dielectric layer 4 form a semi-insulating resistive field plate structure in the trench 3, and as shown in fig. 1, the resistive field plate material and the field plate dielectric layer structure connected with the substrate are adjusted in the Z-axis direction, so that the power density of the device is increased under the condition of considering the actual process while the effects of the impurity concentration and the on-resistance of the original modulation drift region are maintained.
For example, a silicon dioxide film is grown on the side wall and the bottom of the trench by using a thermal oxidation method to form an oxidation dielectric layer, the oxidation dielectric layer at the bottom is etched, the trench is filled with semi-insulating polysilicon material along the top to the bottom of the trench and is contacted with the substrate, the semi-insulating polysilicon of the region outside the trench is etched and removed to perform surface planarization treatment, so as to form a resistance dielectric field plate, namely, a resistance field plate 5, preferably, a chemical mechanical polishing mode can be adopted, as shown in fig. 1, the oxidation dielectric layer 4 is contacted with a channel region (namely, a P communication region) 8, a source region 9 is contacted with a P plus region (namely, a p+ region) 10, and the same plane where the source region 9, the p+ region 10 and the channel region are located is parallel to the resistance field plate 5 and is vertically and orthogonally contacted with the wiring direction of source metal (namely, a source electrode 11).
A source region 9 and a p+ region 10 arranged in parallel in the epitaxial layer 2 and positioned on top of the epitaxial layer 2;
a channel region 8 disposed in the epitaxial layer 2 and below the source region 9 and the p+ region 10;
For example, performing boron ion implantation after photoetching the top region of the epitaxial layer 2 by photoetching, for example, adopting 80kev,3e15 cm -2 implantation conditions, and forming a P channel region 8 by high-temperature annealing, so as to control the junction depth to be about 2 μm; forming a source region 9 by performing N-type ion implantation in a P-type channel region close to one side of a gate electrode through photoetching, wherein arsenic ions or phosphorus ions are optionally implanted, and the concentration of the heavily doped implantation in the region is 5e15 cm -2; performing boron ion implantation in the P-type channel region at one side far away from the grid electrode through photoetching to form a P plus region 10, wherein the P plus region is heavily doped; annealing is performed to control the junction depth of the source region and form an effective channel of the MOS device with the region 8 below the gate region.
A source electrode 11 disposed on top of the epitaxial layer 2 and located above the source region 9, the p+ region 10, the oxide dielectric layer 4 and the resistive field plate 5; wherein the source electrode 11 is electrically connected to the resistive field plate 5.
Depositing a passivation layer on top of the epitaxial layer 2, and forming a metal wiring layer and an alloy by performing a source contact opening and a gate contact opening on the passivation layer, wherein the source metal 11 must be in contact with the resistive field plate region 5; and carrying out a back thinning process on the substrate to form a back metal contact.
In the above manner, on the basis of the conventional MOS device, the MOS device provided in the present embodiment performs trench etching and performs resistive field plate material filling in the direction perpendicular to the source electrode wiring of the poly gate (gate oxide layer and poly silicon layer); the electric field of the drift region is modulated through the resistance field plate, so that high breakdown voltage can be realized under high impurity concentration; the concentration of the resistance field plate which can be modulated is related to the width of the primary cell, the concentration of the drift region is effectively increased under the same breakdown voltage by compressing the width of the primary cell, and the on-resistance is reduced, but the size of the primary cell on a plane is limited by factors such as a process and the like; the size of the three-dimensional orthogonal distributed resistance field plates is compressed in the vertical direction (namely the Z-axis direction) under the condition of not changing the cross-sectional area of the primary cells, the injection process and the like, so that the power density of the device is greatly improved.
In some embodiments, a gate structure formed by a gate oxide layer and a polysilicon layer is sequentially disposed on the top surface of the epitaxial layer, and upward along the top of the epitaxial layer.
For example, an epitaxial layer (epi layer) is a silicon layer that is used to optimize device performance and provide additional thickness. The gate oxide layer is typically a very thin insulating silicon oxide (SiO 2) layer that is located between the polysilicon gate and the silicon substrate to provide isolation and insulation.
By polysilicon layer is meant a layer composed of polysilicon material, which is commonly used to construct the gate of a MOS device. The polysilicon layer is located over the gate oxide layer, and forms a gate structure of the MOS device together with the gate oxide layer.
In some embodiments, further comprising: a drain electrode (not shown) formed by metal evaporation under the substrate away from the epitaxial layer; a gate electrode (not shown) is a polysilicon layer on top of the epitaxial layer, covering the channel region.
In the above manner, during the operation of the MOS device, when the gate voltage is properly adjusted, the channel region is switched between the conductive and non-conductive states, so as to realize the switching control of the current, and the drain electrode is used for collecting or injecting the current, depending on the operation mode of the device.
In some embodiments, the oxidation dielectric layer is respectively contacted with a channel region, a source region and a p+ region, a plane where the channel region, the source region and the p+ region are parallel is parallel to the resistance field plate, and the resistance field plate is respectively perpendicular to the metal wiring direction among the channel region, the source region and the p+ region.
The cell area is compressed in the longitudinal direction, so that the impurity concentration modulating capability of the field plate on the (epitaxial layer) drift region is greatly improved, and the novel device structure and process design capability are formed. By improving the field plate from being parallel to the direction of the cells to be vertical to the cells, the cell volume can be reduced in the vertical direction, the on-resistance can be greatly reduced while the breakdown voltage is maintained, and higher power density can be realized under the same chip area.
The implementation of the technical scheme is described below by taking a P-channel high-voltage MOS device as an example, and other ways of implementing the present disclosure should not be considered as different schemes from the present scheme, and the corresponding N-channel high-voltage MOS device and P-channel MOS device are structurally equivalent, doped differently, and the process needs to be implemented by making certain adjustments according to the different process characteristics of the P-type and N-type impurities, which are well known to those skilled in the art, and should not be considered as being not limited by the present disclosure. The following examples describe the processes that are well known to those of ordinary skill in the art and are not described in great detail.
In other embodiments, the present invention further provides a method for manufacturing a vertical double-diffused power semiconductor device, including:
Step S1, providing a substrate and forming an epitaxial layer on the substrate;
In step S1, see fig. 4 in detail, a substrate 1 is provided as a drain region of a MOS device, which is an N-type doped semiconductor material (e.g. silicon, silicon carbide, gallium arsenide, etc.); an epitaxial layer 2 is formed on the substrate 1, and the epitaxial layer 2 is also an N-type doped semiconductor material as a drift region of the MOS device.
Wherein the substrate 1 is heavily doped, and the epitaxial layer 2 is lightly doped; the thickness of the epitaxial layer 2 may be flexibly designed as appropriate, for example, for a breakdown voltage of 600V, and the thickness of the epitaxial wafer 2 may be designed to be 30 μm.
Step S2, forming a groove, wherein the groove vertically penetrates through the epitaxial layer to the substrate;
in step S2, referring to fig. 5 in detail, a trench with a predetermined pattern is etched, the trench is located on a plane parallel to a P-well (i.e., P-channel) formed subsequently and the source region, the bottom is connected to the substrate, and two sides of the trench are connected to the drift region P-well, and the source n+ is connected to the P plus (i.e., p+) region.
The grooves vertically penetrate through the epitaxial layer to extend to the substrate, and 1-2 micrometer grooves are formed in the substrate, so that the grooves are communicated with the substrate.
Step S3, oxidizing the bottom and the side wall of the groove to form the oxidation dielectric layer, etching to remove the oxidation dielectric layer at the bottom of the groove, and filling the groove to form a semi-insulating resistance field plate;
In step S3, see FIGS. 6-7 for details, a silicon dioxide film is grown on the side wall and bottom of the trench by thermal oxidation to form a field plate dielectric layer, i.e., an oxidized dielectric layer; etching the silicon dioxide film layer until the substrate at the bottom of the groove is exposed; and growing semi-insulating polycrystalline silicon material by using an epitaxial method, and filling the grooves to form a resistance field plate, wherein the resistance field plate is connected with the substrate.
The resistor field plate is made of semi-insulating polycrystalline silicon material, is a structure for improving the performance of power MOSFET (metal oxide semiconductor field effect transistor) and other power semiconductor devices, and is mainly used for reducing electric field peaks by expanding a depletion region so as to improve the breakdown voltage and reliability of the devices. While the advantages of semi-insulating polysilicon include its relatively high resistivity, good thermal stability, and good compatibility with silicon-based device processes, these characteristics make it one of the ideal materials for fabricating resistive field plates.
S4, forming a channel region, a source region and a P+ region at the top of the interior of the epitaxial layer, wherein the oxidation dielectric layer is respectively contacted with the channel region, the source region and the P+ region, and the plane where the channel region, the source region and the P+ region are parallel is parallel to the resistance field plate;
In step S4, see fig. 9 for details, prepared by: performing first ion implantation in the top region of the epitaxial layer through a photomask pattern, and then diffusing by utilizing a high-temperature annealing condition to form a channel region; performing second ion implantation of source heavy doping through the photoetching pattern, wherein the region is positioned on the channel region close to the grid polysilicon; and carrying out third ion implantation of the P plus region beside the source region through the photoetching pattern, and then carrying out ion diffusion through annealing.
For example, the boron ion implantation is performed after the top region of the epitaxial layer is photoetched by photoetching, for example, the first ion implantation is performed firstly, the implantation condition of 80kev,3e13 cm -2 is adopted, then the first ion diffusion is performed under the protection of inert gas, for example, the ion diffusion at 1050 ℃ for 90min, and a P-type doped MOS channel region is formed at the top inside the epitaxial layer 2, namely, a P-channel 8 is formed by high-temperature annealing, so that the junction depth is controlled to be about 2 μm.
For example, N-type ion implantation is performed in the P-type channel region near one side of the gate electrode to form a source region, for example, the source region is first subjected to photolithography, photoresist is used as a shielding mask, and then a second ion implantation is performed, arsenic ion or phosphorus ion implantation is adopted, and the heavy doping implantation concentration of the region can be selected to be 5e15 cm -2; source regions 9 are formed.
For example, a P plus region 10 is formed by performing boron ion implantation in the P-type channel region on the side remote from the gate electrode by photolithography, the region being heavily doped; for example, the P-channel region is first subjected to photolithography, photoresist is used as a shielding mask, then a third ion implantation, such as boron ion implantation of 5e10 15cm-2, is performed, and then annealing diffusion is performed to control the junction depth of the source region, so that an effective channel of the MOS device is formed below the gate region with the P-channel.
In step S4, before forming the channel region, the source region, and the p+ region on top of the epitaxial layer, the method further includes:
S5, etching and removing the semi-insulating material except the groove in the upper surface of the epitaxial layer, and carrying out surface planarization treatment; surface oxidation is carried out on the top of the epitaxial layer, and a gate oxide layer is formed; and growing gate polysilicon above the gate oxide layer, and performing polysilicon doping injection to form a polysilicon layer.
In step S5, see fig. 8 in detail, the semi-insulating polysilicon material in the area outside the trench is etched and removed by using a photolithography pattern, and surface planarization is performed to oxidize the surface of the epitaxial layer 2, so as to form a gate oxide layer, where the thickness of the optional gate oxide layer is 60nm; growing a polysilicon layer with a certain thickness above the oxide layer, carrying out P-type heavy doping, and then annealing to form gate contact; and photoetching and etching to form a gate oxide layer 6 and a polysilicon layer 7, and then carrying out gate polycrystalline oxidation.
In addition, the step S5 may be performed before the step S4 or after the step S4, and both execution logics are not described herein.
And S6, depositing a passivation layer on the top surface of the epitaxial layer, and carrying out metal contact opening on the passivation layer to form a source electrode which is electrically connected with the source region and the resistance field plate respectively.
In step S6, see fig. 10 in detail, a passivation layer is deposited on top of the source region and p+ region and metal contact openings are made to form surface source and gate metal contacts; for example, a metal wiring layer and an alloy are formed on the passivation layer and source contact openings and gate contact openings are performed, wherein a source (metal or alloy) electrode must be in contact with the resistive field plate 5.
It should be understood that a passivation layer is formed on the surface of the device (corresponding to the gate oxide layer, the polysilicon layer, the source region and the p+ region) by deposition, then a source contact hole is formed in the passivation layer, a metal layer is deposited and is subjected to photoetching to form a source electrode, and the source electrode is arranged on the surface of the device and is connected with the source region n+, the P plus region and the resistor field plate.
In addition, a back thinning process is carried out on the substrate, and metal is deposited to form drain electrode contact.
Further, it is understood that the process of forming the gate electrode is similar to that, and the description of the electrode further included in the vertical cell distributed resistance field plate modulation VDMOS device is omitted herein:
A drain electrode formed by metal evaporation under the substrate away from the drift region;
The grid electrode is a polycrystalline silicon area on the top of the epitaxial layer and covers the channel of the MOS device.
That is, a gate electrode is formed on the polysilicon layer on top of the epitaxial layer, the gate electrode overlying the channel region; the wiring direction of the gate electrode and the source electrode is perpendicular to the plane of the groove.
In this embodiment, the structure of the resistive field plate material and the field plate dielectric layer connected to the substrate is adjusted, so that the power density of the device is increased under the condition of considering the actual process while the effects of the impurity concentration and the on-resistance of the original modulation drift region are maintained.
By the mode, the vertical double-diffusion field effect transistor with the vertical distribution resistance field plate for modulating the conductance modulation provides a novel cell structure on the basis of the super-junction VDMOS device with the two-dimensional plane distribution. The principle of the device is that the resistor field plates at two sides can modulate the drift region area in the middle of the resistor field plates, and the one-dimensional longitudinal electric field of the drift region is improved to be a two-dimensional orthogonal electric field, so that the longitudinal electric field becomes uniform. The concentration of the depletable drift region is proportional to the distance between the two resistive field plates. When the resistance field plate is not located on the XY plane as shown in FIG. 1 but located on the YZ plane, by reducing the distance in the Z direction, the process difficulty of reducing the cell volume can be effectively improved and reduced without changing the process parameters such as injection and the like, and meanwhile, the ratio of the breakdown voltage to the specific on-resistance of the device can be reduced.
In this embodiment, see fig. 11 to 13 for details, in the embodiment, there are three cell results of the trench distances z=1 μm, z=2 μm and z=3 μm. And under the condition of the same doping, epitaxial concentration and doping size, the breakdown voltages of the three are simulated. When the concentration of the epitaxial layer is 2E15 cm -3, the drift region can be exhausted by cell structures with three intervals, and the breakdown voltage reaches more than 600V; referring to FIG. 11, when the epitaxial layer concentration is 5E15 cm -3, the cell drift region with 3 μm pitch cannot be fully depleted, the breakdown voltage drops to 500V, and the remaining two structures remain around 600V; as the epitaxial layer concentration is further increased to 1e16 cm -3, detailed in fig. 12, the breakdown voltage of the cell at the pitch of 3 μm drops rapidly to about 210V, the cell at the pitch of 2 μm drops to 450V, and detailed in fig. 13, the cell at the pitch of 1 μm remains at the breakdown voltage of 607V. Compared with a cell with a groove distance of Z=3μm, the doping concentration of the drift region can be increased by 5 times under the breakdown voltage of 600V by the 1 μm spacing, so that the purposes of improving the power density and the on-resistance are achieved, and the power density of the VDMOS device is increased by times based on the post-molar thinking of the microelectronic device by means of the processing capacity of a relatively large critical dimension process.
In summary, the invention discloses a vertical double-diffused power semiconductor device and a manufacturing method thereof, and the provided MOS device is characterized in that on the basis of a conventional MOS device, trench etching is performed and the filling of a resistance field plate material is performed in the vertical direction of a polycrystalline gate (a gate oxide layer and a polycrystalline silicon layer) and a source electrode wiring; the electric field of the drift region is modulated through the resistance field plate, so that high breakdown voltage can be realized under high impurity concentration; the concentration of the resistance field plate which can be modulated is related to the width of the primary cell, the concentration of the drift region is effectively increased under the same breakdown voltage by compressing the width of the primary cell, and the on-resistance is reduced, but the size of the primary cell on a plane is limited by factors such as a process and the like; the size of the resistance field plates which are distributed in a three-dimensional orthogonal mode is compressed in the vertical direction under the condition that the cross-sectional area of a primitive cell, an injection process and the like are not changed, and therefore the power density of the device is greatly improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (11)
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