TWM645270U - Semiconductor structure - Google Patents
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- TWM645270U TWM645270U TW112202682U TW112202682U TWM645270U TW M645270 U TWM645270 U TW M645270U TW 112202682 U TW112202682 U TW 112202682U TW 112202682 U TW112202682 U TW 112202682U TW M645270 U TWM645270 U TW M645270U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 230000003287 optical effect Effects 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 230000000903 blocking effect Effects 0.000 claims abstract description 41
- 239000003292 glue Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 description 28
- 238000010586 diagram Methods 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 3
- 229920000297 Rayon Polymers 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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Abstract
Description
本創作係關於一種半導體結構,尤其是一種用於感測裝置之環境光或距離的感測器裝置。The present invention relates to a semiconductor structure, particularly a sensor device for sensing ambient light or distance of a device.
在感測裝置的環境光或距離之感測器裝置的技術領域中,當紅外線晶片發光或光線在經過可透光的透明膠時會導致光線遭到干擾而產生散射。因此,離開裝置的光線不一定是直線的,可能在其他角度仍會有光線折射進入感測器裝置的收光區(或稱光學接收區),進而影響感測器裝置的測量準確性。In the technical field of sensor devices for sensing ambient light or distance of a device, when an infrared chip emits light or when the light passes through a light-transmissive transparent glue, the light will be interfered and scattered. Therefore, the light leaving the device is not necessarily straight. There may still be light refracted at other angles and enter the light receiving area (or optical receiving area) of the sensor device, thereby affecting the measurement accuracy of the sensor device.
在習知的技術上,藉由 「雙模(Double mold) 」 或 「一模一蓋(one mold one cap) 」的製程來製造感測器裝置可有效降低光學接收區(Photic Detecting Zone)串音干擾的問題。如圖1所示,由習知製程製造之半導體結構具有基板S,基板S設置的發光晶片和電路板之間隔著光學阻擋層B,使得發光晶片放射的光沿著入射光路徑I照射到物件O。接著光反射後沿著反射光路徑R射向電路板。但此製程的配置將使感測器裝置的半導體結構受限於壓模模流和上蓋的規格,導致半導體結構的尺寸勢必加大,不利於應用在例如智慧型手機的零件上。此外,習知技術之光學阻擋層的上蓋部分並未阻擋多餘的光線,使得電路板接收入射光遭受可透光之透明膠的干擾後,進而造成接收光後產生的訊號不夠準確,測量的準確性因而降低。In the conventional technology, manufacturing the sensor device through a "double mold" or "one mold one cap" process can effectively reduce the number of optical receiving zone (Photic Detecting Zone) strings. The problem of sound interference. As shown in Figure 1, a semiconductor structure manufactured by a conventional process has a substrate S. The light-emitting chip and the circuit board provided on the substrate S are separated by an optical blocking layer B, so that the light emitted by the light-emitting chip irradiates the object along the incident light path I. O. The light is then reflected and directed toward the circuit board along the reflected light path R. However, the configuration of this process will limit the semiconductor structure of the sensor device to the specifications of the die mold flow and the upper cover. As a result, the size of the semiconductor structure will inevitably increase, which is not conducive to application in parts such as smartphones. In addition, the upper cover part of the optical blocking layer in the conventional technology does not block excess light, so that when the circuit board receives the incident light, it is interfered by the light-transmissive transparent glue, which in turn causes the signal generated after receiving the light to be inaccurate, and the measurement is not accurate. Sexuality is thus reduced.
因此,在該領域上亟需一種改良之用於感測器裝置的半導體結構以克服上述的缺點。Therefore, there is an urgent need in this field for an improved semiconductor structure for a sensor device to overcome the above-mentioned shortcomings.
為了解決上述的技術問題,本創作提供一種半導體結構,其包括:一基板,其具有安裝表面;一發光晶片及一電路板,該發光晶片及該電路板設置在該安裝表面上; 一第一可透光層,其封圍該電路板;一第二可透光層,其封圍該發光晶片;以及一光學阻擋層,其設置在該基板上且位於該發光晶片及該電路板之間,其中該光學阻擋層包括:至少一壁,其插入該基板;以及上蓋,其與該至少一壁連接並覆蓋該第一可透光層之一部分,以透過該第一可透光層形成一收光孔。In order to solve the above technical problems, the present invention provides a semiconductor structure, which includes: a substrate with a mounting surface; a light-emitting chip and a circuit board, the light-emitting chip and the circuit board are disposed on the mounting surface; a first A light-transmissive layer that encloses the circuit board; a second light-transmissible layer that encloses the light-emitting chip; and an optical blocking layer that is disposed on the substrate and between the light-emitting chip and the circuit board , wherein the optical blocking layer includes: at least one wall inserted into the substrate; and an upper cover connected to the at least one wall and covering a portion of the first light-transmissive layer to form a Light hole.
本創作提供之半導體結構中,該電路板為一撿光器。In the semiconductor structure provided by this invention, the circuit board is a light picker.
本創作提供之半導體結構中,該收光孔的位置對應於該撿光器的一收光區。In the semiconductor structure provided by this invention, the position of the light-collecting hole corresponds to a light-collecting area of the light picker.
本創作提供之半導體結構中,該光學阻擋層係以點膠的方式形成且該膠為黑膠。In the semiconductor structure provided by this invention, the optical blocking layer is formed by dispensing glue and the glue is black glue.
本創作提供之半導體結構中,該光學阻擋層係以壓模的方式形成。In the semiconductor structure provided by this invention, the optical blocking layer is formed by stamping.
本創作提供之半導體結構中,該收光孔的位置未對應於該電路板連接至該基板的連接線。In the semiconductor structure provided by this invention, the position of the light-collecting hole does not correspond to the connection line connecting the circuit board to the substrate.
本創作提供之半導體結構中,該上蓋係以點膠的方式形成。In the semiconductor structure provided by this invention, the upper cover is formed by dispensing glue.
本創作提供之半導體結構中,該上蓋覆蓋該第二可透光層的一部分,以透過該第二可透光層形成一發光孔。In the semiconductor structure provided by this invention, the upper cover covers a part of the second light-transmissive layer to form a light-emitting hole through the second light-transmissive layer.
本創作提供之半導體結構中,該發光孔的位置對應於該發光晶片。In the semiconductor structure provided by this invention, the position of the light-emitting hole corresponds to the light-emitting chip.
本創作提供之半導體結構中,該至少一壁的寬度大於該電路板及該發光晶片的寬度。In the semiconductor structure provided by this invention, the width of the at least one wall is greater than the width of the circuit board and the light-emitting chip.
本創作至少藉由「一光學阻擋層,其設置在該基板上且位於該發光晶片及該電路板之間」、「上蓋,其與該至少一壁連接並覆蓋該第一可透光層之一部分,以透過該第一可透光層形成一收光孔」之技術特徵,使得光學阻擋層可阻擋發光晶片和用於接收光之電路板之間的串音干擾,且可顯著降低元件尺寸而仍保有效能提升的有利功效,藉此能大幅應用在手機等攜帶式3C產品的環境光暨距離感測器上。This invention at least uses "an optical blocking layer, which is disposed on the substrate and between the light-emitting chip and the circuit board", and "a top cover, which is connected to the at least one wall and covers the first light-transmissive layer. Part of the technical feature is to form a light-collecting hole through the first light-transmissive layer, so that the optical blocking layer can block crosstalk interference between the light-emitting chip and the circuit board used to receive light, and can significantly reduce the component size. While still retaining the beneficial effect of performance improvement, it can be widely used in ambient light and distance sensors for portable 3C products such as mobile phones.
圖2A顯示根據本創作第一實施例之半導體結構的側剖面端視圖。圖2B顯示根據本創作第一實施例之半導體結構的俯視圖。圖3顯示根據本創作第一實施例之半導體結構的側剖面端視及光路徑示意圖。FIG. 2A shows a side cross-sectional end view of a semiconductor structure according to a first embodiment of the present invention. FIG. 2B shows a top view of a semiconductor structure according to the first embodiment of the present invention. FIG. 3 shows a side cross-sectional end view and a schematic light path diagram of the semiconductor structure according to the first embodiment of the present invention.
如圖2A及圖2B所示,根據本創作第一實施例的半導體結構100包括基板110、發光晶片120、電路板130、第一可透光層140、第二可透光層150以及光學阻擋層160。發光晶片120藉由黏膠122黏接在基板110的安裝表面112上,並透過第一連接線121連接至基板110上的電路接觸點(例如電極114)以供電給發光晶片120並傳送電子訊號來驅動發光晶片120。第二可透光層150係封圍並完全覆蓋發光晶片120,使發光晶片120被包覆在基板110上。As shown in FIGS. 2A and 2B , the semiconductor structure 100 according to the first embodiment of the present invention includes a substrate 110 , a light-emitting chip 120 , a circuit board 130 , a first light-transmissive layer 140 , a second light-transmissible layer 150 and an optical barrier. Layer 160. The light-emitting chip 120 is bonded to the mounting surface 112 of the substrate 110 through the adhesive 122, and is connected to the circuit contact points (such as electrodes 114) on the substrate 110 through the first connection wire 121 to supply power to the light-emitting chip 120 and transmit electronic signals. to drive the light emitting chip 120. The second light-transmissive layer 150 encloses and completely covers the light-emitting chip 120 so that the light-emitting chip 120 is covered on the substrate 110 .
電路板130藉由黏膠131黏接在基板110的安裝表面112上,並透過至少一條第二連接線132連接至基板110上的電路接觸點(例如電極113)以供電給電路板130並傳送電子訊號來驅動電路板130。第一可透光層140係封圍並完全覆蓋電路板130,使電路板130被包覆在基板110上。The circuit board 130 is adhered to the mounting surface 112 of the substrate 110 through adhesive 131, and is connected to circuit contact points (such as electrodes 113) on the substrate 110 through at least one second connection line 132 to supply power to the circuit board 130 and transmit power. Electronic signals drive the circuit board 130. The first light-transmissive layer 140 encloses and completely covers the circuit board 130 so that the circuit board 130 is covered on the substrate 110 .
第一透光層140和第二透光層150可由例如光學級環氧樹脂或類似者製成。黏膠122、131可為本創作之技術領域中習知的晶片黏結薄膜(Die Attach Film;DAF)等材料製成。第一連接線120和第二連接線132可由例如導電金屬材料的金焊線製成。The first light-transmitting layer 140 and the second light-transmitting layer 150 may be made of, for example, optical grade epoxy resin or the like. The adhesives 122 and 131 can be made of materials such as Die Attach Film (DAF) that are commonly known in the technical field of this invention. The first connection line 120 and the second connection line 132 may be made of, for example, gold bonding wires of conductive metal material.
如圖2A所示,光學阻擋層160設置在基板110上並位於發光晶片120和電路板130之間,用以阻擋發光晶片120發出的光直接進入可包括撿光器135的電路板130內,使撿光器135的收光區所接收的光都來自從物件直接反射的光。As shown in FIG. 2A , the optical blocking layer 160 is disposed on the substrate 110 and is located between the light-emitting chip 120 and the circuit board 130 to block the light emitted by the light-emitting chip 120 from directly entering the circuit board 130 that may include the light picker 135. The light received by the light collecting area of the light picker 135 comes from the light directly reflected from the object.
光學阻擋層160可包括上蓋162和壁161,壁161插入至基板110並固定連接在基板110上,用以阻擋發光晶片120發出的光線橫向直接被電路板130上的撿光器135接收。上蓋162係連接在壁161上往垂直於壁161直立方向的方向上往兩側延伸並覆蓋第一可透光層140和第二可透光層150的上表面。上蓋162開設有發光孔180及收光孔170。如圖2B所示,發光孔180的位置可對應於基板110上發光晶片120的位置,而收光孔170的位置可對應於電路板130上撿光器135中尤其是收光區的位置。換言之,收光孔170的位置未對應於該電路板130連接至該基板110的連接線(例如第二連接線132)。此外,光學阻擋層160或壁161的寬度D1大於電路板130的寬度D2及發光晶片120的寬度D3,從而也大於進光孔170及發光孔180的寬度。The optical blocking layer 160 may include an upper cover 162 and a wall 161. The wall 161 is inserted into the substrate 110 and fixedly connected to the substrate 110 to block the light emitted by the light-emitting chip 120 from being directly received laterally by the light picker 135 on the circuit board 130. The upper cover 162 is connected to the wall 161 and extends to both sides in a direction perpendicular to the upright direction of the wall 161 and covers the upper surfaces of the first light-transmissive layer 140 and the second light-transmissible layer 150 . The upper cover 162 is provided with a light emitting hole 180 and a light receiving hole 170 . As shown in FIG. 2B , the position of the light-emitting hole 180 may correspond to the position of the light-emitting chip 120 on the substrate 110 , and the position of the light-receiving hole 170 may correspond to the position of the light-collecting area of the light picker 135 on the circuit board 130 . In other words, the position of the light-receiving hole 170 does not correspond to the connection line (for example, the second connection line 132 ) connecting the circuit board 130 to the substrate 110 . In addition, the width D1 of the optical blocking layer 160 or the wall 161 is larger than the width D2 of the circuit board 130 and the width D3 of the light-emitting chip 120 , and thus is also larger than the widths of the light inlet hole 170 and the light emitting hole 180 .
如圖3所示,這使得光學阻擋層160的上蓋162可確保發光晶片120放出的光線在入射光區域Z0的範圍內通過發光孔180沿著入射光路徑I照射在物件O上,且進而確保從物件O上在第一反射光區域Z1反射的光線可通過進光孔170大致照射在電路板130上撿光器135的區域中;而沿著例如在第二反射光區域Z2中的第二反射光路徑R2的光,其並不是照射在撿光器135的區域中,則被光學阻擋層160的上蓋162阻擋在半導體結構100之外。如此,在本創作的第一實施例中,發光晶片120的放射出的光線被光學阻擋層160的壁161阻擋而不會直接由電路板130上的撿光器135接收,使得撿光器135的偵測效果更精準也減少發光晶片120和電路板130間的串音干擾。此外,不會照射在撿光器135上的反射光(例如沿著第二反射光路徑R2在第二反射光區域Z2內的光)也被光學阻擋層160的上蓋162阻擋,使得反射的光不會因為散射或繞射而進入撿光器135的收光區中,從而使撿光器135的偵測效果更精準。As shown in FIG. 3 , this enables the upper cover 162 of the optical blocking layer 160 to ensure that the light emitted by the light-emitting chip 120 passes through the light-emitting hole 180 along the incident light path I and irradiates the object O within the incident light area Z0, and further ensures that The light reflected from the object O in the first reflected light area Z1 can be illuminated roughly in the area of the light picker 135 on the circuit board 130 through the light inlet hole 170; while along the second reflected light area Z2, for example, The light of the reflected light path R2, which does not illuminate the area of the light picker 135, is blocked from the semiconductor structure 100 by the upper cover 162 of the optical blocking layer 160. In this way, in the first embodiment of the invention, the light emitted by the light-emitting chip 120 is blocked by the wall 161 of the optical blocking layer 160 and will not be directly received by the light picker 135 on the circuit board 130, so that the light picker 135 The detection effect is more accurate and the crosstalk interference between the light-emitting chip 120 and the circuit board 130 is reduced. In addition, the reflected light that does not illuminate the light picker 135 (for example, the light in the second reflected light area Z2 along the second reflected light path R2) is also blocked by the upper cover 162 of the optical blocking layer 160, so that the reflected light The light will not enter the light collecting area of the light picker 135 due to scattering or diffraction, thereby making the detection effect of the light picker 135 more accurate.
圖4顯示根據本創作第二實施例之半導體結構的側剖面端視圖。根據本創作第二實施例的半導體結構200包括基板210、發光晶片220、電路板230、第一可透光層240、第二可透光層250、光阻擋層260、收光孔270、發光孔280等元件,其中基板210、發光晶片220、發光晶片220的第一連接線221、電路板230、電路板230的第二連接線232、第一可透光層240、第二可透光層250、收光孔270、發光孔280、安裝表面214皆分別對應上述第一實施例中的基板110、發光晶片120、發光晶片120的第一連接線121、電路板130、電路板130的第二連接線132、第一可透光層140、第二可透光層150、收光孔170、發光孔180、安裝表面112,在此為了簡潔的緣故省略不贅述。FIG. 4 shows a side cross-sectional end view of a semiconductor structure according to a second embodiment of the present invention. The semiconductor structure 200 according to the second embodiment of the present invention includes a substrate 210, a light-emitting chip 220, a circuit board 230, a first light-transmissive layer 240, a second light-transmissible layer 250, a light blocking layer 260, a light-collecting hole 270, a light-emitting Hole 280 and other components, including the substrate 210, the light-emitting chip 220, the first connection line 221 of the light-emitting chip 220, the circuit board 230, the second connection line 232 of the circuit board 230, the first light-transmissive layer 240, the second light-transmissive layer The layer 250, the light-receiving hole 270, the light-emitting hole 280, and the mounting surface 214 respectively correspond to the substrate 110, the light-emitting chip 120, the first connection line 121 of the light-emitting chip 120, the circuit board 130, and the circuit board 130 in the first embodiment. The second connection line 132, the first light-transmissive layer 140, the second light-transmissible layer 150, the light-receiving hole 170, the light-emitting hole 180, and the mounting surface 112 are omitted here for the sake of brevity.
本創作第二實施例的光學阻擋層260可包括第一壁261、第二壁263、第三壁264及上蓋262。第一壁261、第二壁263及第三壁264分別插入至基板210並固定連接在基板210上,其中第一壁261係用以阻擋發光晶片220發出的光線橫向直接被電路板230上的撿光器235接收。第二壁263及第三壁264則分別設置在基板210彼此相對的兩個側邊上,亦即設置在第一壁261相對的兩側,用以使電路板230和發光晶片220不受到半導體結構200以外在裝置上其他零件的干擾,例如其他電子零件可能導致的串音干擾。上蓋262係固定連接在第一壁261、第二壁263及第三壁264上,從第二壁263以垂直於第一壁261、第二壁263及第三壁264直立方向的方向往第三壁264延伸並整體覆蓋第一可透光層240和第二可透光層250的上表面。上蓋262開設有發光孔280及收光孔270。The optical blocking layer 260 of the second embodiment of the invention may include a first wall 261, a second wall 263, a third wall 264 and an upper cover 262. The first wall 261 , the second wall 263 and the third wall 264 are respectively inserted into the base plate 210 and fixedly connected to the base plate 210 . The first wall 261 is used to block the light emitted by the light-emitting chip 220 from being directly lateral to the circuit board 230 . The light detector 235 receives. The second wall 263 and the third wall 264 are respectively provided on two opposite sides of the substrate 210, that is, they are provided on two opposite sides of the first wall 261, so as to prevent the circuit board 230 and the light-emitting chip 220 from being affected by the semiconductor. Interference from other parts on the device other than the structure 200, such as crosstalk interference that may be caused by other electronic parts. The upper cover 262 is fixedly connected to the first wall 261, the second wall 263 and the third wall 264, from the second wall 263 to the third wall in a direction perpendicular to the upright direction of the first wall 261, the second wall 263 and the third wall 264. The three walls 264 extend and entirely cover the upper surfaces of the first light-transmissive layer 240 and the second light-transmissible layer 250 . The upper cover 262 is provided with a light emitting hole 280 and a light receiving hole 270 .
圖5A至圖5F顯示根據本創作第一實施例之半導體結構的製程示意圖。在圖5A顯示的晶片黏結(Die Attach)製程中,藉由黏膠122、131分別將發光晶片120及電路板130黏結在基板110的安裝表面112上且在安裝表面112上另設置有電極113、114。在圖5B顯示的線連結(Wire Bonding)製程中,將第一連接線121和第二連接線132分別將發光晶片120和電路板130電性連接至電極114和電極113。在圖5C顯示的模製(Molding)製程中,將可透光層190模製在基板110上,以封圍並完全覆蓋基板110上的電路板130和發光晶片120。在圖5D顯示的預切割(Pre-saw)製程中,將可透光層190切割成第一可透光層140及第二可透光層150,其中第一可透光層140上形成有第一凸台141,而第二可透光層150上形成有第二凸台151。此外,在第一可透光層140和第二可透光層150之間形成有切割至基板110中的第一凹部111。在圖5E顯示的分配(Dispensing)製程中,光學阻擋層160注入第一凹部111以及環繞第一凸台141、第二凸台151之第一可透光層140和第二可透光層150界定的空間,使光學阻擋層160形成壁161和上蓋162在該空間中且上蓋162的上表面和第一凸台141和第二凸台151的上表面齊平。藉此,第一可透光層140透過第一凸台141在上蓋162中形成收光孔170,而第二可透光層150透過第二凸台151在上蓋162中形成發光孔180。最後,在圖5F顯示的封裝切割(PKG-saw)後的俯視圖,可自發光孔180看到藉由黏膠122黏著在基板110上的發光晶片120以及自收光孔170看到電路板130上的撿光器135。5A to 5F show schematic process diagrams of a semiconductor structure according to the first embodiment of the present invention. In the die attach process shown in FIG. 5A , the light-emitting chip 120 and the circuit board 130 are bonded to the mounting surface 112 of the substrate 110 through adhesives 122 and 131 respectively, and an electrode 113 is provided on the mounting surface 112 . ,114. In the wire bonding process shown in FIG. 5B , the first connection wire 121 and the second connection wire 132 electrically connect the light-emitting chip 120 and the circuit board 130 to the electrode 114 and the electrode 113 respectively. In the molding process shown in FIG. 5C , the light-transmissive layer 190 is molded on the substrate 110 to enclose and completely cover the circuit board 130 and the light-emitting chip 120 on the substrate 110 . In the pre-saw process shown in FIG. 5D , the light-transmissive layer 190 is cut into a first light-transmissive layer 140 and a second light-transmissible layer 150 , where a first light-transmissive layer 140 is formed with The first boss 141 is formed on the second light-transmissive layer 150 . In addition, a first recess 111 cut into the substrate 110 is formed between the first light-transmissive layer 140 and the second light-transmissible layer 150 . In the dispensing process shown in FIG. 5E , the optical blocking layer 160 is injected into the first recess 111 and the first light-transmissive layer 140 and the second light-transmissible layer 150 surrounding the first boss 141 and the second boss 151 The defined space is such that the optical blocking layer 160 forms the wall 161 and the upper cover 162 in the space, and the upper surface of the upper cover 162 is flush with the upper surfaces of the first boss 141 and the second boss 151 . Thereby, the first light-transmissive layer 140 forms a light-receiving hole 170 in the upper cover 162 through the first boss 141 , and the second light-transmissible layer 150 forms a light-emitting hole 180 in the upper cover 162 through the second boss 151 . Finally, in the top view of the package after cutting (PKG-saw) shown in FIG. 5F , the light-emitting chip 120 adhered to the substrate 110 by the adhesive 122 can be seen from the light-emitting hole 180 and the circuit board 130 can be seen from the light-receiving hole 170 The light picker 135 on.
圖6A至圖6G顯示根據本創作第二實施例之半導體結構的製程示意圖。圖6A顯示的晶片黏結(Die Attach)製程、圖6B顯示的線連結(Wire Bonding)製程、圖6C顯示的模製(Molding)製程和圖6G顯示的封裝切割(PKG-saw)分別與上述圖5A至圖5C和圖5F相同,在此為了簡潔的緣故省略不再贅述。在圖6D顯示的預切割(Pre-saw)製程中,將可透光層290切割成第一可透光層240及第二可透光層250,其中第一可透光層240上形成有第一凸台241,而第二可透光層250上形成有第二凸台251。此外,在第一可透光層240和第二可透光層250之間形成有切割至基板210中的第一凹部211;且在第一可透光層240靠近外側邊緣處形成有切割至基板210中的第二凹部212以及在第二可透光層250靠近外側邊緣處形成有切割至基板210中的第三凹部213。在圖6E顯示的分配(Dispensing)製程中,光學阻擋層260注入第一凹部211、第二凹部212、第三凹部213以及環繞第一凸台241、第二凸台251之第一可透光層240和第二可透光層250界定的空間,使光學阻擋層260形成第一壁261、第二壁263、第三壁264以及連接第一壁261、第二壁263、第三壁264之上蓋262在該空間中,上蓋262的上表面和第一凸台241和第二凸台251的上表面齊平。藉此,第一可透光層240透過第一凸台241在上蓋262中形成收光孔270,而第二可透光層250透過第二凸台251在上蓋262中形成進光孔280。最後,在圖6G的俯視圖,可自發光孔280看到藉由黏膠222黏著在基板210上的發光晶片220以及自收光孔270看到電路板230上的撿光器235。6A to 6G show schematic process diagrams of a semiconductor structure according to a second embodiment of the present invention. The die attachment (Die Attach) process shown in Figure 6A, the wire bonding (Wire Bonding) process shown in Figure 6B, the molding (Molding) process shown in Figure 6C and the package cutting (PKG-saw) shown in Figure 6G are respectively different from the above figures. 5A to 5C are the same as FIG. 5F and will not be described again for the sake of simplicity. In the pre-saw process shown in FIG. 6D , the light-transmissive layer 290 is cut into a first light-transmissive layer 240 and a second light-transmissible layer 250 , where a first light-transmissive layer 240 is formed with The first boss 241 is formed on the second light-transmissive layer 250 . In addition, a first recess 211 cut into the substrate 210 is formed between the first light-transmissible layer 240 and the second light-transmissible layer 250; and a cut-to-cut groove is formed near the outer edge of the first light-transmissible layer 240. The second recess 212 in the substrate 210 and the third recess 213 cut into the substrate 210 are formed near the outer edge of the second light-transmissible layer 250 . In the dispensing process shown in FIG. 6E , the optical blocking layer 260 is injected into the first concave portion 211 , the second concave portion 212 , the third concave portion 213 and the first light-transmissive portion surrounding the first boss 241 and the second boss 251 . The space defined by the layer 240 and the second light-transmissive layer 250 allows the optical blocking layer 260 to form the first wall 261, the second wall 263, and the third wall 264 and connect the first wall 261, the second wall 263, and the third wall 264. The upper cover 262 is in this space, and the upper surface of the upper cover 262 is flush with the upper surfaces of the first boss 241 and the second boss 251 . Thereby, the first light-transmissive layer 240 forms a light-receiving hole 270 in the upper cover 262 through the first boss 241 , and the second light-transmissible layer 250 forms a light-inlet hole 280 in the upper cover 262 through the second boss 251 . Finally, in the top view of FIG. 6G , the light-emitting chip 220 adhered to the substrate 210 by the adhesive 222 can be seen from the light-emitting hole 280 and the light picker 235 on the circuit board 230 can be seen from the light-collecting hole 270 .
圖6F顯示從圖6E之沿著6F-6F的剖面線擷取的端視圖,光學阻擋層260封圍且覆蓋被第一透光層240封圍在基板210上的電路板230。類似地,光學阻擋層260封圍且覆蓋被第二透光層250封圍在基板210上的發光晶片220。FIG. 6F shows an end view taken along the section line 6F-6F of FIG. 6E , with the optical blocking layer 260 enclosing and covering the circuit board 230 enclosed by the first light-transmitting layer 240 on the substrate 210 . Similarly, the optical blocking layer 260 encloses and covers the light-emitting wafer 220 enclosed by the second light-transmitting layer 250 on the substrate 210 .
圖7A至圖7J顯示根據本創作第一實施例之半導體結構的另一製程示意圖。圖7A顯示的晶片黏結(Die Attach)製程、圖7B顯示的線連結(Wire Bonding)製程和圖7C顯示的模製(Molding)製程分別與上述圖5A至圖5C相同,在此為了簡潔的緣故省略不再贅述。在圖7D顯示的第一預切割(Pre-saw)製程中,將可透光層190切割成第一可透光層140及第二可透光層150,其中,在第一可透光層140和第二可透光層150之間形成有切割至基板110中的第一凹部111,且第一凹部111與第一可透光層140和第二可透光層150的上表面處分別形成兩個階梯部分。在圖7E顯示的第一分配(Dispensing)製程中,光學阻擋層160注入並填滿第一凹部111形成剖面為T字型的壁,光學阻擋層160的上表面與第一可透光層140和第二可透光層150的上表面齊平。在圖7F顯示的第二預切割(Pre-saw)製程中,進行第二次的預切割,在第一可透光層140、第二可透光層150和光學阻擋層160共同形成的上表面切割出溝槽並在第一可透光層140、第二可透光層150上分別形成第一凸台141和第二凸台151。在圖7G顯示的第二分配(Dispensing)製程中,以點膠的方式將光學阻擋材料注入該溝槽內形成附加光學阻擋層160’ ,且如圖7I的俯視圖所示形成覆蓋光學阻擋層160的附加光學阻擋層160’。在圖7H顯示的封裝切割(PKG-saw)製程中,將附加光學阻擋層160’進行切割,使其上表面變為平整,且切割後的光學阻擋層160’與第一凸台141和第二凸台151在高度上存在一段段差。第一凸台141在附加光學阻擋層160’之間形成收光孔170,而第二凸台151在附加光學阻擋層160’之間形成發光孔180。在此製程實施例中,可在基板110上設置多於一個的撿光器及發光晶片。例如,如圖7I中完成封裝切割製程後的俯視圖所示,可自發光孔180看到兩個發光晶片120、120’以及自收光孔170看到電路板130上的兩個撿光器(第一撿光器133、第二撿光器134)。7A to 7J show another process diagram of a semiconductor structure according to the first embodiment of the present invention. The die attachment (Die Attach) process shown in Figure 7A, the wire bonding (Wire Bonding) process shown in Figure 7B, and the molding (Molding) process shown in Figure 7C are respectively the same as the above-mentioned Figures 5A to 5C, and are here for the sake of simplicity. No further description will be omitted. In the first pre-saw process shown in FIG. 7D , the light-transmissive layer 190 is cut into a first light-transmissive layer 140 and a second light-transmissible layer 150 , where in the first light-transmissive layer A first recess 111 cut into the substrate 110 is formed between 140 and the second light-transmissive layer 150, and the first recess 111 is connected to the upper surfaces of the first light-transmissive layer 140 and the second light-transmissible layer 150 respectively. Two stepped sections are formed. In the first dispensing process shown in FIG. 7E , the optical blocking layer 160 is injected into and fills the first recess 111 to form a T-shaped wall with a cross-section. The upper surface of the optical blocking layer 160 is in contact with the first light-transmissive layer 140 It is flush with the upper surface of the second light-transmissive layer 150 . In the second pre-saw process shown in FIG. 7F , a second pre-saw is performed, and the first light-transmissive layer 140 , the second light-transmissible layer 150 and the optical blocking layer 160 are jointly formed. Grooves are cut on the surface, and first bosses 141 and second bosses 151 are respectively formed on the first light-transmissive layer 140 and the second light-transmissible layer 150 . In the second dispensing process shown in Figure 7G, optical blocking material is injected into the trench by dispensing to form an additional optical blocking layer 160', and a covering optical blocking layer 160 is formed as shown in the top view of Figure 7I additional optical blocking layer 160'. In the package cutting (PKG-saw) process shown in FIG. 7H, the additional optical barrier layer 160' is cut so that its upper surface becomes flat, and the cut optical barrier layer 160' is in contact with the first boss 141 and the first boss 141. There is a certain height difference between the two bosses 151 . The first boss 141 forms the light-receiving hole 170 between the additional optical blocking layers 160', and the second boss 151 forms the light-emitting hole 180 between the additional optical blocking layers 160'. In this process embodiment, more than one photodetector and light-emitting chip can be disposed on the substrate 110 . For example, as shown in the top view after completing the package cutting process in FIG. 7I , two light-emitting wafers 120 and 120' can be seen from the light-emitting hole 180 and two light pickers on the circuit board 130 can be seen from the light-receiving hole 170 ( first light picker 133, second light picker 134).
圖7J顯示從圖7I之沿著7J-7J的剖面線擷取的端視圖,附加光學阻擋層160’覆蓋在第一透光層140封圍在基板110上的電路板130。類似地,光學阻擋層160’覆蓋被第二透光層150封圍在基板110上的發光晶片120、120’。7J shows an end view taken along the section line 7J-7J from FIG. 7I, with the additional optical blocking layer 160' covering the circuit board 130 with the first light-transmitting layer 140 surrounding the substrate 110. Similarly, the optical blocking layer 160' covers the light-emitting wafers 120, 120' enclosed by the second light-transmitting layer 150 on the substrate 110.
以上所揭示的內容僅為本創作的較佳可行實施例之一,並非因此侷限本創作的申請專利範圍,凡運用本創作說明書及圖式內容所做的等效技術變化,均包含於本創作的申請專利範圍內。The content disclosed above is only one of the best possible embodiments of this invention, and does not limit the patentable scope of this invention. All equivalent technical changes made by using the description and drawings of this invention are included in this invention. within the scope of the patent application.
100、200:半導體結構 110、210:基板 111、211:第一凹部 212:第二凹部 213:第三凹部 112、214:安裝表面 113、114、215、216:電極 120、120’、220:發光晶片 121、221:第一連接線 130、230:電路板 131、122、222、231:黏膠 132、232:第二連接線 133:第一撿光器 134:第二撿光器 135、235:撿光器 140、240:第一可透光層 141、241:第一凸台 150、250:第二可透光層 151、251:第二凸台 160、260:光學阻擋層 160’:附加光學阻擋層 161:壁 261:第一壁 263:第二壁 264:第三壁 162、262:上蓋 170、270:收光孔 180、280:發光孔 190:可透光層 B:光學阻擋層 D1~D3:寬度 I:入射光路徑 O:物件 R:反射光路徑 R1:第一反射光路徑 R2:第二反射光路徑 S:基板 Z0:入射光區域 Z1:第一反射光區域 Z2:第二反射光區域100, 200: Semiconductor structure 110, 210: Substrate 111, 211: first concave part 212:Second recess 213: The third concave part 112, 214: Installation surface 113, 114, 215, 216: Electrode 120, 120’, 220: Luminous chip 121, 221: first connection line 130, 230: Circuit board 131, 122, 222, 231: Viscose 132, 232: Second connection line 133:The first light picker 134: Second light picker 135, 235: Light picker 140, 240: first light-transmissive layer 141, 241: The first boss 150, 250: Second light-transmissive layer 151, 251: Second boss 160, 260: Optical barrier layer 160’: Additional optical blocking layer 161: wall 261:First wall 263:Second wall 264:Third wall 162, 262: Upper cover 170, 270: Light receiving hole 180, 280: Luminous hole 190: Translucent layer B: Optical barrier layer D1~D3: Width I: incident light path O:Object R: Reflected light path R1: first reflected light path R2: second reflected light path S:Substrate Z0: incident light area Z1: first reflected light area Z2: The second reflected light area
圖1顯示先前技術之半導體結構的側剖面端視及光路徑示意圖。FIG. 1 shows a side cross-sectional end view and a schematic light path diagram of a semiconductor structure in the prior art.
圖2A顯示根據本創作第一實施例之半導體結構的側剖面端視圖。FIG. 2A shows a side cross-sectional end view of a semiconductor structure according to a first embodiment of the present invention.
圖2B顯示根據本創作第一實施例之半導體結構的俯視圖。FIG. 2B shows a top view of a semiconductor structure according to the first embodiment of the present invention.
圖3顯示根據本創作第一實施例之半導體結構的側剖面端視及光路徑示意圖。FIG. 3 shows a side cross-sectional end view and a schematic light path diagram of the semiconductor structure according to the first embodiment of the present invention.
圖4顯示根據本創作第二實施例之半導體結構的側剖面端視圖。FIG. 4 shows a side cross-sectional end view of a semiconductor structure according to a second embodiment of the present invention.
圖5A至圖5F顯示根據本創作第一實施例之半導體結構的製程示意圖。5A to 5F show schematic process diagrams of a semiconductor structure according to the first embodiment of the present invention.
圖6A至圖6G顯示根據本創作第二實施例之半導體結構的製程示意圖。6A to 6G show schematic process diagrams of a semiconductor structure according to a second embodiment of the present invention.
圖7A至圖7J顯示根據本創作第一實施例之半導體結構的另一製程示意圖。7A to 7J show another process diagram of a semiconductor structure according to the first embodiment of the present invention.
100:半導體結構 100:Semiconductor Structure
110:基板 110:Substrate
112:安裝表面 112:Installation surface
113、114:電極 113, 114: Electrode
120:發光晶片 120:Light-emitting chip
121:第一連接線 121: First connection line
130:電路板 130:Circuit board
131:黏膠 131:Viscose
132:第二連接線 132: Second connection line
140:第一可透光層 140: First light-transmissive layer
150:第二可透光層 150: Second light-transmissive layer
160:光學阻擋層 160: Optical barrier layer
161:壁 161: wall
162:上蓋 162: Upper cover
170:收光孔 170: Light receiving hole
180:發光孔 180: Luminous hole
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW112202682U TWM645270U (en) | 2023-03-24 | 2023-03-24 | Semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWM645270U (en) |
-
2023
- 2023-03-24 TW TW112202682U patent/TWM645270U/en unknown
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