TWM531653U - Field effect transistor with multiple width electrode structure - Google Patents

Description

Field effect transistor with multiple width electrode structure

The present invention relates to a field effect transistor having a multi-width electrode structure, and more particularly to a field effect transistor including an electrode portion having multiple widths.

With the development of technology and the advancement of the times, advances in semiconductor process technology have led to the development of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs, hereinafter referred to as MOSFETs).

Among them, the existing semiconductor process uses various methods to form a MOSFET. Generally speaking, an epitaxial layer is generally formed on a semiconductor substrate, a trench is formed on the epitaxial layer, and a step is formed in the trench as a power. The gate of the crystal.

However, in the MOSFETs fabricated by the conventional method of forming the above-mentioned gates, there is generally a problem of high total gate charge (Qg) and high actual performance index (Figure of Merit; FOM), wherein the total gate charge refers to When the MOSFET is fully turned on, the charge required by the gate, the total gate charge is related to the startup speed of the MOSFET. The high total gate charge reduces the switching speed and increases the gate loss, thereby increasing the switching loss and reducing the efficiency; Performance index is based on on-resistance and total gate It is determined by the load (Qg multiplied by Rdson), and the high actual performance index indicates that the conduction loss and the switching loss are poor.

Therefore, in the process of manufacturing a MOSFET and forming a trench, how to reduce the total gate charge and the actual performance index has become an improvement target of the prior art.

In view of the structure of the existing MOSFET and its manufacturing process, there is generally a problem of high total gate charge and high practical performance index. Therefore, this creation mainly provides a field effect transistor with multiple width electrode structure, which mainly makes the electrode structure exhibit multiple widths and different heights, so as to reduce the total gate charge and the actual performance index.

Based on the above objectives, the main technical means adopted by the present invention is to provide a field effect transistor having a multi-width electrode structure, comprising a semiconductor substrate, an epitaxial layer, an oxide layer, a first electrode portion, and a width grading portion. a second electrode portion, a gate oxide layer, a gate portion, a body region, a source region, an interlayer dielectric layer, and a source electrode. The epitaxial layer is formed on the semiconductor substrate and has at least one trench extending in a vertical direction, the trench having a trench sidewall and a trench bottom. The oxide layer is formed on the sidewall of the trench and the bottom of the trench, and has a first tapered structure that gradually recesses from the periphery toward the center of the trench. The first electrode portion is adjacent to the bottom of the trench, and is separated from the epitaxial layer by the oxide layer, and has a first height and a first width respectively in a vertical direction and a horizontal direction perpendicular to the vertical direction. The width grading portion fills the first tapered structure from the first electrode The portion extends away from the bottom of the trench and is separated from the epitaxial layer by an oxide layer. The second electrode portion extends from the width grading portion toward the bottom of the trench in the trench, and is separated from the epitaxial layer by the oxide layer, and has a second height and a second width in the vertical direction and the horizontal direction, respectively. A gate oxide layer is formed on the trench sidewall, the oxide layer and the second electrode portion, and is located in the trench. The gate portion is formed on the gate oxide layer, and is separated from the second electrode portion by the gate oxide layer and has a third width in the horizontal direction. The body region is disposed on the epitaxial layer and adjacent to the gate portion, and is separated from the gate portion by the gate oxide layer. The source region is disposed on the body region and is spaced apart from the gate portion by the gate oxide layer. The interlayer dielectric layer covers the source region and the gate portion. The source electrode covers the body region and the interlayer dielectric layer and is in contact with the source region. Wherein the first height is greater than or equal to the second height, the first width is smaller than the second width, and the second width is smaller than the third width.

Based on the above-mentioned necessary technical means, the field effect transistor having the multi-width electrode structure further includes the following preferred technical means. The oxide layer has a second divergent structure gradually recessed from the periphery toward the second electrode portion adjacent to the second electrode portion, and the gate oxide layer fills the second diffractive structure.

After adopting the main technical means of the field effect transistor having the multi-width electrode structure provided by the present invention, since the gate structure exhibits multiple widths and different heights, the first width of the first electrode portion is smaller than that of the second electrode portion. The second width, the second width of the second electrode portion is smaller than the third width of the gate portion, and the second height of the second electrode portion is less than or equal to the first height of the first electrode portion, thereby effectively reducing the total gate charge and Actual performance index.

The specific embodiments used in the present application will be further illustrated by the following examples and drawings.

1‧‧‧Field effect transistor with multiple width electrode structure

11‧‧‧Semiconductor substrate

12‧‧‧ epitaxial layer

121‧‧‧ trench

1211‧‧‧ trench sidewall

1212‧‧‧Bottom of the trench

13‧‧‧Oxide layer

131‧‧‧First concave structure

132‧‧‧Second tapered structure

14‧‧‧First electrode section

15‧‧‧Width gradient

16‧‧‧Second electrode section

17‧‧‧ gate oxide layer

18‧‧‧Bridge

19‧‧‧ Body area

20‧‧‧ source area

21‧‧‧Interlayer dielectric layer

22‧‧‧Source electrode

2‧‧‧hard mask

3‧‧‧ photoresist layer

4‧‧‧Consumable sacrificial oxide layer

5‧‧‧First polycrystalline layer

51‧‧‧First electrode polysilicon layer

61‧‧‧Second electrode polysilicon layer

7‧‧‧ third polysilicon layer

8‧‧‧ mask layer

100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400‧‧‧ waveforms

L1‧‧‧Vertical direction

L2‧‧‧ horizontal direction

W1‧‧‧ first width

W2‧‧‧ second width

W3‧‧‧ third width

H1‧‧‧ first height

H2‧‧‧second height

WH1, WH2, WH3‧‧‧ vacant area width

The first diagram and the first A diagram show a schematic flow chart of a method for manufacturing a field effect transistor having a multi-width electrode structure according to a preferred embodiment of the present invention.

The second figure shows a cross-sectional view of a semiconductor substrate and an epitaxial layer of the preferred embodiment of the present invention.

The third figure shows a cross-sectional view of the trench etched in the epitaxial layer of the preferred embodiment of the present invention.

The fourth figure shows a cross-sectional view of the consumable sacrificial oxide layer formed in the trench of the preferred embodiment of the present invention.

Figure 5 is a cross-sectional view showing the formation of an oxide layer in the preferred embodiment of the present invention.

The sixth drawing shows a cross-sectional view of the first polysilicon layer of the preferred embodiment of the present invention formed on the oxide layer.

Figure 7 is a cross-sectional view showing the etching of the first polysilicon layer to form the first electrode polysilicon layer in the preferred embodiment of the present invention.

Figure 8 is a cross-sectional view showing the etching of the second polysilicon layer to form the second electrode polysilicon layer in the preferred embodiment of the present invention.

Figure 9 is a cross-sectional view showing the formation of a third polysilicon layer on the gate oxide layer in the preferred embodiment of the present invention.

Figure 10 is a cross-sectional view showing the formation of an interlayer dielectric layer in the preferred embodiment of the present invention. Figure.

Figure 11 is a cross-sectional view showing the body region and the source region of the etched portion of the etched portion of the preferred embodiment of the present invention.

Figure 12 is a cross-sectional view showing a field effect transistor having a multi-width electrode structure in accordance with a preferred embodiment of the present invention.

The thirteenth diagram shows a schematic diagram of the simulated structure of the prior art field effect transistor.

Fig. 14 is a schematic view showing the simulation structure of a field effect transistor having a multi-width electrode structure according to another embodiment of the present invention.

The fifteenth diagram is a schematic view showing the simulation structure of the field effect transistor having the multi-width electrode structure of the preferred embodiment of the present invention.

Figure 16 shows a waveform diagram of the input capacitance of this creation and prior art.

The seventeenth figure shows a waveform diagram of the output capacitance of the present and prior art.

The eighteenth figure shows a waveform diagram of the reverse conversion capacitance of the present invention and the prior art.

The nineteenth figure is a schematic diagram showing the waveform of the total gate charge of this creation and the prior art.

In the field effect transistor having a multi-width electrode structure provided by the present invention, the combined implementation manners are numerous, and therefore will not be further described herein, and only a preferred embodiment will be specifically described.

Please refer to the first to the twelfth drawings. The first diagram and the first A diagram show the flow chart of the manufacturing method of the field effect transistor having the multi-width electrode structure of the preferred embodiment of the present invention. The second figure shows a cross-sectional view of a semiconductor substrate and an epitaxial layer of the preferred embodiment of the present invention. The third figure shows a cross-sectional view of the trench etched in the epitaxial layer of the preferred embodiment of the present invention. The fourth figure shows a cross-sectional view of the consumable sacrificial oxide layer formed in the trench of the preferred embodiment of the present invention. Figure 5 is a cross-sectional view showing the formation of an oxide layer in the preferred embodiment of the present invention. The sixth drawing shows a cross-sectional view of the first polysilicon layer of the preferred embodiment of the present invention formed on the oxide layer.

Figure 7 is a cross-sectional view showing the etching of the first polysilicon layer to form the first electrode polysilicon layer in the preferred embodiment of the present invention. Figure 8 is a cross-sectional view showing the etching of the second polysilicon layer to form the second electrode polysilicon layer in the preferred embodiment of the present invention. Figure 9 is a cross-sectional view showing the formation of a third polysilicon layer on the gate oxide layer in the preferred embodiment of the present invention. Figure 10 is a cross-sectional view showing the formation of an interlayer dielectric layer in the preferred embodiment of the present invention. Figure 11 is a cross-sectional view showing the body region and the source region of the etched portion of the etched portion of the preferred embodiment of the present invention. Figure 12 is a cross-sectional view showing a field effect transistor having a multi-width electrode structure in accordance with a preferred embodiment of the present invention.

As shown in the figure, in the steps of the method for fabricating the field effect transistor having the multi-width electrode structure of the preferred embodiment, as shown in the second figure, the step S101 is first performed to provide a semiconductor substrate 11 and in the semiconductor. An epitaxial layer 12 is formed on the substrate 11 (the formation is in the prior art, and the portion referred to as "forming" hereinafter will not be described again). Wherein, the semiconductor substrate 11 is generally doped with an ion concentration (for example, an N type), The epitaxial layer 12 is also generally doped with an ion concentration (for example, N-type), and the ion concentration of the epitaxial layer 12 is lower than that of the semiconductor substrate 11, which is a prior art and will not be described again.

After the step S101 is performed, the step S102 is performed to etch at least one trench 121 (only one is shown) extending in a vertical direction L1. The trench 121 has a trench sidewall 1211 and a trench. The bottom portion 1212 of the trench, and in the etching method, as shown in the third figure, the hard mask 2 is formed on the epitaxial layer 12 (the material is prior art, will not be described again), and then on the hard mask 2 The photoresist layer 3 is formed (for the prior art, will not be described again) and then the trenches 121 are etched (what etching is used in the prior art, and the portion referred to hereinafter as "etching" will not repeat which etching is used). In addition, it should be noted that the sidewall 1211 of the preferred embodiment of the present invention refers to the sidewall of the entire trench 121, that is, if the above view is taken, the sidewall is integrated, instead of The perspective view of the section view has two side walls, which are hereby clarified.

As shown in the fourth figure, step S103 is followed to form a consumable sacrificial oxide layer 4 on the surface of the epitaxial layer 12, the trench sidewalls 1211 of the trench 121, and the trench bottom portion 1212. Then, step S104 is performed to completely etch the consumable sacrificial oxide layer 4. The steps S103 and S104 are used to improve the regularity of the crystal lattice arrangement on the surface of the epitaxial layer 12, the trench sidewalls 1211, and the trench bottom portion 1212 to increase the flatness. In other embodiments, Steps S103 and S104 may not be employed.

As shown in the fifth and sixth figures, step S105 is performed on the surface of the epitaxial layer 12, the trench sidewalls 1211 of the trench 121, and the trenches. The bottom portion 1212 of the trench forms an oxide layer 13, and a first polysilicon layer 5 is formed on the oxide layer 13 to have an approximately T-shaped structure.

As shown in the seventh figure, step S106 is followed to etch a portion of the first polysilicon layer 5, so that the remaining first polysilicon layer 5 forms a first electrode polysilicon layer 51 in the trench 121, and then steps are performed. S107 etches an oxide layer 13 adjacent to the portion of the first electrode polysilicon layer 51 and the trench sidewall 1211, such that the oxide layer 13 has a self-peripheral toward the first electrode polysilicon layer 51 adjacent to the first electrode polysilicon layer 51 (or The first tapered structure 131 is gradually recessed toward the center of the trench 121. Specifically, the width of the first tapered structure 131 is gradually decreased downward along the vertical direction L1. In the preferred embodiment, the first tapered structure 131 is adjacent to the upper half of the first electrode polysilicon layer 51; The thickness of the oxide layer 13 located above and adjacent to the trench sidewall 1211 and the surface of the epitaxial layer 12 also becomes thinner, and the thickness of the oxide layer 13 located adjacent to the trench bottom 1212 is thicker.

As shown in the eighth embodiment, a second polysilicon layer is formed on the first electrode polysilicon layer 51 (step is not shown, specifically showing a T-shaped structure similar to the first polysilicon layer 5). And the second polysilicon layer fills the first tapered structure 131.

Then, step S109 is performed to etch a portion of the second polysilicon layer, such that the remaining second polysilicon layer forms a second electrode polysilicon layer 61 in the trench 121, and the first electrode polysilicon layer 51 and the second electrode are formed. The polysilicon layer 61 forms a first electrode portion 14, a width grading portion 15, and a second electrode portion 16.

Wherein the width grading portion 15 is located in the first tapered structure 131, and is separated from the epitaxial layer 12 by the oxide layer 13. The first electrode portion 14 extends from the width grading portion 15 toward the groove bottom portion 1212 and is spaced apart from the epitaxial layer 12 by the oxide layer 13. The second electrode portion 16 extends from the width grading portion 15 away from the groove bottom portion 1212 and is spaced apart from the epitaxial layer 12 by the oxide layer 13.

The first electrode portion 14 has a first height H1 and a first width W1 in the vertical direction L1 and a horizontal direction L2 perpendicular to the vertical direction L1, and the second electrode portion 16 has one in the vertical direction L1 and the horizontal direction L2, respectively. The second height H2 is a second width W2. The first height H1 is greater than or equal to the second height H2, and the first width W1 is smaller than the second width W2.

As shown in the eighth figure, step S110 is followed to etch the oxide layer 13 adjacent to the upper side of the second electrode portion 16 and the trench sidewall 1211, so that the surface of the epitaxial layer 12 and the trench sidewall 1211 are exposed and the oxide layer is exposed. 13 adjacent to the second electrode portion 16 has a second divergent structure 132 gradually recessed from the periphery toward the second electrode portion 16. Similarly, the width above the second divergent structure 132 gradually decreases downward along the vertical direction L1. In the preferred embodiment of the present invention, the second divergent structure 132 is adjacent to the upper half of the second electrode portion 16. Further, the first electrode portion 14 and the second electrode portion 16 may be a source electrode portion or a gate electrode portion, depending on the practical design.

As shown in the ninth and tenth diagrams, step S111 is followed to form a gate oxide layer 17 on the second electrode portion 16 and the trench sidewall 1211, and the gate oxide layer 17 fills the second tapered structure 132. . In addition, in step S111, a third polysilicon layer 7 is formed on the gate oxide layer 17, and a portion of the third polysilicon layer 7 is etched, so that the remaining third polysilicon layer 7 is in the trench 121. A gate portion 18 is formed therein to form a gate portion 18 on the gate oxide layer 17.

Further, the gate portion 18 is spaced apart from the second electrode portion 16 by the gate oxide layer 17, and has a third width W3 in the horizontal direction L2, and the third width W3 is larger than the second width W2.

As shown in the tenth figure, step S112 is followed to sequentially form a body region 19 (P-body) and a source region 20 (N+) adjacent to the gate portion 18 of the epitaxial layer 12, and the manner of formation is not Let me repeat. The body region 19 is spaced apart from the gate portion 18 by the gate oxide layer 17, and the source region 20 is spaced apart from the gate portion 18 by the gate oxide layer 17.

As shown in the tenth and eleventh figures. Then, step S113 is performed to form an interlayer dielectric (ILD) 21 covering the source region 20 and the gate portion 18, and then a mask layer 8 is formed on the interlayer dielectric layer 21, and a portion is formed. After the body region 19 and the source region 20 are etched, the mask layer 8 is removed.

As shown in FIG. 12, the final step S114 is performed to form a source electrode 19 covering the body region 19 and the interlayer dielectric layer 21 and contacting the source region 20, thereby fabricating the preferred embodiment of the present invention. The field effect transistor 1 of a multi-width electrode structure in which the source electrode 22 exhibits an approximately U-shaped structure.

Please refer to FIG. 13 to FIG. 15 together. FIG. 13 is a schematic diagram showing the simulation structure of the prior art field effect transistor, and FIG. 14 is a view showing another embodiment of the present invention having a multi-width electrode structure. Schematic diagram of the analog structure of the field effect transistor. The fifteenth diagram is a schematic view showing the simulation structure of the field effect transistor having the multi-width electrode structure of the preferred embodiment of the present invention.

As shown in the figure, after the DC simulation of the structure of the thirteenth to fifteenth drawings is actually performed by the software, the following table values can be obtained:

It can be seen from the above that, regardless of whether the actual performance index and the total gate charge of the structure using the fourteenth or fifteenth figure are lower than the actual performance index and the total gate charge of the prior art, the use of the present invention is adopted. After the structure, the total gate charge and the actual performance index can be effectively reduced.

In addition, as can be seen from the figure, the width WH1 of the depletion region is approximately equal to the width WH2 of the depletion region, and the width WH3 of the depletion region is greater than the width WH2 of the depletion region. Therefore, if the ratio between the second height H2 and the first height H1 is larger, the depletion is insufficient. The wider the width of the region, the smaller the depletion capacitance (C _dep ) can be achieved under the same threshold voltage (V _D ). The above-described depletion region widths WH1, WH2, and WH3 refer to lengths in the vertical direction L1 indicated by WH1, WH2, and WH3, respectively.

It is worth mentioning that the capacitance C _{gd is} generally affected by the above-mentioned depletion capacitance C _dep and the oxide layer capacitance C _OX . The input capacitance (C _ISS ) is the sum of the capacitance C _gs and the capacitance C _gd , and the output capacitance (C _OSS ) capacitance The sum of C _ds and the capacitance C _gd , the reverse conversion capacitance ( C _RSS ) is the same as the capacitance C _gd .

Please refer to the sixteenth figure. The sixteenth figure shows the waveform diagram of the input capacitance (C _ISS ) of this creation and the prior art. As shown in the figure, the sixteenth embodiment performs the AC simulation with the structures of the thirteenth to fifteenth drawings, wherein the waveform 100 represents the waveform of the structure of the thirteenth diagram, and the waveform 200 represents the fourteenth and tenth The waveform of the structure of the five figures (since the waveforms are similar, so only shown by the waveform 200), it can be seen from the waveforms 100 and 200 that the comparison of the input capacitance with the threshold voltage V _D = 50 V can be used in this creation. The input capacitance of the structure is significantly smaller than that of the prior art.

Please refer to the seventeenth figure, which shows a waveform diagram of the output capacitance (C _OSS ) of the present invention and the prior art. As shown in the figure, the seventeenth embodiment performs an alternating current (AC) simulation with the structures of the thirteenth to fifteenth drawings, wherein the waveform 300 represents the waveform of the structure of the thirteenth diagram, and the waveform 400 represents the fourteenth diagram. The waveform of the structure, the waveform 500 represents the waveform of the structure of the fifteenth figure. It can be known from the waveforms 300, 400 and 500 that the output capacitance is compared with the threshold voltage V _D = 50 V, and the structure used in the creation can be known. The output capacitance is significantly smaller than that of the prior art, and particularly in the case where the first height H1 is equal to the second height H2, the output capacitance is significantly reduced.

Please refer to the eighteenth figure. The eighteenth figure shows the waveform diagram of the reverse conversion capacitor (C _RSS ) of this creation and the prior art. As shown in the figure, the eighteenth diagram is an AC simulation using the structures of the thirteenth to fifteenth diagrams, wherein the waveform 600 represents the waveform of the structure of the thirteenth diagram, and the waveform 700 represents the structure of the fourteenth diagram. Waveform, waveform 800 represents the waveform of the structure of the fifteenth figure. It can be seen from waveforms 600, 700 and 800 that the reverse conversion capacitance is compared with the back-conversion capacitor with a threshold of V _D = 50 V, and the reverse conversion capacitance of the structure used in the present creation can be known. Both are significantly smaller than the prior art structure, particularly in the case where the first height H1 is equal to the second height H2, the reverse conversion capacitance is significantly reduced.

Please refer to the nineteenth figure. The nineteenth figure shows the waveform diagram of the total gate charge of this creation and the prior art. As shown, after AC simulation, waveforms 900 and 1200 represent the waveform of the structure of the thirteenth diagram, waveforms 1000 and 1300 represent the waveform of the structure of the fourteenth diagram, and waveforms 1100 and 1400 represent the structure of the fifteenth diagram. The waveforms, as seen by waveforms 900, 1000, 1100, 1200, 1300, and 1400, are the total structure of the architecture used in this creation, whether at the same gate bias voltage V _G or the same gate bias voltage V _D . The gate charge (Qg) is low, and further, it can be seen from the following table that Qgd is also low.

In summary, after adopting the main technical means of the field effect transistor having the multi-width electrode structure provided by the present invention, since the electrode structure exhibits multiple widths and different heights, the first width of the first electrode portion is smaller than the second width. a second width of the electrode portion, a second width of the second electrode portion is smaller than a third width of the gate portion, and a second height of the second electrode portion is less than or equal to a first height of the first electrode portion, thereby effectively reducing the total Gate charge, actual performance index, input capacitance, output capacitance, and reverse conversion capacitance, which greatly increase the performance of the field effect transistor.

The features and spirit of the present invention are more clearly described in the above detailed description of the preferred embodiments, and the scope of the present invention is not limited by the preferred embodiments disclosed herein. On the contrary, it is intended to cover all kinds of changes and equivalences within the scope of the patent application to which the present invention is intended.

1‧‧‧Multiple width electrode structure Field effect transistor

11‧‧‧Semiconductor substrate

12‧‧‧ epitaxial layer

13‧‧‧Oxide layer

14‧‧‧First electrode section

15‧‧‧Width gradient

16‧‧‧Second electrode section

17‧‧‧ gate oxide layer

18‧‧‧Bridge

19‧‧‧ Body area

20‧‧‧ source area

21‧‧‧Interlayer dielectric layer

22‧‧‧Source electrode

Claims (3)

A field effect transistor having a multi-width electrode structure, comprising: a semiconductor substrate; an epitaxial layer formed on the semiconductor substrate and extending in a vertical direction with at least one trench having a trench a sidewall of the trench and a bottom of the trench; an oxide layer formed on the sidewall of the trench and the bottom of the trench, and having a first tapered structure gradually recessed from the periphery toward the center of the trench; a first electrode portion Adjacent to the bottom of the trench, the oxide layer is spaced apart from the epitaxial layer, and has a first height and a first width along a vertical direction and a horizontal direction perpendicular to the vertical direction; The width grading portion fills the first tapered structure, extending from the first electrode portion toward the bottom of the trench, and is separated from the epitaxial layer by the oxide layer; a second electrode portion is attached The trench extends from the width grading portion toward the bottom of the trench, and the oxide layer is spaced apart from the epitaxial layer, and has a second height and a second width respectively along the vertical direction and the horizontal direction. a gate oxide layer, Formed on the trench sidewall, the oxide layer and the second electrode portion, and located in the trench; a gate portion is formed on the gate oxide layer, and the gate oxide layer The second electrode portions are spaced apart and have a third width along the horizontal direction; a body region is disposed on the epitaxial layer and adjacent to the gate portion, and is separated from the gate portion by the gate oxide layer; a source region is disposed on the body region And the gate oxide layer is spaced apart from the gate portion; an interlayer dielectric layer covers the source region and the gate portion; and a source electrode covers the body region and the interlayer layer The electrical layer is in contact with the source region; wherein the first height is greater than or equal to the second height, the first width is less than the second width, and the second width is less than the third width. The field effect transistor having a multi-width electrode structure according to claim 1, wherein the oxide layer has a second recess adjacent to the second electrode portion adjacent to the second electrode portion. Gradient structure. A field effect transistor having a multi-width electrode structure as described in claim 2, wherein the gate oxide layer fills the second diffractive structure.