TWI910048B - Silver-plating process for wafers - Google Patents
Silver-plating process for wafersInfo
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- TWI910048B TWI910048B TW114117730A TW114117730A TWI910048B TW I910048 B TWI910048 B TW I910048B TW 114117730 A TW114117730 A TW 114117730A TW 114117730 A TW114117730 A TW 114117730A TW I910048 B TWI910048 B TW I910048B
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Abstract
本發明關於提供被動元件沾銀製程的一種晶片斜沾銀製程方法,可以提升其在電子產品品質的穩定度,主要係將數個晶片轉移埋入至一第二載板內後,再以偏位平針壓抵晶片的第一邊角以凸露於該第二載板;再對該第一邊角進行沾銀烘乾;再以滾輪將該第一邊角以滾壓方式將其壓入於該第二載板內;再以頂出平針將該晶片從該第二載板轉移埋入至一第三載板內;再以偏位平針壓抵該晶片的第二邊角凸露於該第三載板;再對該晶片的第二邊角進行沾銀烘乾;最後,再以頂出平針將該晶片壓出於該第三載板外,以完成整個的沾銀製程。This invention relates to a method for a passive component silver plating process, which can improve the stability of electronic product quality. The method mainly involves transferring several chips into a second substrate, then pressing a first corner of the chip against the substrate using an offset pin to expose it; then applying silver plating to the first corner and drying it; then pressing the first corner into the second substrate using a roller; then transferring the chip from the second substrate into a third substrate using an ejector pin; then pressing a second corner of the chip against the substrate using an offset pin to expose it; then applying silver plating to the second corner of the chip and drying it; finally, pressing the chip out of the third substrate using an ejector pin to complete the entire silver plating process.
Description
本發明係關於一種被動元件的製程領域,尤指一種晶片斜沾銀製程之技術範疇。This invention relates to the field of passive component manufacturing processes, and more particularly to a technique for a wafer oblique silver plating process.
按,被動元件的電極沾銀(Ag Dipping)技術主要用於增強電極的導電性、提高焊接性及提升可靠性。該技術廣泛應用於陶瓷電容(MLCC)、壓電元件、電阻器及感測元件等。Note that the ag dipping technique for passive components is mainly used to enhance the conductivity of the electrodes, improve solderability, and increase reliability. This technique is widely used in ceramic capacitors (MLCCs), piezoelectric elements, resistors, and sensing elements.
然而,現代電子科技日新月異,輕薄短小的電子產品陸續問世,陶瓷芯子的尺寸被要求越來越小,平面沾銀的技術已不敷需求。又因陶瓷芯子斜沾銀電極可克服其位於電子產品內的溫度差異及震動所產生脆裂之不穩定性、進而提高該電子產品固定的穩定性、也同時提高電感值的精準度,以使大量電子3C產品更加小型、精細、且價格合理,但市面上卻未見到晶片斜沾銀之相關技術,極待開發。However, with the rapid development of modern electronic technology and the emergence of increasingly thin and small electronic products, the size of ceramic cores is required to be smaller and smaller, and the flat silver plating technology is no longer sufficient to meet the needs. Furthermore, because oblique silver plating of ceramic core electrodes can overcome the instability caused by temperature differences and vibrations within electronic products, thereby improving the stability of the electronic product and improving the accuracy of inductance values, it is possible to make a large number of electronic 3C products smaller, more refined, and more affordable. However, related technologies for oblique silver plating of chips are not yet available on the market and are in great need of development.
緣此,本發明人乃窮極心思開發出本發明晶片斜沾銀製程方法,故本發明之主要目的:在於提供增進電子產品固定的穩定性的一種晶片斜沾銀製方法程;本發明之次要目的:在於提供最少製程步驟的晶片斜沾銀製程方法。Therefore, the inventors have devoted themselves to developing the wafer oblique silver plating process of the present invention. Thus, the primary objective of the present invention is to provide a wafer oblique silver plating process that improves the stability of electronic product mounting; the secondary objective of the present invention is to provide a wafer oblique silver plating process with the fewest process steps.
為達上述目的,本發明關於晶片斜沾銀製程方法係運用如下技術手段,其包含有:一植入裝料步驟,係將數個晶片由一第一載板轉移埋入至一第二載板的內部;一轉下凸步驟,係以數支偏位平針插入並壓抵位於該第二載板內的該數個晶片的一邊而分別呈現傾斜效果,並將該數個晶片的各第一邊角凸露於該第二載板;一第一次沾銀烘乾步驟,係對該數個晶片的各第一邊角進行沾銀並烘乾;一滾壓平步驟,係以至少一滾輪,再將該數個晶片已沾銀的各第一邊角以滾壓方式將其壓入於該第二載板的內部;一轉空板步驟,係將該第二載板與一第三載板互為相疊後,再以數支頂出平針將該數個晶片從該第二載板轉移埋入至一第三載板的內部;一轉向凸步驟,係以數支偏位平針壓抵該數個晶片的另一邊而分別呈現傾斜效果,並將該數個晶片的各第二邊角凸露於該第三載板;一第二次沾銀烘乾步驟,係對該數個晶片的各第二邊角進行沾銀並烘乾;及一卸料步驟,再以數支頂出平針插入於該第三載板,並將該數個晶片壓出於該第三載板外。To achieve the above objectives, the present invention relates to a wafer oblique silver-coating process using the following technical means, comprising: an implantation loading step, in which several wafers are transferred from a first substrate and embedded into the interior of a second substrate; a tilting protrusion step, in which several offset flat pins are inserted and pressed against one side of the wafers located in the second substrate to create an oblique effect, and each first corner of the wafers protrudes from the second substrate; a first silver-coating and drying step, in which each first corner of the wafers is silver-coated and dried; and a rolling flattening step, in which at least one roller is used to roll the silver-coated first corners of the wafers. The process involves pressing the wafers into the interior of the second substrate; a blanking step, in which the second substrate and a third substrate are stacked on top of each other, and several ejector pins are used to transfer the wafers from the second substrate into the interior of the third substrate; a convex turning step, in which several offset pins are used to press against the other side of the wafers to create a tilting effect, and the second corners of the wafers protrude from the third substrate; a second silver coating and drying step, in which the second corners of the wafers are coated with silver and dried; and an unloading step, in which several ejector pins are inserted into the third substrate and the wafers are pressed out of the third substrate.
其中該第一載板為導板,而該第二載板與該第三載板均為薄膠板。The first carrier plate is a guide plate, while the second and third carrier plates are both thin plastic sheets.
其中該偏位平針的頭部寬度小於該頂出平針的頭部寬度。The head width of the offset flat needle is smaller than the head width of the protruding flat needle.
其中在該植入裝料步驟中,該數個晶片係位於該第二載板內部的頂緣或下緣切齊。In the implantation and loading step, the chips are located at the top or bottom edge of the second substrate.
其中在該植入裝料步驟中,該第一載板位於該第二載板位的下方,而該第一載板的下方則設有數個沖針組與位於該第一載板內的該數個晶片互為對應。In the implantation loading step, the first carrier plate is located below the second carrier plate, and several punch groups are provided below the first carrier plate, which correspond to the several chips located in the first carrier plate.
其中在該轉空板步驟中,該數個晶片係位於該第三載板內部的頂緣或下緣切齊。In the empty board step, the chips are located at the top or bottom edge of the third carrier board.
其中在該轉空板步驟中,該第三載板位於該第二載板位的下方,而該第二載板的上方則設有該數支頂出平針與位於該第二載板內的該數個晶片互為對應。In the empty board step, the third carrier board is located below the second carrier board, and the second carrier board has several ejector pins on top of it that correspond to the several chips located inside the second carrier board.
其中在該轉下凸步驟中,該數個晶片分別以一第一支點進行傾斜。In the downward convex step, the wafers are tilted around a first fulcrum.
其中在該轉向凸步驟中,該數個晶片分別以一第二支點進行傾斜。In the turning convex step, the chips are tilted at a second fulcrum.
其中在該滾壓平步驟中,係以二滾輪分別置於並接觸該第二載板的上緣及下緣方式來進行滾壓入切齊。In the rolling process, two rollers are placed on and in contact with the upper and lower edges of the second carrier plate to roll into the edge for alignment.
本發明藉由上述技術手段,可以達成如下功效:By employing the aforementioned technical means, this invention can achieve the following effects:
1.本發明製程方法主要提供被動元件等相關晶片之二端電極底部的斜沾銀。前述該等晶片及其斜沾銀電極可克服讓其位於電子產品內的溫度差異及震動所產生脆裂之不穩定性、進而提高該電子產品品質的穩定性、也同時提高電感值的精準度,讓大量電子3C產品更加小型、精細、且價格合理。1. The manufacturing process of this invention mainly provides oblique silver plating on the bottom of the two electrodes of passive components and related chips. The aforementioned chips and their oblique silver-plated electrodes can overcome the instability caused by temperature differences and vibrations within electronic products, thereby improving the stability of the electronic product quality and simultaneously improving the accuracy of inductance values, making a large number of electronic 3C products smaller, more refined, and more reasonably priced.
2.本發明製程方法係為最少步驟的製程方法,藉由此方法可以簡化自動沾銀專用機台的裝置機構的複雜程度。2. The process method of this invention is the process method with the fewest steps, thereby simplifying the complexity of the device mechanism of the automatic silver plating machine.
本發明係關於一種晶片斜沾銀製程方法,如圖1及圖2所示,係主要提供被動元件晶片4的二端電極40的第一邊角41及第二邊角42進行沾銀的方法,進而提升其及電子產品品質的穩定度;其中該晶片斜沾銀製程方法A係包含有:一植入裝料步驟a、一轉下凸步驟b、一第一次沾銀烘乾步驟c、一滾壓平步驟d、一轉空板步驟e、一轉向凸步驟f、一第二次沾銀烘乾步驟g及一卸料步驟h;茲將上述流程步驟配合圖式說明如後,特別說明,本發明各圖式列舉較大晶片4與晶片4a且分列於二點鏈線的兩側來配合說明。This invention relates to a method for oblique silver plating of a wafer, as shown in Figures 1 and 2. It mainly provides a method for plating silver onto the first corner 41 and second corner 42 of the two electrodes 40 of a passive component wafer 4, thereby improving the stability of its quality and that of electronic products. The oblique silver plating process A includes: an implantation loading step a, a downward rotating convex... Step b, a first silver-dip drying step c, a rolling flattening step d, a turning empty plate step e, a turning convex step f, a second silver-dip drying step g, and a unloading step h; the above process steps are explained below with reference to the diagrams. In particular, the diagrams of this invention use larger chip 4 and chip 4a as examples, arranged on both sides of a two-point chain for illustration.
該植入裝料步驟a,如圖1及圖3所示,係將呈現二維矩陣排列的數個晶片4(或晶片4a)由一第一載板1轉移埋入至一第二載板2的內部;其中該第一載板1為導板,而該第二載板2為薄膠板(Thin Carrier Plate,簡稱TCP),且將該第一載板1位於該第二載板2位的下方,而該第一載板1的下方則設有數個沖針組5與位於該第一載板1內的該數個晶片4(或晶片4a)互為對應,即該數個沖針組5亦呈現二維矩陣排列,以利將該數個晶片4(或晶片4a)由該第一載板1的位置轉移埋入至該第二載板2的位置。而該數個晶片4位於該第二載板2內部的位置不同於該數個晶片4a位於該第二載板2內部的位置,換言之,讓該數個晶片4位於該第二載板2內部的上緣21切齊,而讓該數個晶片4a位於該第二載板2內部的下緣22切齊。As shown in Figures 1 and 3, the implantation step a involves transferring several chips 4 (or chips 4a) arranged in a two-dimensional matrix from a first carrier plate 1 into the interior of a second carrier plate 2. The first carrier plate 1 is a guide plate, and the second carrier plate 2 is a thin carrier plate (TCP). The first carrier plate 1 is positioned below the second carrier plate 2. Below the first carrier plate 1, there are several punch groups 5 that correspond to the chips 4 (or chips 4a) located within the first carrier plate 1. That is, the punch groups 5 are also arranged in a two-dimensional matrix to facilitate the transfer of the chips 4 (or chips 4a) from the position of the first carrier plate 1 into the position of the second carrier plate 2. The positions of the chips 4 inside the second substrate 2 are different from the positions of the chips 4a inside the second substrate 2. In other words, the upper edge 21 of the chips 4 inside the second substrate 2 is aligned with the upper edge 21, while the lower edge 22 of the chips 4a inside the second substrate 2 is aligned with the upper edge 22.
該轉下凸步驟b,如圖1及圖4所示,係以呈現二維矩陣排列的數支偏位平針6往下插入並壓抵位於該第二載板2內的該數個晶片4(或晶片4a)的一邊而分別呈現傾斜效果,並將該數個晶片4的各第一邊角41凸露於該第二載板2。其中該數個晶片4分別大約在一第一支點23為中心,經該數支偏位平針6的壓抵來進行傾斜旋轉而凸露;而該數個晶片4a亦分別大約在一第一支點23為中心,經該數支偏位平針6的壓抵來進行傾斜旋轉而凸露。As shown in Figures 1 and 4, step b involves inserting several offset pins 6 arranged in a two-dimensional matrix downwards and pressing them against one side of several chips 4 (or chips 4a) located within the second substrate 2, thereby tilting them and exposing the first corners 41 of each chip 4 to the second substrate 2. Each chip 4 is tilted and rotated approximately around a first fulcrum 23, and the chips 4a are also tilted and rotated approximately around a first fulcrum 23, and are thus exposed.
該第一次沾銀烘乾步驟c,如圖1及圖5所示,係對該數個晶片(或晶片4a)已凸露於該第二載板2的各第一邊角41進行沾銀並烘乾。其沾銀的方式為將該第二載板2移到一沾銀槽9的正上方後,往正下方移動至前述該各第一邊角41浸入該沾銀槽9內部的銀液91止,再恢復至該沾銀槽9的正上方位置,然後再移動該第二載板2至一烘乾箱來進行烘乾前述沾銀的部位。The first silvering and drying step c, as shown in Figures 1 and 5, involves silvering and drying the first edges 41 of the several wafers (or wafers 4a) that are protruding from the second substrate 2. The silvering method is as follows: the second substrate 2 is moved directly above a silvering tank 9, then moved directly downwards until the aforementioned first edges 41 are immersed in the silver liquid 91 inside the silvering tank 9, and then returned to the position directly above the silvering tank 9. Then, the second substrate 2 is moved to a drying oven to dry the aforementioned silvered areas.
該滾壓平步驟d,如圖1及圖6所示,係使用至少一滾輪7移至經烘乾後的該第二載板2之一側,再以該至少一滾輪7將該數個晶片4(或晶片4a)已沾銀的各第一邊角41以滾壓方式將其壓入於該第二載板2的內部,而本步驟較佳的方式是以二滾輪7分別置於並接觸該第二載板2一側的上緣21及下緣22方式來將已沾銀的各第一邊角41進行滾壓入並切齊於該上緣21。As shown in Figures 1 and 6, the rolling step d involves using at least one roller 7 to move to one side of the dried second carrier plate 2, and then using the at least one roller 7 to press the silver-coated first edges 41 of the plurality of wafers 4 (or wafers 4a) into the interior of the second carrier plate 2 by rolling. A preferred method for this step is to use two rollers 7 respectively placed on and in contact with the upper edge 21 and lower edge 22 of one side of the second carrier plate 2 to roll and cut the silver-coated first edges 41 into the upper edge 21.
該轉空板步驟e,如圖1及圖7所示,係將該第二載板2與一第三載板3互為相疊後,再以呈現二維矩陣排列的數支頂出平針8將該數個晶片4(或晶片4a)從該第二載板2轉移埋入至該第三載板3的內部的上緣31(或下緣32),而該數個晶片4位於該第三載板3內部的位置不同於該數個晶片4a位於該第三載板3內部的位置,換言之,讓該數個晶片4位於該第三載板3內部的上緣31切齊,而讓該數個晶片4a位於該第三載板3內部的下緣32切齊。其中於本實施例,該第三載板3亦為TCP薄膠板,且該第二載板2位於該第三載板3的上方,讓該數支頂出平針8則從該第二載板2的上方插入,以移動位於該第二載板2內部的該數個晶片4(或晶片4a)至該第三載板3的內部的上緣31(或下緣32)。As shown in Figures 1 and 7, the empty board transfer step e involves stacking the second carrier board 2 and the third carrier board 3 on top of each other, and then using several ejector pins 8 arranged in a two-dimensional matrix to transfer the chips 4 (or chips 4a) from the second carrier board 2 and embed them into the upper edge 31 (or lower edge 32) inside the third carrier board 3. The position of the chips 4 inside the third carrier board 3 is different from the position of the chips 4a inside the third carrier board 3. In other words, the upper edge 31 of the chips 4 inside the third carrier board 3 is aligned with the upper edge 31, while the lower edge 32 of the chips 4a inside the third carrier board 3 is aligned with the upper edge 31. In this embodiment, the third carrier board 3 is also a TCP thin film board, and the second carrier board 2 is located above the third carrier board 3, so that the several ejector pins 8 are inserted from above the second carrier board 2 to move the several chips 4 (or chips 4a) located inside the second carrier board 2 to the upper edge 31 (or lower edge 32) inside the third carrier board 3.
該轉向凸步驟f,如圖1及圖8所示,同該轉下凸步驟b的作法,係以呈現二維矩陣排列的數支偏位平針6壓抵該數個晶片4(或晶片4a)未沾銀的另一邊,而分別呈現傾斜效果,並將該數個晶片4(或晶片4a)的各第二邊角42凸露於該第三載板3。即讓該數個晶片4分別大約在一第二支點33為中心,經該數支偏位平針6的壓抵來進行傾斜旋轉而凸露;而該數個晶片4a亦分別大約在一第二支點33為中心,經該數支偏位平針6的壓抵來進行傾斜旋轉而凸露。As shown in Figures 1 and 8, the turning convex step f is similar to the turning convex step b. It involves several offset pins 6 arranged in a two-dimensional matrix pressing against the un-silvered sides of the wafers 4 (or wafers 4a), creating a tilting effect and exposing the second corners 42 of each wafer 4 (or wafer 4a) to the third substrate 3. Specifically, the wafers 4 are tilted and rotated approximately around a second fulcrum 33, and the wafers 4a are also tilted and rotated approximately around a second fulcrum 33, and thus exposed.
該第二次沾銀烘乾步驟g,如圖1及圖9所示,同該第一次沾銀烘乾步驟c的做法,係對該數個晶片4(或晶片4a)的各第二邊角42進行沾銀並烘乾;即將該第三載板3移到該沾銀槽9的正上方後,往正下方移動至前述該各第二邊角42浸入該沾銀槽9內部的銀液91止,再恢復至該沾銀槽9的正上方位置,然後再移動該第三載板3至一烘乾箱來進行烘乾前述沾銀的部位。The second silvering and drying step g, as shown in Figures 1 and 9, is the same as the first silvering and drying step c. It involves silvering and drying each of the second edges 42 of the chips 4 (or chips 4a). Specifically, the third carrier plate 3 is moved directly above the silvering tank 9, then moved directly downwards until the silver liquid 91 inside the silvering tank 9 is immersed in the aforementioned second edges 42. It is then returned to the position directly above the silvering tank 9, and then the third carrier plate 3 is moved to a drying oven to dry the aforementioned silvered areas.
該卸料步驟h,如圖1及圖10所示,再以呈現二維矩陣排列的數支頂出平針8插入於該第三載板3,並將該數個晶片4(或晶片4a)壓出於該第三載板3外。特別說明,通常該偏位平針6的頭部寬度小於該頂出平針8的頭部寬度。As shown in Figures 1 and 10, in the unloading step h, several ejector pins 8 arranged in a two-dimensional matrix are inserted into the third carrier plate 3, and the several wafers 4 (or wafers 4a) are pressed out of the third carrier plate 3. It should be noted that the head width of the offset pin 6 is usually smaller than the head width of the ejector pin 8.
因此,本發明提供一種晶片斜沾銀製程的較佳解決方案,進而提升晶片及其在電子產品品質的穩定度,係主要係將數個晶片4(或晶片4a)由該第一載板1都轉移埋入至一第二載板2內後,再以該數個偏位平針6壓抵該數個晶片4(或晶片4a)兩端電極40的所有第一邊角41均凸露於該第二載板2;再對所有該第一邊角41進行沾銀烘乾;再以該滾輪7將所有該第一邊角41以滾壓方式將其壓入於該第二載板2內;再以該數個頂出平針8將該數個晶片4(或晶片4a)從該第二載板2轉移埋入至一第三載板3內;再以該數個偏位平針6壓抵該數個晶片4(或晶片4a)的所有第二邊角42均凸露於該第三載板3;再對該數個晶片4(或晶片4a)的所有第二邊角42均進行沾銀烘乾;最後,再以該數個頂出平針8將該數個晶片4(或晶片4a)均壓出於該第三載板3外,以完成整個的沾銀製程。Therefore, this invention provides a better solution for a wafer oblique silver plating process, thereby improving the stability of the wafer and its quality in electronic products. The main process involves transferring several wafers 4 (or wafers 4a) from the first substrate 1 and embedding them into a second substrate 2. Then, several offset pins 6 are used to press all the first edges 41 of the electrodes 40 at both ends of the wafers 4 (or wafers 4a) so that they protrude from the second substrate 2. Next, all the first edges 41 are silver-plated and dried. Finally, rollers 7 are used to press all the first edges 41 into the substrate by rolling. Inside the second substrate 2; then, the several ejector pins 8 are used to transfer the several chips 4 (or chips 4a) from the second substrate 2 and embed them into a third substrate 3; then, the several offset pins 6 are used to press all the second edges 42 of the several chips 4 (or chips 4a) so that they protrude from the third substrate 3; then, all the second edges 42 of the several chips 4 (or chips 4a) are dipped in silver and dried; finally, the several ejector pins 8 are used to press the several chips 4 (or chips 4a) out of the third substrate 3 to complete the entire silver plating process.
綜上所述,本發明係關於一種晶片斜沾銀製程方法,且上述所構成製程步驟及方法均未曾見於書刊或公開使用,誠符合發明專利申請要件,懇請鈞局明鑑,早日准予專利,至為感禱;In conclusion, this invention relates to a method for oblique silver plating on wafers, and the above-mentioned process steps and methods have not been seen in any books or publicly used. It truly meets the requirements for an invention patent application. We earnestly request the Bureau of Technology to review this invention and grant the patent as soon as possible. We are deeply grateful.
需陳明者,以上所述乃是本案之具體實施例所運用之技術原理,若依照本案構想所作之改變,其所產生之功能及作用均未超出本說明書及圖式所涵蓋精神時,均應在本案之申請專利範圍內,合予陳明。It should be stated that the above-described technical principles are those used in the specific implementation of this case. Any changes made in accordance with the concept of this case, provided that their functions and effects do not exceed the spirit of this specification and drawings, shall be stated within the scope of the patent application in this case.
A:晶片斜沾銀製程方法 a:植入裝料步驟 b:轉下凸步驟 c:第一次沾銀烘乾步驟 d:滾壓平步驟 e:轉空板步驟 f:轉向凸步驟 g:第二次沾銀烘乾步驟 h:卸料步驟 1:第一載板 2:第二載板 21:上緣 22:下緣 23:第一支點 3:第三載板 31:上緣 32:下緣 33:第二支點 4:晶片 40:電極 4a:晶片 41:第一邊角 42:第二邊角 5:沖針組 6:偏位平針 7:滾輪 8:頂出平針 9:沾銀槽 91:銀液A: Wafer Angled Silver Dipping Process a: Implantation Loading Step b: Turning Downward Convex Step c: First Silver Dipping and Drying Step d: Rolling Flattening Step e: Turning Empty Plate Step f: Turning Toward Convex Step g: Second Silver Dipping and Drying Step h: Unloading Step 1: First Carrier Plate 2: Second Carrier Plate 21: Upper Edge 22: Lower Edge 23: First Support Point 3: Third Carrier Plate 31: Upper Edge 32: Lower Edge 33: Second Support Point 4: Wafer 40: Electrode 4a: Wafer 41: First Corner 42: Second Corner 5: Punch Pin Assembly 6: Offset Flat Pin 7: Roller 8: Ejector Flat Pin 9: Silver Dipping Tank 91: Silver Liquid
[圖1]本發明晶片斜沾銀製程方法之步驟流程圖。 [圖2]晶片完成本發明沾銀製程方法後之外觀示意圖。 [圖3]本發明關於其植入裝料步驟之示意圖。 [圖4]本發明關於其轉下凸步驟之示意圖。 [圖5]本發明關於其第一次沾銀烘乾步驟之示意圖。 [圖6]本發明關於其滾壓平步驟之示意圖。 [圖7]為本發明關於其轉空板步驟之示意圖。 [圖8]為本發明關於其轉向凸步驟之示意圖。 [圖9]為本發明關於其第二次沾銀烘乾步驟之示意圖 [圖10]為本發明關於其卸料步驟之示意圖。[Figure 1] Flowchart of the wafer oblique silver plating process of the present invention. [Figure 2] Schematic diagram of the appearance of the wafer after the completion of the silver plating process of the present invention. [Figure 3] Schematic diagram of the implantation loading step of the present invention. [Figure 4] Schematic diagram of the turning-down bump step of the present invention. [Figure 5] Schematic diagram of the first silver plating drying step of the present invention. [Figure 6] Schematic diagram of the rolling flattening step of the present invention. [Figure 7] Schematic diagram of the empty board turning step of the present invention. [Figure 8] Schematic diagram of the turning-up bump step of the present invention. [Figure 9] Schematic diagram of the second silver plating drying step of the present invention. [Figure 10] Schematic diagram of the unloading step of the present invention.
A:晶片斜沾銀製程方法 A: Silver plating process for wafers (oblique application)
a:植入裝料步驟 a: Implantation procedure
b:轉下凸步驟 b: Turn down the convex step
c:第一次沾銀烘乾步驟 c: First silver-dipped and dried step
d:滾壓平步驟 d: Rolling flat step
e:轉空板步驟 e: Steps to switch to an empty board
f:轉向凸步驟 f: Turning step
g:第二次沾銀烘乾步驟 g: Second silver coating and drying step
h:卸料步驟 h: Unloading steps
Claims (10)
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| US20140097004A1 (en) | 2009-01-27 | 2014-04-10 | Panasonic Corporation | Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same |
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| US20140097004A1 (en) | 2009-01-27 | 2014-04-10 | Panasonic Corporation | Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same |
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