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JPH062241Y2 - Chip resistance - Google Patents

Chip resistance

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Publication number
JPH062241Y2
JPH062241Y2 JP13682189U JP13682189U JPH062241Y2 JP H062241 Y2 JPH062241 Y2 JP H062241Y2 JP 13682189 U JP13682189 U JP 13682189U JP 13682189 U JP13682189 U JP 13682189U JP H062241 Y2 JPH062241 Y2 JP H062241Y2
Authority
JP
Japan
Prior art keywords
chip resistor
resistor
electrodes
insulating substrate
ceramic substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP13682189U
Other languages
Japanese (ja)
Other versions
JPH0375501U (en
Inventor
龍 荒澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koa Corp
Original Assignee
Koa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koa Corp filed Critical Koa Corp
Priority to JP13682189U priority Critical patent/JPH062241Y2/en
Publication of JPH0375501U publication Critical patent/JPH0375501U/ja
Application granted granted Critical
Publication of JPH062241Y2 publication Critical patent/JPH062241Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Non-Adjustable Resistors (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は、プリント配線板に面実装されるチップ抵抗に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a chip resistor surface-mounted on a printed wiring board.

〔従来の技術〕[Conventional technology]

第2図は従来一般のチップ抵抗をプリント配線板上に実
装した状態を示す断面図である。
FIG. 2 is a sectional view showing a state in which a conventional general chip resistor is mounted on a printed wiring board.

同図において、チップ抵抗1は、スラリを薄板状に形成
した所謂グリーンシートを焼成・分割してなる略直方体
のセラミック基板2と、このセラミック基板2の側面を
抱き込んで天面および底面に至る一対の電極3,4と、
銀くわれを防止するために各電極3,4の表面に被着さ
れたニッケルメッキ層5,6と、はんだ濡れ性を確保す
るたに各ニッケルメッキ層5,6の表面に被着されたは
んだメッキ層7,8と、セラミック基板2の天面で両電
極3,4を連結する抵抗体9と、この抵抗体9の表面を
覆うガラス材等のオーバコート10とによつて構成され
ている。
In FIG. 1, a chip resistor 1 has a substantially rectangular parallelepiped ceramic substrate 2 formed by firing and dividing a so-called green sheet in which a slurry is formed into a thin plate, and a side surface of the ceramic substrate 2 is held to reach a top surface and a bottom surface. A pair of electrodes 3, 4,
Nickel plating layers 5 and 6 applied to the surfaces of the electrodes 3 and 4 to prevent silver nicking, and nickel plating layers 5 and 6 to ensure solder wettability. The solder plating layers 7 and 8, a resistor 9 that connects the electrodes 3 and 4 on the top surface of the ceramic substrate 2, and an overcoat 10 such as a glass material that covers the surface of the resistor 9 are used. There is.

かかるチツプ抵抗1をプリント配線板11上に実装する
際には、図示せぬ自動実装機のマウントノズルで天面側
のオーバコート10を吸引チャッキングし、予ペースト
状のはんだを塗布しておいた一対のランド12,13に
電極3,4を位置合わせしてチップ抵抗1を搭載した
後、リフロー炉等で加熱してはんだ付けを行い、これに
よってチップ抵抗1はプリント配線板11に面実装され
る。なお、図中の符号14,15ははんだを示してい
る。
When mounting the chip resistor 1 on the printed wiring board 11, the overcoat 10 on the top surface side is suction-chucked by a mount nozzle of an automatic mounting machine (not shown), and pre-paste solder is applied. After mounting the chip resistor 1 by aligning the electrodes 3 and 4 with the pair of lands 12 and 13, the chip resistor 1 is surface-mounted on the printed wiring board 11 by heating in a reflow furnace or the like for soldering. To be done. Reference numerals 14 and 15 in the drawing indicate solder.

〔考案が解決しようとする課題〕[Problems to be solved by the device]

しかしながら、上述した従来のチップ抵抗1は、バレル
メッキ等により形成されるニッケルメッキ層5,6およ
びはんだメッキ層7,8の厚みを高精度に規定すること
が困難であるという理由で、外形寸法にばらつきを生じ
やすく、そのため該チップ抵抗1をプリント配線板11
にランド12,13上へ搭載する際に、位置ずれを起こ
しやすいという不具合があった。
However, in the conventional chip resistor 1 described above, it is difficult to precisely define the thicknesses of the nickel plating layers 5 and 6 and the solder plating layers 7 and 8 formed by barrel plating or the like. Of the printed circuit board 11 and therefore the chip resistor 1
However, there is a problem in that when it is mounted on the lands 12 and 13, a positional deviation easily occurs.

また、該チップ抵抗1の天面側には、抵抗体9を覆うオ
ーバーコート10の表面や周縁に段差が形成されている
ので、マウントノズルによるチャッキング時に空気が漏
れやすく、そのためチャッキング不良をおこして実装率
が低下するという不具合もあった。
Further, on the top surface side of the chip resistor 1, since a step is formed on the surface and the peripheral edge of the overcoat 10 that covers the resistor 9, air easily leaks at the time of chucking by the mount nozzle, so that a chucking failure occurs. There was also a problem that the mounting rate decreased.

本考案はこのような事情に鑑みてなされたもので、その
目的は、ランドとの位置ずれたチャッキング不良を起こ
しにくく自動実装に好適なチップ抵抗を提供することに
ある。
The present invention has been made in view of such circumstances, and an object thereof is to provide a chip resistor that is less likely to cause a chucking defect that is displaced from the land and is suitable for automatic mounting.

〔課題を解決するための手段〕[Means for Solving the Problems]

上記目的を達成するために、本考案は、略直方体の絶縁
基板の表面に、メッキ層に被覆された一対の電極と、こ
れら両電極間を連結する抵抗体とを備えたチップ抵抗に
おいて、上記絶縁基板の底面の両端部を凹凸形状となし
て該凹凸部分に上記電極を設け、該絶縁基板の底面の中
央部に上記抵抗体を設ける構成とした。
In order to achieve the above object, the present invention provides a chip resistor having a pair of electrodes coated with a plating layer on the surface of an insulating substrate having a substantially rectangular parallelepiped shape, and a resistor connecting the two electrodes. Both ends of the bottom surface of the insulating substrate are formed in a concavo-convex shape, the electrodes are provided on the concavo-convex portion, and the resistor is provided at the central portion of the bottom surface of the insulating substrate.

〔作用〕[Action]

チップ抵抗の底面側に電極と抵抗体とを配設すれば、該
チップ抵抗の側面および天面には絶縁基板(セラミック
基板)の平坦面のみを露出させることができ、よって該
チップ抵抗の外形寸法の精度が高まってランドとの位置
ずれが起こりにくくなるとともに、該チップ抵抗の天面
が平坦になってチャッキング不良が起こりにくくなり、
また、電極を絶縁基板の凹凸部分に形成して剥離強度を
高めているので、底面側のみの電極であっても実装後に
剥離を起こす心配はない。
By arranging the electrode and the resistor on the bottom surface side of the chip resistor, only the flat surface of the insulating substrate (ceramic substrate) can be exposed on the side surface and the top surface of the chip resistor. The dimensional accuracy is improved, and the positional deviation from the land is less likely to occur, and the top surface of the chip resistor is flattened, and the chucking failure is less likely to occur.
Further, since the electrodes are formed on the concave and convex portions of the insulating substrate to enhance the peeling strength, there is no fear of peeling after mounting even if the electrodes are only on the bottom surface side.

〔実施例〕〔Example〕

以下、本考案の実施例を図に基づいて説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本考案の一実施例に係るチップ抵抗をプリント
配線板上に実装した状態を示す断面図であって、第2図
と対応する部分には同一符号が付してある。
FIG. 1 is a sectional view showing a state in which a chip resistor according to an embodiment of the present invention is mounted on a printed wiring board, and the portions corresponding to those in FIG. 2 are designated by the same reference numerals.

第1図に示すチップ抵抗1は、略直方体のセラミック基
板2の底面の両端部に凹凸2a,2bが形成してあっ
て、これらの凹凸2a,2bの表面にそれぞれ電極3,
4が形成してあり、各電極3,4の表面にはニッケルメ
ッキ層5,6およびはんだメッキ層7,8が被着させて
ある。また、セラミック基板2の底面の中央部には、両
電極3,4間を連結する抵抗体9が形成してあり、この
抵抗体9の表面にはオーバーコート10が被着させてあ
る。つまり、このチップ抵抗1は、ニッケルメッキ層
5,6およびはんだメッキ層7,8に覆われた電極3,
4や、オーバーコート10に覆われた抵抗体9が、すべ
て底面側に配設してあって、このチップ抵抗1の側面お
よび天面にはセラミック基板2の平坦面のみが露出して
いる。
The chip resistor 1 shown in FIG. 1 has concavities and convexities 2a and 2b formed at both ends of the bottom surface of a substantially rectangular parallelepiped ceramic substrate 2, and electrodes 3 and 4 are formed on the surfaces of these concavities and convexities 2a and 2b, respectively.
4 are formed, and nickel plating layers 5 and 6 and solder plating layers 7 and 8 are adhered to the surfaces of the electrodes 3 and 4, respectively. Further, a resistor 9 for connecting the electrodes 3 and 4 is formed at the center of the bottom surface of the ceramic substrate 2, and an overcoat 10 is applied to the surface of the resistor 9. In other words, the chip resistor 1 includes the electrodes 3, 3 covered with the nickel plating layers 5, 6 and the solder plating layers 7, 8.
4 and the resistor 9 covered with the overcoat 10 are all disposed on the bottom surface side, and only the flat surface of the ceramic substrate 2 is exposed on the side surface and the top surface of the chip resistor 1.

上記チップ抵抗1の外形寸法Lは、グリーンシートの分
割溝のピッチにより規定されるセラミック基板2の外形
寸法と同等であり、ニッケルメッキ層5,6やはんだメ
ッキ層7,8に厚みに左右されなくなるので、寸法精度
が著しく向上している。したがって、このチップ抵抗1
をプリント配線板11のランド12,13上へ搭載する
際の位置合わせ精度が向上し、位置ずれが起こりにくく
なっている。また、このチップ抵抗1の天面は平坦なの
で、マウントノズルによるチャッキング時に空気漏れが
発生しにくく、そのため従来品に比べてチャッキング不
良が起こりにくくなっている。そして、このようにラン
ド12,13との位置ずれやチャッキング不良を起こし
にくいチップ抵抗1を用いて自動実装を行うことによ
り、実装率を大幅に高めることができる。
The outer dimension L of the chip resistor 1 is equal to the outer dimension of the ceramic substrate 2 defined by the pitch of the dividing grooves of the green sheet, and depends on the thickness of the nickel plating layers 5, 6 and the solder plating layers 7, 8. Since it disappears, the dimensional accuracy is significantly improved. Therefore, this chip resistor 1
The alignment accuracy is improved when the printed circuit board 11 is mounted on the lands 12 and 13 of the printed wiring board 11, and the positional deviation is less likely to occur. Further, since the top surface of the chip resistor 1 is flat, air leakage is less likely to occur during chucking by the mount nozzle, and therefore, chucking failure is less likely to occur as compared with the conventional product. The mounting rate can be significantly increased by automatically performing the mounting using the chip resistor 1 which is less likely to cause the positional deviation from the lands 12 and 13 and the chucking failure.

さらにまた、上記チップ抵抗1は、電極3,4をセラミ
ック基板2の凹凸2a,2bの表面に形成して剥離強度
を高めているので、底面側のみの電極3,4であっても
実装後に剥離を起こす心配はない。しかも、従来品がセ
ラミック基板の底面の他に側面および天面にも電極を印
刷形成していたのに対し、上記チップ抵抗1は底面のみ
に印刷すればよいので、工程数が削減でき、コストダウ
ンを図れるという利点もある。なお、上記凹凸2a,2
bは、セラミック基板2の母材であるグリーンシートに
分割溝を形成するプレス工程で一括して形成しておけば
よい。
Furthermore, in the chip resistor 1, since the electrodes 3 and 4 are formed on the surfaces of the irregularities 2a and 2b of the ceramic substrate 2 to enhance the peeling strength, even if the electrodes 3 and 4 only on the bottom surface side are mounted after mounting. There is no need to worry about peeling. In addition, in the conventional product, electrodes are formed by printing not only on the bottom surface of the ceramic substrate but also on the side surface and the top surface, whereas the chip resistor 1 needs to be printed only on the bottom surface. There is also an advantage that you can down. In addition, the unevenness 2a, 2
b may be collectively formed in a pressing process of forming the dividing groove in the green sheet which is the base material of the ceramic substrate 2.

〔考案の効果〕[Effect of device]

以上説明したように、本考案によれば、絶縁基板(セラ
ミック基板)の底面の両端部に形成した凹凸部分に電極
を設け、該絶縁基板の底面の中央部に抵抗体を設けてあ
るので、外形寸法の精度が高まってランドとの位置ずれ
が起こりにくく、かつ天面が平坦になってチャッキング
不良が起こりにくく、しかも底面側のみに電極を設けれ
ばよいので工程数が削減でき、自動実装に好適でコスト
ダウンが図れるチップ抵抗を提供することができる。
As described above, according to the present invention, the electrodes are provided on the uneven portions formed on both ends of the bottom surface of the insulating substrate (ceramic substrate), and the resistor is provided on the central portion of the bottom surface of the insulating substrate. The accuracy of the external dimensions is improved, the positional deviation from the land is unlikely to occur, the top surface is flat and chucking failure is less likely to occur, and the number of steps can be reduced because the electrodes can be provided only on the bottom side. It is possible to provide a chip resistor that is suitable for mounting and that can reduce the cost.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案の一実施例に係るチップ抵抗をプリント
配線板に実装した状態を示す断面図、第2図は従来一般
のチップ抵抗をプリント配線板に実装した状態を示す断
面図である。 1……チップ抵抗、2……セラミック基板(絶縁基
板)、2a,2b……凹凸、3,4……電極、5,6…
…ニッケルメッキ層、7,8……はんだメッキ層、9…
…抵抗体、10……オーバーコート、11……プリント
配線板、12,13……ランド。
FIG. 1 is a sectional view showing a state in which a chip resistor according to an embodiment of the present invention is mounted on a printed wiring board, and FIG. 2 is a sectional view showing a state in which a conventional general chip resistor is mounted on a printed wiring board. . 1 ... Chip resistance, 2 ... Ceramic substrate (insulating substrate), 2a, 2b ... Roughness, 3, 4 ... Electrode, 5, 6 ...
… Nickel plated layer, 7, 8 …… Solder plated layer, 9…
... resistor, 10 ... overcoat, 11 ... printed wiring board, 12,13 ... land.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】略直方体の絶縁基板の表面に、メッキ層に
被覆された一対の電極と、これら両電極間を連結する抵
抗体とを備え、プリント配線板に面実装されるチップ抵
抗において、上記絶縁基板の底面の両端部を凹凸形状と
なして該凹凸部分に上記電極を設け、該絶縁基板の底面
の中央部に上記抵抗体を設けたことを特徴とするチップ
抵抗。
1. A chip resistor surface-mounted on a printed wiring board, comprising a pair of electrodes coated with a plating layer on the surface of a substantially rectangular parallelepiped insulating substrate, and a resistor for connecting the two electrodes together. A chip resistor, characterized in that both ends of a bottom surface of the insulating substrate are formed in a concavo-convex shape, the electrodes are provided on the concavo-convex portion, and the resistor is provided at a central portion of the bottom surface of the insulating substrate.
JP13682189U 1989-11-28 1989-11-28 Chip resistance Expired - Lifetime JPH062241Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13682189U JPH062241Y2 (en) 1989-11-28 1989-11-28 Chip resistance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13682189U JPH062241Y2 (en) 1989-11-28 1989-11-28 Chip resistance

Publications (2)

Publication Number Publication Date
JPH0375501U JPH0375501U (en) 1991-07-29
JPH062241Y2 true JPH062241Y2 (en) 1994-01-19

Family

ID=31684008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13682189U Expired - Lifetime JPH062241Y2 (en) 1989-11-28 1989-11-28 Chip resistance

Country Status (1)

Country Link
JP (1) JPH062241Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5459400B2 (en) * 2010-06-11 2014-04-02 株式会社村田製作所 Electronic components

Also Published As

Publication number Publication date
JPH0375501U (en) 1991-07-29

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