TWI906008B - Memory testing method, memory testing device and non-transitory computer-readable storage medium - Google Patents

Abstract

A memory testing method comprises following steps. A bank of the memory is switched from an idle state to an active state. A delay-locked loop reset instruction is transmitted to the memory which is at the active state. A read instruction is transmitted to the memory, wherein a time calculated from the transmitting of the delay-locked loop reset instruction to the transmitting of the read instruction is less than a specific time. A reading result of the read instruction is received. In response to the reading result is fail, the memory is determined not to meet a double data rate fifth-generation standard.

Description

Memory testing methods, memory testing devices, and nontransient computer-readable storage media

This disclosure relates to a memory testing method, and more particularly to a memory testing method for determining whether memory meets the fifth-generation double data rate standard.

As memory component technology has advanced, manufacturers and academic institutions have established numerous universal standards to differentiate memory storage efficiency and speed. Products that meet certain specifications (such as storage capacity per unit area) or performance (such as read/write efficiency) can obtain corresponding certification marks. Memory manufacturers also typically refer to these established standards in their hardware design for promotional purposes and to meet customer requirements.

This disclosure provides a memory testing method applicable to electronic devices. The memory testing method includes: switching a first memory bank from an idle state to an enabled state; transmitting a delayed phase-locked loop (PLL) reset command to the enabled memory; transmitting a read command to the memory within a specific time period starting from the transmission of the PLL reset command; receiving a read result regarding the read command; and responding to a read failure by determining that the memory does not meet the fifth-generation double data rate standard.

This disclosure also provides a memory testing method applicable to electronic devices. The memory testing method includes: transmitting a delayed phase-locked loop (PLL) reset command to the memory; transmitting an enable command to the memory, wherein a first time interval between transmitting the delayed PLL reset command and transmitting the enable command is not less than the delayed PLL cycle; then... The system then transmits a delayed phase-locked loop (PLL) reset command to memory; transmits a read command to memory, wherein the second time interval between transmitting the delayed PLL reset command and transmitting the read command is less than the delayed PLL cycle; and responds if the read result fails, determining that the memory does not meet the fifth-generation double data rate standard.

This disclosure also provides a memory testing apparatus for testing memory, the memory testing apparatus including a processor, wherein the processor is configured to perform the following operations: switch a first library of memory from an idle state to an enabled state; transmit a delayed phase-locked loop reset instruction to the enabled memory; transmit a read instruction to the memory within a specific time period from the transmission of the delayed phase-locked loop reset instruction; receive a read result regarding the read instruction; and, in response to a read result failure, determine that the memory does not meet the fifth generation double data rate standard.

This disclosure also provides a non-transient computer-readable storage medium having at least one set of instructions stored thereon, which, when executed by a processing unit, perform the memory testing method.

It should be understood that the foregoing general description and the following specific description are merely exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure.

To make the description of this disclosure more detailed and complete, reference can be made to the accompanying figures and the various embodiments described below, in which the same numbers represent the same or similar elements.

Please refer to Figure 1, which is a schematic diagram of the memory testing device 12 and memory 14 in a partial embodiment of this disclosure. As shown in Figure 1, the memory testing device 12 includes a processor 122 and is coupled to the memory 14. The memory testing device 12 is used to determine whether the memory 14 conforms to the fifth generation double data rate standard.

Current memory standards, such as the double data rate fifth-generation (DDR5) standard set by the Joint Electron Devices Engineering Council (JEDEC), do not allow for specific operating methods.

For example, memory that meets the fifth generation double data rate standard can only execute specific instructions in the activated state and the idle state. For instance, the delayed-locked loop reset (DLL Reset) instruction cannot be executed in the activated state.

However, some memory products on the market do not meet the Double Data Rate 5 (DDR) standard and support specific operating modes. This would increase the flexibility in memory product design and further improve its performance. To determine whether a memory product complies with the relevant standard's operating limitations, competing manufacturers need to test it. However, current prior art lacks an effective and rapid memory testing method to test whether a memory product supports specific operating modes while not meeting the DDR standard. The memory testing device 12 disclosed herein provides a convenient and efficient way to test whether memory 14 meets the DDR standard.

In some embodiments, processor 122 may include a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and/or a suitable computing unit.

Please refer to Figure 2, which is a schematic diagram of memory 14 in a partial embodiment of this disclosure. Memory 14 includes a delay-locked loop (DLL) circuit 1402, a storage array 1404, a row decoder 1406, a column decoder 1408, and an input/output unit 1410. In one embodiment, memory 14 may be a synchronous dynamic random access memory (SDRAM).

The delayed phase-locked loop circuit 1402 is used to calibrate the clock signals for data output and input in memory 14 to stabilize the clock of memory 14 and synchronize it with the clock of external devices (e.g., memory testing device 12) that read and write memory.

The storage array 1404 includes at least one bank for storing data. The row decoder 1406 and column decoder 1408 are used to identify the row and column where the data corresponding to the read and/or write instruction is located when the memory 14 receives read and/or write instructions, and to perform read and/or write operations.

The input/output unit 1410 provides a data strobe signal (DQS). When memory 14 receives a read command from an external device, the data strobe signal transmits the corresponding data from memory 14 to the external device. Conversely, when memory 14 receives a write command from an external device, the data strobe signal transmits the corresponding data from the external device to memory 14.

In some embodiments, processor 122 switches memory 14 from an idle state to an enabled state; next, processor 122 sends a delayed phase-locked loop (PLL) reset instruction to memory 14 in the enabled state; then, within a specific time period starting from the sending of the PLL reset instruction, processor 122 sends a read instruction to memory 14; subsequently, processor 122 determines whether reading memory 14 was successful; finally, in response to a failure to read memory 14, processor 122 determines that memory 14 does not meet the fifth-generation double data rate standard; conversely, in response to a successful read of memory 14, processor 122... 122 determines that memory 14 may meet the fifth generation double data rate standard.

In some embodiments, processor 122 sends a delayed phase-locked loop (PLL) reset instruction to memory 14 in an idle state; next, processor 122 switches the first memory bank of memory 14 from an idle state to an enabled state; then, processor 122 sends a delayed PLL reset instruction to memory 14 in an enabled state; subsequently, processor 122 switches the second memory bank of memory 14 from an idle state to an enabled state; next, within a specific time period starting from the sending of the delayed PLL reset instruction, processor 122 sends a read instruction to memory 14; then, processor... 122 determines whether reading memory 14 was successful; finally, in response to a failure to read memory 14, processor 122 determines that memory 14 does not meet the fifth generation double data rate standard; conversely, in response to a successful read of memory 14, processor 122 determines that memory 14 may meet the fifth generation double data rate standard.

In some embodiments, processor 122 sends a delayed phase-locked loop (PLL) reset instruction to memory 14; next, processor 122 sends an enable instruction to memory 14, wherein the first time interval between sending the PLL reset instruction and sending the enable instruction is not less than the PLL cycle; then, processor 122 sends the PLL reset instruction to memory 14 again; subsequently, processor... 122 sends a read instruction to memory 14, wherein the second time interval between sending the delayed phase-locked loop reset instruction and sending the read instruction is less than the delayed phase-locked loop cycle; finally, if the read of memory 14 fails, processor 122 determines that memory 14 does not meet the fifth generation double data rate standard; conversely, if the read of memory 14 succeeds, processor 122 determines that memory 14 may meet the fifth generation double data rate standard.

Please refer to Figure 3, which is a schematic diagram of the memory testing method 20 in some embodiments of this disclosure. The memory testing method 20 includes steps S202, S204, S206, S208, S210, and S212, and is used to determine whether the memory (e.g., memory 14) conforms to the fifth generation double data rate standard. In some embodiments, the memory testing method 20 can be performed by the memory testing device 12 shown in Figure 1.

Specifically, the memory testing method 20 determines whether the memory meets the fifth-generation double data rate standard by sending a delayed phase-locked loop reset command to the memory when the memory is in the enabled state and reading the memory within a certain period of time.

Since memory conforming to the fifth-generation double data rate standard does not support executing delayed phase-locked loop (PLL) reset commands while enabled, if reading the memory fails after sending the LPL reset command, it means the memory supports executing LPL reset commands while enabled. Memory testing method 20 then further determines that the memory does not conform to the fifth-generation double data rate standard. For details on how memory testing method 20 is performed, please refer to the following paragraphs.

In step S202, memory testing method 20 switches the memory from an idle state to an enabled state. In some embodiments, memory testing method 20 sends an enable instruction (e.g., an ACTIVE instruction) to the memory to switch the memory to an enabled state.

It should be noted that the enable instruction is used to switch at least one bank in memory to the enabled state so that the bank that has been switched to the enabled state can be further read and/or written.

In step S204, memory test method 20 sends a delayed phase-locked loop reset instruction to the memory in the enabled state.

It should be noted that the delayed phase-locked loop reset instruction is used to synchronize the clock of the memory with the clock of an external device (e.g., memory test device 12), so that when the memory is subsequently read and/or written, the data selection signal provided by the memory's input/output unit (e.g., input/output unit 1410) can correctly transmit data on the same clock as the external device.

Therefore, in step S204, after the memory receives the delay phase-locked loop reset command, it resets the delay phase-locked loop circuit (e.g., delay phase-locked loop circuit 1402) and synchronizes the clock of the memory with the clock of the external device (e.g., memory test device 12).

It is important to note that after the memory receives the delayed phase-locked loop (PLL) reset command, at least the corresponding PLL cycle (tDLLK) interval for the memory specification is required before the memory can proceed with functions that require PLL circuitry participation, such as read and write operations. The PLL cycle is the time required for the memory to complete the PLL reset.

For example, under the fifth-generation double data rate standard, with a memory data transfer rate of 4800 megabits per second (Mbps), the memory's delay phase-locked loop (PLL) cycle is approximately 638.976 nanoseconds. This means that after the memory receives a PLL reset command, it takes several hundred nanoseconds before it can execute a specific function.

In step S206, memory testing method 20 sends a read instruction to the memory within a specific time period starting from the transmission of the delayed phase-locked loop reset instruction. In some embodiments, the specific time is no more than the memory's delayed phase-locked loop cycle. Further in step S208, memory testing method 20 determines whether the read was successful.

It should be noted that the read instruction is used to read data from at least one library in the memory. After the memory receives the read instruction, the memory's output/input unit provides a data selection signal to transmit the corresponding data.

After the memory receives the delayed phase-locked loop (PLL) reset command in step S204, if the memory supports executing the PLL reset command in the enabled state, the PLL will be reset. However, before a sufficient duration (i.e., the PLL cycle) has elapsed, a read command is received in step S206. At this time, the clock of the data selection signal provided by the output/input unit is not synchronized with the external clock, making it impossible for the data selection signal to be read according to the external clock (e.g., memory test device 12), causing memory test method 20 to fail to read the memory.

Conversely, if the memory does not support executing the delayed phase-locked loop (PLL) reset command while enabled, the PLL will not be reset after receiving the PLL reset command in step S204. Then, after receiving the read command in step S206, the output/input unit can provide a data selection signal on the correct clock, enabling memory test method 20 to successfully read the memory.

Therefore, in step S210, in response to the memory test method 20 failing to read, the memory test method 20 determines that the memory does not meet the fifth generation double data rate standard; conversely, in step S212, in response to the memory test method 20 successfully reading, the memory test method 20 determines that the memory may meet the fifth generation double data rate standard.

Please refer to Figure 4, which is a schematic diagram of the memory testing method 30 in some embodiments of this disclosure. The memory testing method 30 includes steps S302, S304, S306, S308, S310, S312, S314, and S316, and is used to determine whether the memory (e.g., memory 14) conforms to the fifth generation double data rate standard. In some embodiments, the memory testing method 30 can be performed by the memory testing device 12 shown in Figure 1.

Similarly, memory testing method 30 determines whether the memory meets the fifth-generation double data rate standard by sending a delayed phase-locked loop reset command to the memory when the memory is in the enabled state and reading the memory within a certain period of time.

Since memory conforming to the fifth-generation double data rate standard does not support executing delayed phase-locked loop (PLL) reset commands while enabled, if reading the memory fails after sending the LPL reset command, it means the memory supports executing LPL reset commands while enabled. Memory testing method 30 then further determines that the memory does not conform to the fifth-generation double data rate standard. For details on how memory testing method 30 performs the test, please refer to the following paragraphs.

In step S302, the memory testing method 30 sends a delay phase-locked loop reset command to the memory in the idle state. Step S302 is used to initialize the memory. The memory testing method 30 first resets the delay phase-locked loop circuit (e.g., delay phase-locked loop circuit 1402) in the idle state of the memory to synchronize the clock of the memory with the clock of the external device (e.g., memory testing device 12) to eliminate other factors (e.g., the clock of the memory is not synchronized with the clock of the external device) that may cause subsequent steps to fail to read the memory, thereby affecting the test results of the memory testing method 30.

Next, in step S304, the memory testing method 30 switches the first library of the memory from an idle state to an enabled state. In some embodiments, the memory storage array (e.g., storage array 1404) contains multiple libraries, and in step S304, the memory testing method 30 switches one of the libraries (i.e., the first library) of the memory from an idle state to an enabled state. In some embodiments, the memory testing method 30 transmits an instruction to enable one of the libraries in the memory (e.g., an ACTIVE BANK 1 instruction) to the memory, switching one of the libraries (i.e., the first library) of the memory to an enabled state. In some embodiments, the time interval between sending the delayed phase-locked loop (PLL) reset command in step S302 and sending the enable command in step S304 in memory testing method 30 is not less than the delayed PLL cycle. In other words, after sending the delayed PLL reset command, memory testing method 30 waits at least the duration of the delayed PLL cycle before sending the enable command to ensure that the memory completes the delayed PLL reset.

According to the specifications of the fifth generation double data rate standard, the delayed phase-locked loop reset instruction cannot be executed as long as one of the libraries in the memory is in an enabled state. Therefore, in step S304, the memory test method 30 switches one of the libraries in the memory to an enabled state to meet the conditions of the test environment.

Next, in step S306, memory testing method 30 sends a delayed phase-locked loop reset instruction to the memory in the enabled state. It should be noted that step S306 of memory testing method 30 is the same as step S204 of memory testing method 20, and will not be described again for the sake of simplicity.

Subsequently, in step S308, the memory testing method 30 switches the second library of the memory from an idle state to an enabled state. In some embodiments, similar to step S304, in step S308, the memory testing method 30 switches another library in the memory (i.e., the second library), which is different from the first library, from an idle state to an enabled state. In some embodiments, the memory testing method 30 sends an instruction to enable the second library of the memory (e.g., an ACTIVE BANK 0 instruction) to the memory, switching the second library in the memory to an enabled state.

Step S308 is a memory testing method 30. In order to avoid other factors (such as the first library being switched to an idle state) affecting the test results, the second library is switched to an enabled state so that the second library can execute read instructions.

Next, in step S310, the memory testing method 30 sends a read instruction to the memory within a specific time period starting from the transmission of the delayed phase-locked loop reset instruction. Further, in step S312, the memory testing method 30 determines whether the read was successful. In some embodiments, the specific time is less than the memory's delayed phase-locked loop cycle. It should be noted that step S310 of memory testing method 30 is the same as step S208 of memory testing method 20, and step S312 of memory testing method 30 is similar to step S210 of memory testing method 20. For the sake of brevity, the following paragraphs will describe the differences between memory testing method 30 and memory testing method 20.

In some embodiments, the read instruction is used to read data from the second library. Since the second library has been switched to the enabled state in step S308, the memory test method 30 can read the second library to obtain the read result.

It is important to note that after the memory receives the enable command, at least the row-to-column delay (RAS to CAS delay, also known as tRCD) of the corresponding memory specification must elapse before the memory can be read and/or written. The row-to-column delay is the time required for the memory to complete the transition to the enabled state.

For example, under the fifth-generation double data rate standard, with a memory data transfer rate of 4800 megabits per second (Mbps), the row-to-column latency of memory is approximately 14.166~17.5 nanoseconds (far less than the hundreds of nanoseconds required to delay the phase-locked loop cycle). This means that after the memory receives an enable command, it takes approximately tens of nanoseconds before the corresponding library can be read and/or written.

Therefore, in some embodiments, from the time the memory test method 30 sends the enable second library instruction in step S308 to the time the memory test method 30 sends the read instruction in step S310, there must be at least a row-to-column delay (RAS to CAS delay, tRCD), where the RAS to CAS delay is less than a specific time, i.e., less than the delay phase-locked loop cycle. Therefore, in step S310, the memory test method 30 can still send the read instruction to the memory within a specific time.

Finally, similar to step S210 of memory testing method 20, in step S314, when memory testing method 30 fails to read, it is determined that the memory does not meet the fifth generation double data rate standard; conversely, similar to step S212 of memory testing method 20, in step S316, when memory testing method 30 successfully reads, it is determined that the memory may meet the fifth generation double data rate standard.

In summary, the memory testing device 12, memory testing methods 20 and 30 provided in this disclosure can determine whether the memory conforms to the fifth generation double data rate standard by sending a delay phase-locked loop reset command to the memory in the enabled state. This provides an effective and fast memory detection method to test whether the memory does not conform to the fifth generation double data rate standard, and supports resetting the delay phase-locked loop in the enabled state.

Although several embodiments have been detailed above as examples, the memory testing method, memory testing apparatus, and non-transient computer-readable storage medium disclosed herein can also be implemented by other systems, hardware, software, storage media, or combinations thereof. Therefore, the scope of protection of this disclosure should not be limited to the specific implementations described in the embodiments disclosed herein, but should be determined by the scope of the appended patent applications.

It will be apparent to those skilled in the art to which this disclosure pertains that various modifications and variations can be made to the structure of this disclosure without departing from its scope or spirit. In view of the foregoing, the scope of protection of this disclosure also covers modifications and variations made within the scope of the appended patent applications.

12: Memory Testing Device 122: Processor 14: Memory 1402: Delay Phase-Locked Loop Circuit 1404: Memory Array 1406: Row Decoder 1408: Column Decoder 1410: Input/Output Unit 20: Memory Testing Method S202~S212: Steps 30: Memory Testing Method S302~S316: Steps

To make the above and other objects, features, advantages and embodiments of this disclosure more apparent, the accompanying drawings are explained as follows: Figure 1 is a schematic diagram of the memory testing apparatus and memory in some embodiments of this disclosure; Figure 2 is a schematic diagram of the memory in some embodiments of this disclosure; Figure 3 is a flowchart of the memory testing method in some embodiments of this disclosure; and Figure 4 is a flowchart of another memory testing method in some embodiments of this disclosure.

20: Memory Testing Methods

S202~S212: Steps

Claims (10)

A memory testing method, applicable to an electronic device, comprising: transmitting a delayed phase-locked loop (PLL) reset command to a memory in an enabled state; transmitting a read command to the memory within a specific time period from the date of sending the PLL reset command; and determining that the memory does not meet a fifth-generation double data rate (DFR) standard if a read result corresponding to the read command fails. The memory testing method as described in claim 1, further comprising, before switching the memory to the enabled state: transmitting the delayed phase-locked loop (PLL) reset command to the memory in an idle state, wherein the memory is switched from the idle state to the enabled state only after a specific time has elapsed since the PLL reset command was sent to the memory in the idle state. The memory testing method as described in claim 1, wherein the read instruction is used to read a library of the memory, and the memory testing method further includes, before sending the read instruction to the memory: switching the library of the memory from an idle state to an enabled state. The memory testing method as described in claim 3, wherein switching the library of the memory to the enabled state is accomplished by sending an enable library instruction to the memory, and at least one row-to-column delay time, less than the specified time, is elapsed between the sending of the enable library instruction and the sending of the read instruction. The memory testing method as described in claim 1, wherein the specific time is a delayed phase-locked loop cycle. A memory testing method, applicable to an electronic device, comprising: transmitting a delayed phase-locked loop (PLL) reset command to a memory; transmitting an enable command to the memory, wherein a first time interval between transmitting the delayed PLL reset command and transmitting the enable command is not less than a delayed PLL cycle; transmitting the delayed PLL reset command to the memory again; transmitting a read command to the memory, wherein a second time interval between transmitting the delayed PLL reset command and transmitting the read command is less than the delayed PLL cycle; and If a read operation corresponding to the read instruction fails, it is determined that the memory does not meet a fifth-generation double data rate standard. A memory testing apparatus for testing a memory includes: a processor for performing the following operations: transmitting a delayed phase-locked loop (PLL) reset command to the memory in an enabled state; transmitting a read command to the memory within a specific time period from the date of sending the PLL reset command; and determining that the memory does not meet a fifth-generation double data rate (DFR) standard if a read operation corresponding to the read command fails. The memory testing apparatus as described in claim 7, wherein before switching the memory to the enabled state, the processor further performs the following operations: Sends the delayed phase-locked loop (PLL) reset command to the memory in an idle state, wherein the memory is switched from the idle state to the enabled state only after a specific time has elapsed since the PLL reset command was sent to the memory in the idle state. The memory testing apparatus as described in claim 7, wherein the read instruction is used to read a library of the memory, and before sending the read instruction to the memory, the processor further performs the following operations: Switching the library of the memory from an idle state to an enabled state. A non-transient computer-readable storage medium having at least one instruction stored thereon, which, when executed by a processing unit, performs a memory testing method comprising the steps of: transmitting a delayed phase-locked loop (PLL) reset instruction to a memory in an enabled state; transmitting a read instruction to the memory within a specific time period from the date of sending the PLL reset instruction; and determining that a read result corresponding to the read instruction fails, determining that the memory does not conform to a fifth-generation double data rate standard.