TWI864740B - Memory testing method, memory testing device and non-transitory computer-readable storage medium - Google Patents

Abstract

A memory testing method comprises following steps. A bank of the memory is switched from an idle state to an active state. A delay-locked loop reset instruction is transmitted to the memory which is at the active state. A read instruction is transmitted to the memory, wherein a time calculated from the transmitting of the delay-locked loop reset instruction to the transmitting of the read instruction is less than a specific time. A reading result of the read instruction is received. In response to the reading result is fail, the memory is determined not to meet a double data rate fifth-generation standard.

Description

Memory testing method, memory testing device, and non-transitory computer-readable storage medium

The present disclosure relates to a memory testing method, and more particularly to a memory testing method for determining whether a memory complies with the fifth generation double data rate standard.

With the development of memory component technology, in order to distinguish the storage efficiency and speed of memory, the industry and academic institutions have set many common standards. If the product meets certain specifications (such as storage capacity per unit area) or performance (such as read and write efficiency), it can obtain the corresponding certification mark. In order to promote or meet customer requirements, memory manufacturers usually refer to the public standards for hardware design.

The present disclosure provides a memory testing method applicable to electronic devices. The memory testing method includes: switching a first bank of a memory from an idle state to an enabled state; transmitting a delayed phase-locked loop reset instruction to the memory in the enabled state; transmitting a read instruction to the memory within a specific time counted from the transmission of the delayed phase-locked loop reset instruction; receiving a read result related to the read instruction; and in response to the read result being a failure, determining that the memory does not comply with the fifth-generation double data rate standard.

The present disclosure also provides a memory testing method applicable to electronic devices. The memory testing method includes: sending a delayed phase-locked loop reset instruction to the memory; sending an enable instruction to the memory, wherein a first time interval between sending the delayed phase-locked loop reset instruction and sending the enable instruction is not less than a delayed phase-locked loop cycle; and The method comprises the steps of: transmitting a delayed phase-locked loop reset instruction to the memory for the second time; transmitting a read instruction to the memory, wherein a second time interval between transmitting the delayed phase-locked loop reset instruction again and transmitting the read instruction is less than the delayed phase-locked loop cycle; and in response to a read result being a failure, determining that the memory does not comply with the fifth generation double data rate standard.

The present disclosure also provides a memory test device for testing a memory, the memory test device includes a processor, wherein the processor is used to perform the following operations: switching a first bank of the memory from an idle state to an enabled state; sending a delayed phase-locked loop reset instruction to the memory in the enabled state; sending a read instruction to the memory within a specific time counted from the sending of the delayed phase-locked loop reset instruction; receiving a read result related to the read instruction; and in response to the read result being a failure, determining that the memory does not comply with the fifth-generation double data rate standard.

The present disclosure also provides a non-transitory computer-readable storage medium having at least one instruction stored thereon. When a processing unit executes the instructions, the instructions execute the memory testing method.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the disclosure as claimed.

In order to make the description of the present disclosure more detailed and complete, reference may be made to the attached drawings and various embodiments described below, in which the same numbers in the drawings represent the same or similar elements.

Please refer to FIG. 1, which is a schematic diagram of a memory test device 12 and a memory 14 in some embodiments of the present disclosure. As shown in FIG. 1, the memory test device 12 includes a processor 122 and is coupled to the memory 14. The memory test device 12 is used to determine whether the memory 14 complies with the fifth generation double data rate standard.

Current memory standards, such as the double data rate fifth-generation (DDR5) standard developed by the Joint Electron Devices Engineering Council (JEDEC), do not allow for specific operating methods.

For example, a memory that complies with the DDR5 standard can only execute certain instructions in the activated state and the idle state. For example, the delay-locked loop reset (DLL Reset) instruction cannot be executed in the activated state.

However, some memory products on the market do not comply with the fifth generation double data rate standard and support specific operating modes, which will increase the flexibility of memory product design and further improve its performance. In order to determine whether the memory product complies with the operating restrictions of the relevant standards, competing manufacturers need to test it. However, the current known technology lacks an effective and fast memory detection method to test whether the memory product does not comply with the fifth generation double data rate standard and supports a specific operating mode. In the present disclosure, the memory test device 12 can provide a convenient and efficient way to detect whether the memory 14 complies with the fifth generation double data rate standard.

In some embodiments, the processor 122 may include a central processing unit (CPU), multiple processors, a distributed processing system, an application specific integrated circuit (ASIC), and/or an appropriate computing unit.

Please refer to Figure 2, which is a schematic diagram of the memory 14 in some embodiments of the present disclosure. The memory 14 includes a delay-locked loop (DLL) circuit 1402, a storage array 1404, a row decoder 1406, a column decoder 1408, and an input/output unit 1410. In one embodiment, the memory 14 can be a synchronous dynamic random access memory (SDRAM).

The delayed phase-locked loop circuit 1402 is used to calibrate the data output and input clock signals in the memory 14 to stabilize the clock of the memory 14 and synchronize it with the clock of an external device (e.g., memory test device 12) that reads and writes the memory.

The storage array 1404 includes at least one bank and is used to store data. When the memory 14 receives a read and/or write instruction, the row decoder 1406 and the column decoder 1408 are used to confirm the row and column where the data corresponding to the read and/or write instruction is located, and perform reading and/or writing.

The input/output unit 1410 is used to provide a data strobe signal (DQS). When the memory 14 receives a read command from an external device, the data strobe signal transmits the corresponding data from the memory 14 to the external device. Conversely, when the memory 14 receives a write command from an external device, the data strobe signal transmits the corresponding data from the external device to the memory 14.

In some embodiments, the processor 122 switches the memory 14 from an idle state to an enabled state; next, the processor 122 sends a delayed phase-locked loop reset instruction to the memory 14 in the enabled state; then, the processor 122 sends a read instruction to the memory 14 within a specific time from the sending of the delayed phase-locked loop reset instruction; thereafter, the processor 122 determines whether the read of the memory 14 is successful; finally, in response to a failure to read the memory 14, the processor 122 determines that the memory 14 does not comply with the fifth generation double data rate standard; conversely, in response to a success to read the memory 14, the processor 122 122 determines that the memory 14 complies with the fifth generation double data rate standard.

In some embodiments, the processor 122 transmits a delayed phase-locked loop reset instruction to the memory 14 in an idle state; then, the processor 122 switches the first bank of the memory 14 from the idle state to the enabled state; then, the processor 122 transmits a delayed phase-locked loop reset instruction to the memory 14 in the enabled state; thereafter, the processor 122 switches the second bank of the memory 14 from the idle state to the enabled state; then, the processor 122 transmits a read instruction to the memory 14 within a specific time from the transmission of the delayed phase-locked loop reset instruction; then, the processor 122 determines whether the read of memory 14 is successful; finally, in response to a failure to read memory 14, processor 122 determines that memory 14 does not comply with the fifth generation double data rate standard; conversely, in response to a success to read memory 14, processor 122 determines that memory 14 complies with the fifth generation double data rate standard.

In some embodiments, the processor 122 sends a delayed phase-locked loop reset instruction to the memory 14; then, the processor 122 sends an enable instruction to the memory 14, wherein the first time interval between sending the delayed phase-locked loop reset instruction and sending the enable instruction is not less than the delayed phase-locked loop cycle; then, the processor 122 sends the delayed phase-locked loop reset instruction to the memory 14 again; thereafter, the processor 122 transmits a read instruction to the memory 14, wherein the second time interval between transmitting the delayed phase-locked loop reset instruction again and transmitting the read instruction is less than the delayed phase-locked loop cycle; finally, in response to a failure in reading the memory 14, the processor 122 determines that the memory 14 does not comply with the fifth generation double data rate standard; conversely, in response to a success in reading the memory 14, the processor 122 determines that the memory 14 complies with the fifth generation double data rate standard.

Please refer to FIG. 3, which is a schematic diagram of a memory testing method 20 in some embodiments of the present disclosure. The memory testing method 20 includes steps S202, S204, S206, S208, S210, and S212, and is used to determine whether a memory (e.g., memory 14) complies with the fifth generation double data rate standard. In some embodiments, the memory testing method 20 can be executed by the memory testing device 12 shown in FIG. 1.

Specifically, the memory testing method 20 sends a delayed phase-locked loop reset command to the memory when the memory is in an enabled state, and reads the memory within a certain period of time to determine whether it complies with the fifth-generation double data rate standard.

Since a memory that complies with the DDR5 standard does not support the execution of the delayed PLL reset instruction in an enabled state, if the memory reading fails after the delayed PLL reset instruction is sent, it means that the memory supports the execution of the delayed PLL reset instruction in an enabled state, and the memory test method 20 further determines that the memory does not comply with the DDR5 standard. For details on how the memory test method 20 performs the test, please refer to the following paragraphs.

In step S202, the memory testing method 20 switches the memory from the idle state to the enabled state. In some embodiments, the memory testing method 20 sends an enable command (eg, an ACTIVE command) to the memory to switch the memory to the enabled state.

It should be noted that the enable instruction is used to switch at least one bank in the memory to an enabled state, so that the bank switched to the enabled state can be further read and/or written.

In step S204, the memory testing method 20 sends a delayed phase-locked loop reset command to the memory in the enabled state.

It should be noted that the delayed phase-locked loop reset instruction is used to synchronize the clock of the memory with the clock of an external device (e.g., memory test device 12) so that when the memory is read and/or written next, the data selection signal provided by the input/output unit of the memory (e.g., input/output unit 1410) can correctly transmit data at the same clock as the external device.

Therefore, in step S204, after receiving the delay phase-locked loop reset instruction, the memory resets the delay phase-locked loop circuit (eg, delay phase-locked loop circuit 1402) to synchronize the clock of the memory with the clock of the external device (eg, memory test device 12) again.

It should be noted that after the memory receives the delay phase-locked loop reset command, it must wait for at least the delay phase-locked loop cycle (tDLLK) of the corresponding memory specification before the memory can further execute functions that require the participation of the delay phase-locked loop circuit, such as reading and writing. The delay phase-locked loop cycle is the time required for the memory to complete the reset of the delay phase-locked loop.

For example, under the fifth generation double data rate standard, with a memory data transmission speed of 4800 megabits per second (Mbps), the memory delay phase-locked loop cycle is about 638.976 nanoseconds. This means that after the memory receives a delay phase-locked loop reset instruction, it will take about hundreds of nanoseconds before it can execute a specific function.

In step S206, the memory test method 20 sends a read command to the memory within a specific time from the sending of the delayed phase-locked loop reset command. In some embodiments, the specific time is no longer than the delayed phase-locked loop cycle of the memory. Further in step S208, the memory test method 20 determines whether the read is successful.

It should be noted that the read command is used to read data from at least one bank in the memory. After the memory receives the read command, the output/input unit of the memory provides a data strobe signal to transmit the corresponding data.

After the memory receives the delay phase-locked loop reset instruction in step S204, if the memory supports executing the delay phase-locked loop reset instruction in the enabled state, the delay phase-locked loop will be reset, but the read instruction is received in step S206 before a sufficient time (i.e., delay phase-locked loop cycle) has passed. At this time, the data strobe signal clock provided by the output/input unit is not synchronized with the external clock, so that the data strobe signal cannot be read according to the clock of the external (e.g., memory test device 12), causing the memory test method 20 to fail to read the memory.

In contrast, if the memory does not support the execution of the delay phase-locked loop reset instruction in the enabled state, the delay phase-locked loop reset instruction will not be executed after receiving the delay phase-locked loop reset instruction in step S204. Further, after receiving the read instruction in step S206, the output/input unit can provide a data selection signal at the correct clock, so that the memory test method 20 can successfully read the memory.

Therefore, in step S210, in response to the memory test method 20 reading failure, the memory test method 20 determines that the memory does not meet the fifth-generation double data rate standard; in contrast, in step S212, in response to the memory test method 20 reading success, the memory test method 20 determines that the memory meets the fifth-generation double data rate standard.

Please refer to FIG. 4, which is a schematic diagram of a memory testing method 30 in some embodiments of the present disclosure. The memory testing method 30 includes steps S302, S304, S306, S308, S310, S312, S314 and S316, and is used to determine whether a memory (e.g., memory 14) complies with the fifth generation double data rate standard. In some embodiments, the memory testing method 30 can be executed by the memory testing device 12 shown in FIG. 1.

Similarly, the memory testing method 30 sends a delayed phase-locked loop reset command to the memory when the memory is in an enabled state, and reads the memory within a certain period of time to determine whether it complies with the fifth-generation double data rate standard.

Since a memory that complies with the DDR5 standard does not support the execution of the delayed PLL reset instruction in an enabled state, if the memory reading fails after the delayed PLL reset instruction is sent, it means that the memory supports the execution of the delayed PLL reset instruction in an enabled state, and the memory test method 30 further determines that the memory does not comply with the DDR5 standard. For details on how the memory test method 30 performs the test, please refer to the following paragraphs.

In step S302, the memory test method 30 transmits a delay phase-locked loop reset instruction to the memory in the idle state. Step S302 is used to initialize the memory. The memory test method 30 first resets the delay phase-locked loop circuit (e.g., delay phase-locked loop circuit 1402) of the memory in the idle state, and synchronizes the clock of the memory with the clock of the external device (e.g., memory test device 12) to eliminate other factors (e.g., the clock of the memory is not synchronized with the clock of the external device) that cause the subsequent step of reading the memory to fail, thereby affecting the test result of the memory test method 30.

Next, in step S304, the memory testing method 30 switches the first bank of the memory from the idle state to the enabled state. In some embodiments, the storage array of the memory (e.g., storage array 1404) includes a plurality of banks. In step S304, the memory testing method 30 switches one of the banks (i.e., the first bank) of the memory from the idle state to the enabled state. In some embodiments, the memory testing method 30 transmits an instruction to enable one of the banks in the memory (e.g., ACTIVE BANK 1 instruction) to the memory, switching one of the banks in the memory (i.e., the first bank) to the enabled state. In some embodiments, the time interval between the memory test method 30 sending the delayed phase-locked loop reset instruction in step S302 and sending the enable instruction in step S304 is not less than the delayed phase-locked loop cycle. In other words, after the memory test method 30 sends the delayed phase-locked loop reset instruction, at least the length of the delayed phase-locked loop cycle has passed before sending the enable instruction to ensure that the memory completes resetting the delayed phase-locked loop.

According to the specification of the fifth generation double data rate standard, as long as one of the banks in the memory is in the enabled state, the delayed phase-locked loop reset instruction cannot be executed. Therefore, in step S304, the memory test method 30 switches one of the banks of the memory to the enabled state to meet the conditions of the test environment.

Next, in step S306, the memory testing method 30 sends a delayed phase-locked loop reset instruction to the enabled memory. It should be noted that step S306 of the memory testing method 30 is the same as step S204 of the memory testing method 20, and will not be described again for brevity.

Thereafter, in step S308, the memory testing method 30 switches the second bank of the memory from the idle state to the enabled state. In some embodiments, similar to step S304, in step S308, the memory testing method 30 switches another bank (i.e., the second bank) in the memory that is different from the first bank from the idle state to the enabled state. In some embodiments, the memory testing method 30 transmits an instruction (e.g., ACTIVE BANK 0 instruction) to enable the second bank of the memory to the memory, switching the second bank in the memory to the enabled state.

Step S308 is that the memory testing method 30 switches the second bank to an enabled state to enable the second bank to execute a read instruction in order to prevent other factors (such as the first bank being switched to an idle state) from affecting the test result.

Next, in step S310, the memory test method 30 sends a read command to the memory within a specific time from the sending of the delayed phase-locked loop reset command. Further in step S312, the memory test method 30 determines whether the read is successful. In some embodiments, the specific time is less than the delayed phase-locked loop cycle of the memory. It should be noted that step S310 of the memory testing method 30 is the same as step S208 of the memory testing method 20, and step S312 of the memory testing method 30 is similar to step S210 of the memory testing method 20. For the sake of brevity, the following paragraphs will describe the differences between the memory testing method 30 and the memory testing method 20.

In some embodiments, the read instruction is an instruction for reading data from the second library. Since the second library has been switched to an enabled state in step S308, the memory testing method 30 can read the second library to obtain a read result.

It should be noted that after the memory receives the enable command, it takes at least the time interval of the row-to-column delay (RAS to CAS delay, also known as tRCD) corresponding to the memory specification before the memory can be further read and/or written, where the row-to-column delay time is the time required for the memory to complete the switch to the enabled state.

For example, under the fifth generation double data rate standard, with a memory data transmission speed of 4800 megabits per second (Mbps), the row-to-row delay of the memory is about 14.166~17.5 nanoseconds (much shorter than the several hundred nanoseconds required for the delay phase-locked loop cycle). This means that after the memory receives an enable command, it takes about tens of nanoseconds for the bank corresponding to the enable command to be read and/or written.

Therefore, in some embodiments, there is at least a row-to-column delay time (RAS to CAS delay, tRCD) between the time when the memory test method 30 transmits the enable second library instruction in step S308 and the time when the memory test method 30 transmits the read instruction in step S310, wherein the row-to-column delay time is less than a specific time, i.e., also less than a delay phase-locked loop cycle. Therefore, in step S310, the memory test method 30 is still able to transmit the read instruction to the memory within the specific time.

Finally, similar to step S210 of the memory test method 20, in step S314, when the memory test method 30 fails to read, it is determined that the memory does not comply with the fifth-generation double data rate standard; conversely, similar to step S212 of the memory test method 20, in step S316, when the memory test method 30 succeeds in reading, it is determined that the memory complies with the fifth-generation double data rate standard.

In summary, the memory testing device 12, memory testing methods 20 and 30 provided in the present disclosure can determine whether the memory complies with the fifth generation double data rate standard by sending a delay phase-locked loop reset instruction to the memory in the enabled state, providing an effective and fast memory detection method to test whether the memory does not comply with the fifth generation double data rate standard, and supporting the resetting of the delay phase-locked loop in the enabled state.

Although several embodiments are described in detail above as examples, the memory testing method, memory testing device, and non-transitory computer-readable storage medium proposed in the present disclosure may also be implemented by other systems, hardware, software, storage media, or a combination thereof. Therefore, the protection scope of the present disclosure should not be limited to the specific implementation methods described in the embodiments of the present disclosure, but should be subject to the scope of the attached patent application.

It is obvious to those with ordinary knowledge in the art to which the present disclosure belongs that various modifications and changes can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the protection scope of the present disclosure also covers modifications and changes made within the scope of the attached patent application.

12: Memory test device 122: Processor 14: Memory 1402: Delay phase-locked loop circuit 1404: Storage array 1406: Row decoder 1408: Column decoder 1410: Input/output unit 20: Memory test method S202~S212: Step 30: Memory test method S302~S316: Step

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understandable, the attached drawings are described as follows: Figure 1 is a schematic diagram of a memory testing device and a memory in some embodiments of the present disclosure; Figure 2 is a schematic diagram of a memory in some embodiments of the present disclosure; Figure 3 is a flow chart of a memory testing method in some embodiments of the present disclosure; and Figure 4 is a flow chart of another memory testing method in some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

20: Memory testing method S202~S212: Steps

Claims (10)

A memory testing method is applicable to an electronic device, the memory testing method comprising: switching a first bank of a memory from an idle state to an enabled state; transmitting a delayed phase-locked loop reset instruction to the memory in the enabled state; transmitting a read instruction to the memory within a specific time counted from the transmission of the delayed phase-locked loop reset instruction; receiving a read result related to the read instruction; and in response to the read result being a failure, determining that the memory does not comply with a fifth-generation double data rate standard. The memory testing method as described in claim 1, wherein before switching the memory to the enabled state, the memory testing method further comprises: sending the delayed phase-locked loop reset instruction to the memory in the idle state, wherein the memory is switched from the idle state to the enabled state only after the specific time has passed since the delayed phase-locked loop reset instruction was sent to the memory in the idle state. The memory testing method as described in claim 1, wherein the read instruction is used to read a second bank of the memory, and before sending the read instruction to the memory, the memory testing method further comprises: Switching the second bank of the memory from the idle state to the enabled state. A memory testing method as described in claim 3, wherein the switching of the second bank of the memory to the enabled state is completed by sending an enable second bank instruction to the memory, and there is at least a row-to-row delay time between sending the enable second bank instruction and sending the read instruction, and the row-to-row delay time is less than the specific time. A memory testing method as described in claim 1, wherein the specific time is a delay phase-locked loop cycle. A memory testing method is applicable to an electronic device, the memory testing method comprising: transmitting a delayed phase-locked loop reset instruction to a memory; transmitting an enable instruction to the memory, wherein a first time interval between transmitting the delayed phase-locked loop reset instruction and transmitting the enable instruction is not less than a delayed phase-locked loop cycle; transmitting the delayed phase-locked loop reset instruction again; loop reset command to the memory; sending a read command to the memory, wherein a second time interval between sending the delayed phase-locked loop reset command again and sending the read command is less than the delayed phase-locked loop cycle; and in response to a read result corresponding to the read command being a failure, determining that the memory does not comply with a fifth-generation double data rate standard. A memory test device for testing a memory includes: a processor for performing the following operations: switching a first bank of the memory from an idle state to an enabled state; transmitting a delayed phase-locked loop reset instruction to the memory in the enabled state; transmitting a read instruction to the memory within a specific time from the transmission of the delayed phase-locked loop reset instruction; receiving a read result of the read instruction; and in response to the read result being a failure, determining that the memory does not comply with a fifth-generation double data rate standard. The memory test device as described in claim 7, wherein before switching the memory to the enabled state, the processor further performs the following operation: sending the delayed phase-locked loop reset instruction to the memory in the idle state, wherein the memory is switched from the idle state to the enabled state only after the specific time has passed since the delayed phase-locked loop reset instruction was sent to the memory in the idle state. A memory testing device as described in claim 7, wherein the read instruction is used to read a second bank of the memory, and before sending the read instruction to the memory, the processor further performs the following operation: switching the second bank of the memory from the idle state to the enabled state. A non-transitory computer-readable storage medium has at least one instruction stored thereon. When a processing unit executes the instructions, the instructions execute a memory test method. The memory test method includes the following steps: switching a first bank of a memory from an idle state to an enabled state; sending a delayed phase-locked loop Reset command to the memory in the enabled state; send a read command to the memory within a specific time from sending the delayed phase-locked loop reset command; receive a read result related to the read command; and in response to the read result being a failure, determine that the memory does not comply with a fifth-generation double data rate standard.

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