TWI906071B - Row decoder circuit - Google Patents

Abstract

A row decoder circuit adapted to a memory device is provided. The row decoder circuit includes a pre-decoder, a plurality of decoders and a mapping control circuit. The pre-decoder is configured to receive row address information and decode the row address information to provide a row select signal group. The plurality of decoders respectively correspond to a plurality of raw address ranges. The mapping control circuit is configured to obtain a selected raw address range according to the row select signal group, and cause the decoder whose corresponding row address range is the same as the selected raw address range to output a word line signal. The mapping control circuit reorders the row address ranges corresponding to the decoders according to a verification data.

Description

Serial decoder circuit

This invention relates to a decoder circuit, and more particularly to a column decoder circuit.

As memory manufacturing technology advances, memory density and die area increase, leading to a higher failure rate per die. It's virtually impossible for all memory cells or blocks within a memory product to be 100% undamaged. Therefore, current technologies primarily utilize row/col redundancy techniques and error correction code (ECC) techniques to repair damaged memory cells. However, these techniques have limited repair capabilities and cannot completely repair some heavily damaged memory devices (chips). Because the location of the damage is random, these partially damaged memory devices cannot be shipped as normal products, reducing the product yield.

This invention provides a serial decoder circuit that enables the use of partially damaged memory devices.

The column decoder circuit of this invention is applicable to memory devices and includes a pre-decoder, multiple decoders, and a mapping control circuit. The pre-decoder is configured to receive column address information and decode the column address information to provide a column selection signal set. Multiple decoders sequentially correspond to multiple column address ranges. The mapping control circuit is coupled to the pre-decoder and the decoders and is configured to obtain a selected column address range based on the column selection signal set, and to output character line signals from decoders whose corresponding column address range matches the selected column address range. The mapping control circuit reorders the column address ranges corresponding to the decoders based on verification data.

Based on the above, by reordering the column address range corresponding to the decoder, the column decoder circuit of this invention can skip damaged memory blocks during mapping, allowing the memory device to function normally. This ensures that partially damaged memory devices remain usable, and also increases product yield and ease of use.

To make the above features and advantages of this invention more apparent and understandable, specific examples are given below, and detailed explanations are provided in conjunction with the accompanying drawings.

Referring to Figure 1, the column decoder circuit 100 of this embodiment is applicable, for example, to memory devices conforming to standards such as hybrid memory cube (HMC), high bandwidth memory (HBM), double data rate (DDR), or low power double data rate (LPDDR). The column decoder circuit 100 includes a pre-decoder 110, decoders 120_0 to 120_11, and a mapping control circuit 130. The pre-decoder 110 receives the column address information RA of the memory cell to be accessed. The column address information RA may, for example, consist of 13 bits. The pre-decoder 110 decodes the column address information RA to provide a column selection signal group SELG. The first part P1 of the column selection signal group SELG corresponds to the column address of the high-order part, including the first column selection signal RSGSEL0[3:0] and the second column selection signal RSGSEL1[2:0]. The second part P2 of the column selection signal group SELG corresponds to the column address of the low-order part, including the column selection signals RMWSEL0[7:0], RMWSEL1[3:0], RMWSEL2[2:0] and RFXSEL[7:0]. The pre-decoder 110 transmits the first part P1 of the column selection signal group SELG to the mapping control circuit 130, and transmits the second part P2 of the column selection signal group SELG to each decoder 120_0~120_11.

Decoders 120_0 to 120_11 correspond sequentially to column address ranges RSG0 to RSG11. Column address ranges RSG0 to RSG11 represent the initial default column address ranges of the 12 memory blocks opened by decoders 120_0 to 120_11 in the memory device. For example, assuming the total column address range provided by the above 12 memory blocks is 0 to 8191, the column address ranges RSG0 to RSG11 are shown in Table 1 below. RSG0 0~687 RSG1 688~1375 RSG2 1376~2047 RSG3 2048~2735 RSG4 2736~3423 RSG5 3424~4095 RSG6 4096~4783 RSG7 4784~5471 RSG8 5472~6143 RSG9 6144~6831 RSG10 6832~7519 RSG11 7250~8191 Table 1

If all 12 memory blocks are undamaged (all are usable), decoders 120_0~120_11 can output character line signals SWL0~SWL11 to the 12 memory blocks respectively to access memory cells whose column addresses are within the column address range RSG0~RSG11.

The mapping control circuit 130 is coupled to the pre-decoder 110 and the decoders 120_0 to 120_11. The mapping control circuit 130 can obtain the selected column address range according to the column selection signal group SELG, and make the decoder output enable level (e.g., high logic level) word line signal of the decoder whose corresponding column address range in decoders 120_0 to 120_11 is the same as the selected column address range.

Specifically, the mapping control circuit 130 analyzes and decodes the signal of the first part P1 of the column selection signal group SELG to obtain the selected column address range of the memory cell to be accessed. At this time, the decoders in decoders 120_0~120_11 whose corresponding column address range is the same as the selected column address range can output the corresponding word line signal according to the second part P2 of the column selection signal group SELG. Furthermore, when the selected column address range is equal to the column address range RSG0, the mapping control circuit 130 causes decoder 120_0 to output the enable level word line signal SWL0 according to the second part P2 of the column selection signal group SELG. When the selected column address range is equal to the column address range RSG1, the mapping control circuit 130 causes the decoder 120_1 to output the enable level word line signal SWL1 according to the second part P2 of the column selection signal group SELG, and so on.

In this embodiment, the mapping control circuit 130 can also receive verification data DV. The verification data DV is, for example, data obtained during the chip probing (CP) stage. The mapping control circuit 130 can determine the location of damaged memory cells or bad memory blocks based on the verification data DV.

Furthermore, the mapping control circuit 130 can generate verification signals SDV0 to SDV11 based on the multiple bit values that constitute the verification data DV. When a verification signal is at a high logic level (logic value 1), it indicates that the corresponding memory block is damaged because faulty memory cells cannot be completely repaired. When a verification signal is at a low logic level (logic value 0), it indicates that the corresponding memory block can be completely repaired without faulty memory cells. Furthermore, when the verification signal SDV0 is at a high logic level (logic value 1), it indicates that the memory block opened by decoder 120_0 is damaged; when the verification signal SDV1 is at a high logic level (logic value 1), it indicates that the memory block opened by decoder 120_1 is damaged, and so on.

When a corrupt memory block exists among the 12 memory blocks opened by decoders 120_0 to 120_11, the mapping control circuit 130 can reorder the column address ranges corresponding to decoders 120_0 to 120_11 according to the verification data DV. For example, as shown in Figure 2, when the memory block opened by decoder 120_1 is a corrupt memory block, the verification signal SDV1 is at a high logic level (logic value 1). Therefore, the mapping control circuit 130 can disable the decoder 120_1 as a bad memory block decoder based on the high logic level verification signal SDV1.

At this time, in order for the memory device to function properly, the mapping control circuit 130 can also shift the column address range corresponding to decoders 120_2 to 120_11, which are decoders of the faulty memory block, from column address range RSG2 to RSG11 to column address range RSG1 to RSG10 according to the verification signals SDV0 to SDV11. This allows decoder 120_2 to replace decoder 120_1 and correspond to column address range RSG1, so that the memory block opened by decoder 120_1 can no longer be mapped.

Similarly, each decoder 120_3~120_11 will replace the previous decoder and correspond to the column address range originally corresponding to the previous decoder.

Thus, the column decoder circuit 100 of this embodiment can skip damaged memory blocks when performing mapping, thereby allowing some damaged memory devices to remain usable.

It should be noted that although this embodiment uses 12 decoders 120_0~120_11 capable of opening 12 memory blocks for illustration, the present invention is not limited thereto. Those skilled in the art can, based on the teachings of the present invention, extrapolate the number of memory blocks and decoders to fewer or more as needed.

The following embodiment illustrates the implementation of the mapping control circuit. The mapping control circuit 300 of this embodiment is applicable to situations where a memory block contains damaged memory cells, requiring a reordering of the column address ranges corresponding to decoders 400_0 to 400_11. The mapping control circuit 300 includes a latch circuit 310, a first logic circuit 320, a second logic circuit 330, a multiplexing circuit 340, and a third logic circuit 350. For clarity, Figures 3A, 3B, and 3C are used to illustrate the internal structures of the latch circuit 310, the first logic circuit 320, the second logic circuit 330, the multiplexing circuit 340, and the third logic circuit 350 in the mapping control circuit 300, respectively.

Referring simultaneously to Figures 3A, 3B, and 3C, latch circuit 310 can store the received authentication data DV. When the system is powered on, latch circuit 310 can obtain the authentication data DV, for example, from another one-time programmable (OTP) memory. Latch circuit 310 includes latches L0 to L11. Latches L0 to L11 can sequentially store multiple bit values that make up the authentication data DV and output them as authentication signals SDV0 to SDV11 respectively.

The first logic circuit 320 is coupled to the latch circuit 310. The first logic circuit 320 can receive the authentication signals SDV0~SDV10 and the low logic level signal VSS, and perform multi-level calculations using the authentication signals SDV0~SDV10 and the low logic level signal VSS to generate control signals ST0~ST10.

In detail, in Figure 3B, the first logic circuit 320 includes OR gates 322_0 to 322_10. OR gates 322_0 to 322_10 are connected in series. The first inputs of OR gates 322_0 to 322_10 respectively receive authentication signals SDV0 to SDV10. The outputs of OR gates 322_0 to 322_10 respectively output control signals ST0 to ST10. The second input of the first-stage OR gate (OR gate 322_0) receives a low logic level signal VSS. The second inputs of the OR gates other than the first-stage OR gates (OR gates 322_1 to 322_10) receive control signals output from the outputs of the previous-stage OR gates.

The second logic circuit 330 can receive the first part P1 of the column selection signal group SELG, and execute and operate the first column selection signal RSGSEL0[3:0] and the second column selection signal RSGSEL1[2:0] in the first part P1 to generate operation signals RS0~RS11.

The second logic circuit 330 includes gates 332_0 to 332_11. The first input terminal of each gate 332_0 to 332_11 receives the corresponding first column selection signal from the first column selection signal RSGSEL0[3:0]. The second input terminal of each gate 332_0 to 332_11 receives the corresponding second column selection signal from the second column selection signal RSGSEL1[2:0]. The output terminals of gates 332_0 to 332_11 output operation signals RS0 to RS11 respectively.

In Figure 3C, multiplexing circuit 340 is coupled to first logic circuit 320 and second logic circuit 330. Multiplexing circuit 340 receives control signals ST0~ST10 and operation signals RS0~RS11, and selects multiple of the operation signals RS0~RS11 as decoding signals SCD0~SCD10 according to the control signals ST0~ST10.

In detail, the multiplexing circuit 340 includes multiplexers 342_0 to 342_10. Each multiplexer 342_0 to 342_10 receives two corresponding operation signals from RS0 to RS11 at its first and second input terminals. For example, multiplexer 342_0 receives operation signal RS0 at its first input terminal and operation signal RS1 at its second input terminal. Multiplexer 342_1 receives operation signal RS1 at its first input terminal and operation signal RS2 at its second input terminal, and so on.

The control terminals of multiplexers 342_0~342_10 receive control signals ST0~ST10 respectively, and the output terminals of multiplexers 342_0~342_10 output decoding signals SCD0~SCD10 respectively. Each multiplexer 342_0~342_10 selects one of the signals received from its first input terminal (upper input terminal) and the signal received from its second input terminal (lower input terminal) as the corresponding decoding signal and outputs it at its output terminal. Taking multiplexer 342_1 as an example, when it receives the high logic level control signal ST1, multiplexer 342_1 will select the operation signal RS1 received from its first input terminal (upper input terminal) as the decoding signal SCD1 for output. When the low logic level control signal ST1 is received, the multiplexer 342_1 will select the operation signal RS2 received by its second input terminal (lower input terminal) as the decoding signal SCD1 for output.

The third logic circuit 350 is coupled to the latch circuit 310, the second logic circuit 330, and the multiplexing circuit 340. The third logic circuit 350 can receive the verification signals SDV0~SDV11, the lowest address operation signal RS0 corresponding to the operation signals RS0~RS11, and the decoding signals SCD0~SCD10. It inverts the verification signals SDV0~SDV11 and then performs the operation with the operation signals RS0 and the decoding signals SCD0~SCD10 respectively to output the generated activation signals SE0~SE11 to the decoders 400_0~400_11 respectively.

In detail, the third logic circuit 350 includes inverters 352_0 to 352_11 and gates 354_0 to 354_11. The input terminals of inverters 352_0 to 352_11 receive SDV0 to SDV11 respectively.

The first input of gate 354_0 receives the operation signal RS0. The first inputs of gates 354_1 to 354_11 receive the decoding signals SCD0 to SCD10, respectively. The second inputs of gates 354_0 to 354_11 are coupled to the outputs of inverters 352_0 to 352_11, respectively. The outputs of gates 354_0 to 354_11 output the enable signals SE0 to SE11, respectively.

In operation, for example, as shown in Figures 4A, 4B, and 4C, when there are damaged or faulty memory cells in the memory block opened by decoder 400_1, the inverter 352_1 in the third logic circuit 350 receives a high-level (logic value 1) verification signal SDV1 from the latch L1 in the latch circuit 310. Thus, the gate 354_1 can only output a low-level (logic value 0) enable signal SE1 to decoder 400_1, thereby disabling decoder 400_1 as a decoder for the faulty memory block.

At this time, the OR gate 322_1 in the first logic circuit 320 will also receive the high logic level verification signal SDV1. Since the OR gates 322_0~322_10 are connected in series, the control signals ST1~ST10 output by the OR gates 322_1~322_10 will all be adjusted to the high logic level. In this case, the multiplexers 342_1~342_10 in the multiplexing circuit 340 will change to select the operation signals RS1~RS10 received by their first input terminal (upper input terminal) as the decoding signals SCD1~SCD10 for output.

In this way, the column address ranges corresponding to decoders 400_2 to 400_11, which are decoders of faulty memory blocks following decoder 400_1, will shift forward from column address ranges RSG2 to RSG11 to column address ranges RSG1 to RSG10. This allows decoder 400_2 to replace decoder 400_1 and correspond to column address range RSG1, preventing the memory block opened by decoder 400_1 from being mapped again.

The following is another embodiment illustrating the implementation of the mapping control circuit. The mapping control circuit 500 of this embodiment is applicable to situations where one or two memory blocks are damaged, requiring reordering of the column address ranges corresponding to decoders 600_0 to 600_11. The mapping control circuit 500 includes a latch circuit 510, a first logic circuit 520, a second logic circuit 530, a multiplexing circuit 540, and a third logic circuit 550. For clarity, Figures 5A, 5B, and 5C are used to illustrate the internal structures of the latch circuit 510, the first logic circuit 520, the second logic circuit 530, the multiplexing circuit 540, and the third logic circuit 550 in the mapping control circuit 500, respectively.

Please refer to Figures 5A, 5B, and 5C simultaneously. The latch circuit 510 can store the received authentication data DV. The latches L0 to L11 included in the latch circuit 510 can sequentially store multiple bit values that make up the authentication data DV, and output them as authentication signals SDV0 to SDV11 respectively.

The first logic circuit 520 is coupled to the latch circuit 510. The first logic circuit 520 can receive authentication signals SDV0~SDV10 and low logic level signal VSS, and perform multi-level operations using the authentication signals SDV0~SDV10 and the low logic level signal VSS to generate control signals ST0~ST10. Unlike the previous embodiment, in this embodiment, each control signal ST0~ST10 consists of two bit signals. For example, control signal ST0 consists of bit signal ST0<0> and bit signal ST0<1>, control signal ST1 consists of bit signal ST1<0> and bit signal ST1<1>, and so on.

In detail, in Figure 5B, the first logic circuit 520 includes OR gates 522_0~522_10, and OR gates 524_0~524_10 and 526_0~526_10. OR gates 522_0~522_10 are connected in series. The first inputs of OR gates 522_0~522_10 respectively receive authentication signals SDV0~SDV10. The outputs of OR gates 522_0~522_10 respectively output bit signals ST0<0>~ST10<0>. The second input of the first-stage OR gate (OR gate 522_0) receives the low logic level signal VSS. The second input of the OR gate (OR gate 522_1~OR gate 522_10) other than the first stage receives the bit signal output by the output of the OR gate of the previous stage.

The first input terminals of gates 524_0 to 524_10 respectively receive authentication signals SDV1 to SDV11. The second input terminals of gates 524_0 to 524_10 respectively receive bit signals ST0<0> to ST10<0>.

OR gates 526_0 to 526_10 are connected in series. The first inputs of OR gates 526_0 to 526_10 are coupled to the outputs of gates 524_0 to 524_10, respectively. The outputs of OR gates 526_0 to 526_9 output bit signals ST1<1> to ST10<1>, respectively. The second input of the first-stage OR gate (OR gate 526_0) receives the low logic level signal VSS. The second inputs of the OR gates other than the first-stage OR gates (OR gates 526_1 to 526_10) receive the bit signals output from the outputs of the previous-stage OR gates.

The second logic circuit 530 can receive the first part P1 of the column selection signal group SELG, and through the gates 532_0~532_11, execute and calculate the first column selection signal RSGSEL0[3:0] and the second column selection signal RSGSEL1[2:0] in the first part P1 to generate the calculation signals RS0~RS11.

In Figure 5C, multiplexing circuit 540 is coupled to first logic circuit 520 and second logic circuit 530. Multiplexing circuit 540 receives control signals ST0~ST10 and operation signals RS0~RS11, and selects multiple of the operation signals RS0~RS11 as decoding signals SCD0~SCD10 according to the control signals ST0~ST10.

Specifically, the multiplexing circuit 540 includes multiplexers 542_0 to 542_10. Unlike the previous embodiment, the first input of multiplexer 542_0 receives a low logic level signal VSS, and the second and third inputs of multiplexer 542_0 receive operation signals RS0 and RS1. Each multiplexer 542_1 to 542_10 receives three corresponding operation signals from RS0 to RS11 at its first, second, and third inputs. For example, the first input of multiplexer 542_1 receives operation signal RS0, the second input of multiplexer 542_1 receives operation signal RS1, and the third input of multiplexer 542_1 receives operation signal RS2. The first input terminal of the multiplexer 542_2 receives the operation signal RS1, the second input terminal of the multiplexer 542_2 receives the operation signal RS2, the third input terminal of the multiplexer 542_2 receives the operation signal RS3, and so on.

The control terminals of multiplexers 542_0~542_10 receive control signals ST0~ST10 respectively, and the output terminals of multiplexers 542_0~542_10 output decoding signals SCD0~SCD10 respectively. Each multiplexer 542_0~542_10 selects one of the signals received from its first input terminal (upper input terminal), its second input terminal (middle input terminal), and its third input terminal (lower input terminal) as the corresponding decoding signal and outputs it at its output terminal according to the received control signal. Taking multiplexer 542_1 as an example, when it receives a control signal ST1 (logic value 11) consisting of a high-level bit signal ST1<0> and a high-level bit signal ST1<1>, multiplexer 542_1 will select the operation signal RS0 received from its first input terminal (upper input terminal) as the decoding signal SCD1 for output. When it receives a control signal ST1 (logic value 01) consisting of a high-level bit signal ST1<0> and a low-level bit signal ST1<1>, multiplexer 542_1 will select the operation signal RS1 received from its second input terminal (middle input terminal) as the decoding signal SCD1 for output. When the multiplexer 542_1 receives the control signal ST1 (logic value 00), which consists of the low logic level bit signal ST1<0> and the low logic level bit signal ST1<1>, it will select the operation signal RS2 received by its third input terminal (lower input terminal) as the decoding signal SCD1 for output.

The third logic circuit 550 is coupled to the latch circuit 510, the second logic circuit 530, and the multiplexing circuit 540. The third logic circuit 550 can receive the authentication signals SDV0~SDV11, the lowest address operation signal RS0 corresponding to the operation signals RS0~RS11, and the decoding signals SCD0~SCD10. The authentication signals SDV0~SDV11 are inverted by inverters 552_0~552_11 and then executed and operated with the operation signals RS0 and the decoding signals SCD0~SCD10 respectively by gates 554_0~554_11, so as to output the generated activation signals SE0~SE11 to the decoders 600_0~600_11 respectively.

In operation, for example, as shown in Figures 6A, 6B, and 6C, if there is damage in the two memory blocks opened by decoders 600_1 and 600_5, the inverters 552_1 and 552_5 in the third logic circuit 550 will receive high logic level (logic value 1) verification signals SDV1 and SDV5 respectively from latches L1 and L5 in the latch circuit 510. Thus, gates 554_1 and 554_5 can only output low logic level (logic value 0) enable signals SE1 and SE5 to decoders 600_1 and 600_5 respectively, thereby disabling decoders 600_1 and 600_5 as decoders of bad memory blocks.

At this time, the OR gate 522_1 in the first logic circuit 520 will also receive the high-level verification signal SDV1. Since OR gates 522_0~522_10 are connected in series, the bit signals ST1<0>~ST10<0> output by OR gates 522_1~522_10 will all be adjusted to the high-level logic. In addition, the outputs of gates 524_1~524_10 that receive the bit signals ST1<0>~ST10<0> will be adjusted to the same logic levels as the verification signals SDV2~SDV11, respectively. That is to say, the output of gate 524_4 will be adjusted to the same high-level logic as SDV5.

Since the OR gates 526_0~526_10 are also connected in series, the bit signals ST5<1>~ST10<1> output by the OR gates 526_4~526_9 will all be adjusted to a high logic level. In this case, the logic values of control signals ST1~ST3 are "01", and the logic values of control signals ST5~ST10 are "11". The multiplexers 542_1~542_3 in the multiplexing circuit 540 will change to select the operation signals RS1~RS3 received by their second input terminal (intermediate input terminal) as the decoding signals SCD1~SCD3 for output. The multiplexers 542_5~542_10 will change to select the operation signals RS4~RS9 received by their first input terminal (top input terminal) as the decoding signals SCD5~SCD10 for output.

In this way, the column address ranges corresponding to decoders 600_2~600_4, which are decoders of bad memory blocks following decoder 600_1, will be shifted forward from column address range RSG2~RSG4 to column address range RSG1~RSG3. The column address ranges corresponding to decoders 600_6~600_11, which are decoders of bad memory blocks following decoder 600_5, will be shifted forward from column address range RSG6~RSG11 to column address range RSG4~RSG9. In this way, decoder 600_2 replaces decoder 600_1 and corresponds to column address range RSG1, and decoder 600_7 replaces decoder 600_5 and corresponds to column address range RSG5, so that the two memory blocks opened by decoders 600_1 and 600_5 can no longer be mapped.

It should be noted that, for ease of understanding, the above embodiments are illustrated with the case of one or two memory blocks containing damaged memory cells, but the present invention is not limited to this. Those skilled in the art can adjust the internal structure of the mapping control circuit according to their actual needs based on the teachings of the present invention to adapt it to cases where more memory blocks contain damaged memory cells.

In summary, the column decoder circuit of this invention does not perform traditional repairs on memory blocks with faulty memory cells, but rather reorders the column address range corresponding to the decoder. In this way, during mapping, damaged memory blocks can be bypassed, allowing the memory device to function normally. This ensures that partially damaged memory devices remain usable, and also increases product yield and ease of use.

100: Column decoder circuit 110: Pre-decoder 120_0~120_11, 400_0~400_11, 600_0~600_11: Decoder 130, 300, 500: Mapping control circuit 310, 510: Latch circuit 320, 520: First logic circuit 322_0~322_10, 522_0~522_10, 526_0~526_10: OR gate 330, 530: Second logic circuit 332_0~332_11, 354_0~354_11, 524_0~524_10, 532_0~532_11, 554_0~554_11: Gate 340, 540: Multiplexing circuit 342_0~342_10, 542_0~542_10: Multiplexer 350, 550: Third logic circuit 352_0~352_11, 552_0~552_11: Inverter DV: Verification data L0~L11: Latch P1: First part P2: Second part RA: Column address information RMWSEL0[7:0], RMWSEL1[3:0], RMWSEL2[2:0], RFXSEL[7:0]: Column select signals RS0~RS11: Operation signals RSG0~RSG11: Column address range RSGSEL0[3:0]: First column select signal RSGSEL1[2:0]: Second column select signal SCD0~SCD10: Decoding signals SDV0~SDV11: Verification signals SE0~SE11: Enable signals SELG: Column select signal group ST0~ST10: Control signals ST0<0>~ST10<0>, ST0<1>~ST10<1>: Bit signals SWL0~SWL11: Word line signals VSS: Low logic level signal

Figure 1 is a block diagram of a column decoder circuit according to one embodiment. Figure 2 is an operational schematic diagram of a column decoder circuit according to one embodiment. Figures 3A to 3C are circuit diagrams of a mapping control circuit according to one embodiment. Figures 4A to 4C are operational schematic diagrams of a mapping control circuit according to one embodiment. Figures 5A to 5C are block diagrams of a mapping control circuit according to another embodiment. Figures 6A to 6C are operational schematic diagrams of a mapping control circuit according to yet another embodiment.

100: Column decoder circuit

110: Predecoder

120_0~120_11: Decoder

130: Mapping control circuit

DV: Verification Data

P1: Part One

P2: Part Two

RA: List address information

RMWSEL0[7:0], RMWSEL1[3:0], RMWSEL2[2:0], RFXSEL[7:0]: Column selection signals

RSG0~RSG11: Column address range

RSGSEL0[3:0]: First column selection signal

RSGSEL1[2:0]: Second column selection signal

SELG: Column Selection Signal Group

Claims (15)

A column decoder circuit, suitable for a memory device, includes: a pre-decoder configured to receive column address information and decode the column address information to provide a column select signal set; a plurality of decoders sequentially corresponding to a plurality of column address ranges; and a mapping control circuit coupled to the pre-decoder and the decoders, configured to obtain a select column address range based on the column select signal set, and to cause the decoder whose corresponding column address range is the same as the select column address range to output a word line signal, wherein the mapping control circuit reorders the column address ranges corresponding to the decoders according to the verification data, and the mapping control circuit determines the location of at least one damaged memory block according to the verification data. The column decoder circuit of claim 1, wherein the mapping control circuit obtains the selected column address range according to a first portion of the column selection signal group, and the decoder corresponding to the same column address range as the selected column address range outputs the corresponding character line signal according to a second portion of the column selection signal group. The column decoder circuit as claimed in claim 1, wherein the mapping control circuit generates a plurality of verification signals based on the verification data, and disables at least one bad memory block decoder among the decoders based on the verification signals. The column decoder circuit as described in claim 3, wherein the mapping control circuit shifts forward the column address ranges corresponding to the decoders following the at least one bad memory block decoder according to the verification signals, thereby replacing the at least one bad memory block decoder. The column decoder circuit of claim 1, wherein the mapping control circuit includes: a latch circuit configured to store the verification data, wherein the latch circuit includes a plurality of latches that output a plurality of bit values constituting the verification data as a plurality of verification signals. The column decoder circuit as described in claim 5, wherein the mapping control circuit further includes: a first logic circuit coupled to the latch circuit, configured to receive the authentication signals and a low logic level signal, and to perform multi-level operations using the authentication signals and the low logic level signal to generate multiple control signals. The column decoder circuit as described in claim 6, wherein the first logic circuit includes: a plurality of OR gates connected in series, each OR gate having a first input receiving a corresponding verification signal, each OR gate having an output output outputting a corresponding control signal, a first-stage OR gate having a second input receiving the low logic level signal, and OR gates other than the first stage having a second input receiving the control signal output by the output of the previous-stage OR gate. The column decoder circuit as described in claim 6, wherein each of the control signals includes a first bit signal and a second bit signal, the first logic circuit comprising: a plurality of first OR gates connected in series, wherein the first input of each of the first OR gates receives corresponding authentication signals, and the output of each of the first OR gates outputs the first bit signal from the corresponding control signals; the second input of the first OR gate of the first stage receives the low logic level signal; and the second input of the first OR gates other than the first stage receives the first bit signal output from the output of the first OR gate of the previous stage; a plurality of AND gates, wherein the first input of each AND gate receives the corresponding authentication signal, and the second input of each AND gate receives the first bit signal from the corresponding control signals; and Multiple second orifices are connected in series. The first input of each of the second orifices is coupled to the output of the corresponding second orifice. The output of each of the second orifices outputs the second bit signal from the corresponding control signals. The second input of the first-stage second orifice receives the low logic level signal. The second input of the second orifices other than the first-stage second orifice receives the second bit signal output from the output of the second orifice of the previous stage. The column decoder circuit as described in claim 6, wherein the mapping control circuit further includes: a second logic circuit configured to receive a first portion of the column selection signal group, and to perform and operate on a plurality of first column selection signals in the first portion and a plurality of second column selection signals in the first portion to generate a plurality of operation signals. The column decoder circuit as described in claim 9, wherein the second logic circuit includes: a plurality of gates, each gate having a first input terminal receiving a corresponding first column selection signal, each gate having a second input terminal receiving a corresponding second column selection signal, and the gates having an output terminal outputting a corresponding operation signal. The column decoder circuit as described in claim 9, wherein the mapping control circuit further includes: a multiplexing circuit coupled to the first logic circuit and the second logic circuit, configured to receive the control signals and the operation signals, and to select a plurality of the operation signals as a plurality of decoding signals according to the control signals. The serial decoder circuit as described in claim 11, wherein the multiplexing circuit includes: a plurality of multiplexers, each multiplexer receiving two corresponding operation signals at its first input and second input, each multiplexer receiving a corresponding control signal at its control terminal, and selecting one of the signal received at its first input and the signal received at its second input as the corresponding decoding signal and outputting it at its output terminal. The decoder circuit as described in claim 11, wherein the multiplexing circuit includes: a plurality of multiplexers, one of which receives the low logic level signal at a first input, the other of which receives two corresponding operation signals at a second and a third input, the other of which receives three corresponding operation signals at a first, a second, and a third input, and the control terminal of each of the multiplexers receives a corresponding control signal and selects one of the signals received at its first input, the second input, and the third input as the corresponding decoding signal for output at its output terminal. The column decoder circuit as described in claim 11, wherein the mapping control circuit further includes: a third logic circuit coupled to the latch circuit, the second logic circuit and the multiplexing circuit, configured to receive the verification signals, the lowest address of the operation signals and the decoding signals, and to invert the verification signals and perform operations with the lowest address of the corresponding operation signal and the decoding signals respectively, so as to output the generated multiple enable signals to the decoders respectively. The column decoder circuit as described in claim 14, wherein the third logic circuit includes: a plurality of inverters, each of which receives a corresponding verification signal at its input; and a plurality of gates, one of which receives the lowest address operation signal among the operation signals at its first input, the other of which receives a corresponding decoding signal at its first input, a second input of each of the gates coupled to the output of a corresponding inverter, and an output of each of the gates outputting a corresponding enable signal.