TWI902452B - Semiconductor device - Google Patents

Abstract

The present disclosure provides a semiconductor device including a semiconductor epitaxial structure, a metal contact structure, an insulating layer and a metal oxide layer. The semiconductor epitaxial structure includes an active structure and a first semiconductor structure under the active structure. The first semiconductor structure includes a first semiconductor contact layer. The first semiconductor contact layer has a lower surface. The metal contact structure directly contacts the lower surface. The insulating layer directly contacts the lower surface and does not directly contact the metal contact structure. The metal oxide layer is located under the first semiconductor contact layer and overlapped with the metal contact structure in a horizontal direction. The metal contact structure is not overlapped with the insulating layer in a vertical direction and is overlapped with the insulating layer in the horizontal direction.

Description

semiconductor devices

This invention relates to a semiconductor device, and more particularly to a semiconductor device having a metal contact structure.

Semiconductor devices have a wide range of applications, and the development and research of related materials are ongoing. For example, III-V group semiconductor materials containing group III and group V elements can be used in various optoelectronic semiconductor devices such as light-emitting diodes (LEDs), laser diodes (LDs), photodetectors, or solar cells. They can also be used as power devices such as switching devices or rectifiers, and are applied in fields such as lighting, medical, display, communication, sensing, and power supply systems. As one type of semiconductor light-emitting element, the light-emitting diode (LED) has advantages such as low power consumption, fast response speed, small size, and long service life, and is therefore widely used in various fields.

This disclosure provides a semiconductor device including a semiconductor epitaxial structure, a metal contact structure, an insulating layer, and a metal oxide layer. The semiconductor epitaxial structure includes an active structure and a first semiconductor structure located beneath the active structure. The first semiconductor structure includes a first semiconductor contact layer. The first semiconductor contact layer has a lower surface. The metal contact structure directly contacts the lower surface. The insulating layer directly contacts the lower surface but is not in direct contact with the metal contact structure and is spaced apart by a distance. The metal oxide layer is located beneath the first semiconductor contact layer and overlaps the metal contact structure in a horizontal direction. The metal contact structure and the insulating layer do not overlap in a vertical direction but overlap in a horizontal direction.

According to one embodiment of this disclosure, the metal contact structure includes a plurality of mutually separated metal pillars. One of the plurality of metal pillars includes a first surface, a second surface, and a side surface, wherein the second surface directly contacts the lower surface of the semiconductor contact layer, the first surface is opposite the second surface, and the side surface connects the first surface and the second surface.

According to one embodiment of this disclosure, the thickness of the metal oxide layer is greater than or less than the thickness of one of the plurality of metal pillars.

According to one embodiment of this disclosure, the metal oxide layer directly contacts the first surface and the side surface.

According to one embodiment of this disclosure, the first semiconductor contact layer comprises multiple mutually separated portions, and the metal contact structure comprises a plurality of mutually separated metal pillars, each portion overlapping and directly contacting the plurality of metal pillars in the vertical direction.

According to one embodiment of this disclosure, the width of one of the plurality of metal pillars may gradually decrease from the side closest to the first semiconductor structure toward the side furthest from the first semiconductor structure.

According to one embodiment of this disclosure, the width of each metal column is greater than 0 μm and less than 10 μm.

According to one embodiment of this disclosure, a reflective layer is also included, located beneath the metal oxide layer.

According to one embodiment of this disclosure, the metal contact structure includes a main contact layer in direct contact with the first semiconductor contact layer, and neither beryllium nor zinc is present in the main contact layer.

This disclosure provides a semiconductor device, including a packaging substrate, a semiconductor device disposed on the packaging substrate, and a packaging layer covering the semiconductor device.

10, 10A, 10B, 10C: Semiconductor devices

100: Semiconductor epitaxial structure

100a: First luminescent layer

100a1: First Semiconductor Structure

100a2: First active structure

100a3: Second Semiconductor Structure

100b: Second luminescent layer

100b1: Third Semiconductor Structure

100b2: Second active structure

100b3: Fourth Semiconductor Structure

100c: Tunneling structure

100c1: First tunnel level

100c2: Second tunnel level

101a: First semiconductor contact layer

101a1: Partial

101b: Second semiconductor contact layer

101s: Lower surface

102: Metal Contact Structure

102a: Metal Column

102-1: Main Contact Layer

102-1a: First primary contact layer

102-1b: Second Primary Contact Layer

102-2: Barrier Layer

102-3: Protrusion

104: The Insulation Layer

104s: Surface

106: First Electrode

106a: Electrode Pad

106b: Extended electrode

106c: Connector

108: Metal oxide layer

110: Reflective layer

110a: Upper surface

112: Bonding layer

114: Base

116: Second Electrode

20: Packaging Structure

21: Packaging substrate

22: Through hole

23: First Conductor Structure

23a: First contact pad

23b: Second contact pad

25: Conductive thread

26: Second Conductive Structure

26a: Third contact pad

26b: Fourth contact pad

28: Encapsulation Layer

θ: Angle

A-A’: Section line

R, _R0 : Region

W1: Width

s1: First surface

s2: Second surface

s3: Side surface

X: Horizontal direction

Y: Vertical direction

G1, G2: Gap

Figure 1 is a perspective view of a semiconductor device according to an embodiment of this disclosure.

Figure 2 is a schematic cross-sectional view of the semiconductor device in Figure 1 along section line A-A'.

Figure 3 is a magnified view of region R of the semiconductor device in Figure 2.

Figure 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of this disclosure.

Figure 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of this disclosure.

Figure 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of this disclosure.

Figure 7 is a schematic cross-sectional view of the package structure of a semiconductor device including an embodiment of this disclosure.

To provide a more detailed and complete description of the present invention, the invention will be explained in detail below with reference to the accompanying drawings. It should be noted that the following illustrations are examples of semiconductor components of the invention and are not intended to limit the invention to these embodiments. In the drawings or description, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shapes or dimensions of the components in the drawings are illustrative only and are not actually limited thereto. It should be particularly noted that components not shown or described in the drawings may be in forms known to those skilled in the art.

Furthermore, unless otherwise specified, the description "the first layer (or structure) is located on the second layer (or structure)" can include embodiments where the first layer (or structure) and the second layer (or structure) are in direct contact, or embodiments where there are other structures between the first layer (or structure) and the second layer (or structure) and they are not in direct contact with each other. Additionally, it should be understood that the vertical relationship between the layers (or structures) may change depending on the viewing angle.

Please refer to Figures 1-3 for the following descriptions of the embodiments. Figure 1 is a top-view perspective view of a semiconductor device according to one embodiment of this disclosure; Figure 2 is a cross-sectional view of the semiconductor device in Figure 1 along section line A-A'; Figure 3 is a partially enlarged view of region R of the semiconductor device in Figure 2. For clarity, the following descriptions of the embodiments will refer to the coordinate axes indicated in Figure 2. The "width" of each component is a value measured along the horizontal direction X; the "thickness" of each component is a value measured along the vertical direction Y; the "stack direction" refers to the vertical direction Y or the opposite direction of the vertical direction Y, which is perpendicular to the horizontal direction X.

As shown in Figure 2, the semiconductor device 10 of this embodiment includes a semiconductor epitaxial structure 100, a metal contact structure 102, and a metal oxide layer 108. Furthermore, the semiconductor device 10 may optionally include an insulating layer 104, a first electrode 106, a metal oxide layer 108, a reflective layer 110, a substrate 114, and a second electrode 116. A bonding layer 112 is located between the semiconductor epitaxial structure 100 and the substrate 114. The reflective layer 110 is located between the bonding layer 112 and the semiconductor epitaxial structure 100. The metal contact structure 102, the insulating layer 104, and the metal oxide layer 108 are all located between the semiconductor epitaxial structure 100 and the reflective layer 110. The first electrode 106 and the second electrode 116 are respectively located on both sides of the semiconductor device 10 for electrical connection to an external power supply. As shown in Figure 2, the first electrode 106 is located above the semiconductor epitaxial structure 100, and the second electrode 116 is located below the substrate 114. In this embodiment, the semiconductor epitaxial structure 100 can form an electrical connection with the reflective layer 110, the bonding layer 112, and the substrate 114 through the metal contact structure 102. In one embodiment, the semiconductor epitaxial structure 100 is first formed on an epitaxial growth substrate through an epitaxial growth process, and then the semiconductor epitaxial structure 100 is bonded to the substrate 114 through the bonding layer 112. After the bonding is completed, the epitaxial growth substrate is removed, thereby forming the semiconductor device 10.

The semiconductor epitaxial structure 100 may include a first semiconductor contact layer 101a. In this embodiment, the first semiconductor contact layer 101a is the semiconductor layer closest to the substrate 114 in the semiconductor epitaxial structure 100. As shown in Figure 2, in the vertical direction Y, a metal contact structure 102 is located between the first semiconductor contact layer 101a and the reflective layer 110. A metal oxide layer 108 is located between the first semiconductor contact layer 101a and the reflective layer 110. In the horizontal direction X, the metal oxide layer 108 substantially overlaps with the metal contact structure 102, that is, the metal oxide layer 108 and the metal contact structure 102 are horizontally juxtaposed on the upper surface 110a of the reflective layer 110. As shown in Figure 3, the metal oxide layer 108 and the metal contact structure 102, as well as the metal oxide layer 108 and the first semiconductor contact layer 101a, can be separated by gaps. Specifically, in the horizontal direction X, the metal oxide layer 108 and the metal contact structure 102 are separated by gap G1, so that the metal oxide layer 108 does not directly contact the metal contact structure 102; in the vertical direction Y, the metal oxide layer 108 and the first semiconductor contact layer 101a are also separated by gap G2, so that the metal oxide layer 108 does not directly contact the first semiconductor contact layer 101a. As shown in Figure 2, the insulating layer 104 can be filled with gaps G1 and G2 to separate the metal oxide layer 108 from the metal contact structure 102, and to separate the metal oxide layer 108 from the first semiconductor contact layer 101a. In this embodiment, both the insulating layer 104 and the metal contact structure 102 are in direct contact with the lower surface 101s of the first semiconductor contact layer 101a. Specifically, the portion of the lower surface 101s of the first semiconductor contact layer 101a that is not in direct contact with the metal contact structure 102 is in direct contact with the insulating layer 104. ^According to one embodiment, the first semiconductor contact layer 101a may have a higher dopant concentration (e.g., ^1x10¹⁸ / ^cm³ or ^higher ) to form a good low-resistance interface with the metal contact structure 102, such as an ohmic contact. Since the resistance between the insulating layer 104 and the first semiconductor contact layer 101a is higher than the resistance between the metal contact structure 102 and the first semiconductor contact layer 101a, the current path is mainly formed in the portion where the metal contact structure 102 and the first semiconductor contact layer 101a are in direct contact. By changing the relative distribution of the insulation layer 104 and the metal contact structure 102, the current distribution effect of the semiconductor device 10 can be improved, thereby enhancing the electrical performance of the semiconductor device 10.

In this embodiment, the metal contact structure 102 includes a plurality of metal pillars 102a that are separated from each other. For ease of description, the relative relationships of the components are illustrated below using one of the metal pillars 102a as an example. As shown in Figure 2, in the vertical direction Y, the insulating layer 104 is located between the first semiconductor contact layer 101a and the metal oxide layer 108, and is in direct contact with a portion of the metal pillar 102a. Specifically, as shown in the partially enlarged schematic diagram of region R in Figure 3, the metal pillar 102a may have a first surface s1, a second surface s2, and a side surface s3. The first surface s1 is farther from the first semiconductor contact layer 101a than the second surface s2, and the side surface s3 connects the first surface s1 and the second surface s2. In one cross-section of the semiconductor device 10, the second surface s2 and the side surface s3 may form an acute angle θ, i.e., the side surface s3 is inclined, thereby making it easier for the insulating layer 104 to cover the side surface s3 of the metal pillar 102a. In one embodiment, the side surface s3 is completely directly covered by the insulating layer 104, thereby separating the metal pillar 102a and the metal oxide layer 108 in the horizontal direction X. In one embodiment, the second surface s2 of the metal pillar 102a is directly connected to the first semiconductor contact layer 101a, and the first surface s1 of the metal pillar 102a is directly connected to the reflective layer 110.

As shown in Figure 3, the metal pillar 102a includes a main contact layer 102-1, which is in direct contact with the first semiconductor contact layer 101a and the reflective layer 110 to form a good electrical contact. The material of the main contact layer 102-1 may contain metals, such as gold (Au), silver (Ag), or alloys containing gold or silver (such as beryllium gold (BeAu) or zinc gold (ZnAu)). According to some embodiments, when the material of the main contact layer 102-1 does not contain any alloys such as beryllium (BeAu) or zinc (ZnAu) (for example, the material of the main contact layer 102-1 is gold (Au), and beryllium (Be) or zinc (Zn) is not present in the main contact layer 102-1), electrical contact (e.g., forming an ohmic junction) between the metal contact structure 102 and the first semiconductor contact layer 101a can be formed at a lower process temperature, thus avoiding the absorption of light emitted by the semiconductor epitaxial structure 100 due to alloy formation at the interface between the metal contact structure 102 and the first semiconductor contact layer 101a during the process. In one embodiment, the metal pillar 102a may optionally include a barrier layer 102-2. As shown in Figure 3, a first main contact layer 102-1a and a second main contact layer 102-1b, the first main contact layer 102-1a being closer to the first semiconductor contact layer 101a than the second main contact layer 102-1b. The first main contact layer 102-1a is in direct contact with the first semiconductor contact layer 101a, and the second main contact layer 102-1b is in direct contact with the reflective layer 110. A barrier layer 102-2 is formed between the first main contact layer 102-1a and the second main contact layer 102-1b, and is in direct contact with the insulating layer 104. The barrier layer 102-2 connects the first main contact layer 102-1a and the second main contact layer 102-1b. The barrier layer 102-2 is closer to the semiconductor epitaxial structure 100 than the second main contact layer 102-1b. The barrier layer 102-2 can be used to block the diffusion of material from the reflective layer 110 into the first semiconductor contact layer 101a, preventing excessive material from the reflective layer 110 from forming an alloy with the metal pillar 102a and/or the material of the first semiconductor contact layer 101a, thus avoiding any impact on reflectivity.

In one embodiment, the metal pillar 102a may optionally include one or more protrusions 102-3. As shown in Figure 3, the protrusions 102-3 may protrude along the vertical direction Y from the second surface s2 toward the first electrode 106 and be embedded in the first semiconductor contact layer 101a. Any two of the plurality of protrusions 102-3 may be separate from or connected to each other. In this embodiment, the cross-sectional shape of the protrusions 102-3 may be generally triangular, trapezoidal, semi-circular, or other arc-shaped. Each of the plurality of protrusions 102-3 may have the same or different dimensions. According to some embodiments, the protrusion 102-3 can increase the contact area between the first semiconductor contact layer 101a and the metal pillar 102a, thereby improving the adhesion between the first semiconductor contact layer 101a and the metal pillar 102a and reducing the resistance between the first semiconductor contact layer 101a and the metal pillar 102a. According to one embodiment, the material of the barrier layer 102-2 may include a metal or alloy, such as tantalum (Ta), titanium (Ti), platinum (Pt), or titanium tungsten (TiW). The protrusion 102-3 contains the same material as the main contact layer 102-1. According to one embodiment, the protrusion 102-3 may comprise the material of the main contact layer 102-1, the material of the first semiconductor contact layer 101a, and/or the material of the reflective layer 110, or an alloy comprising these materials. For example, when the first semiconductor contact layer 101a comprises a binary III-V compound semiconductor material such as gallium phosphide (GaP), the material of the main contact layer 102-1 comprises gold (Au), and the material of the reflective layer 110 comprises silver (Ag), the protrusion 102-3 may comprise at least two of gallium (Ga), gold (Au), and silver (Ag), or an alloy of at least two of them (e.g., GaAuAg, AuAg, or GaAu, etc.).

Referring to Figure 2, in a cross-section of the semiconductor device 10, the metal pillar 102a is generally inverted trapezoidal in shape. The inverted trapezoid includes a long side, a short side, and two inclined sides connecting the long and short sides. The short side is closer to the substrate 114 than the long side. In one embodiment, the thickness of the metal oxide layer 108 is less than the thickness of the metal pillar 102a. In the vertical direction Y, the sum of the thicknesses of the metal oxide layer 108 and the insulating layer 104 may be approximately the same as or differ by less than 1 micrometer from the thickness of the metal pillar 102a. In one embodiment, the thickness of the metal pillar 102a may be in the range of 1000 Å to 1 μm. According to some embodiments, when the thickness of the metal pillar 102a is greater than 1000 Å, the semiconductor device 10 may further exhibit better luminous power. According to one embodiment, the adhesion between the metal oxide layer 108 and the insulating layer 104 can be greater than the adhesion between the insulating layer 104 and the reflective layer 110, or the adhesion between the metal oxide layer 108 and the reflective layer 110 can be greater than the adhesion between the insulating layer 104 and the reflective layer 110. The presence of the metal oxide layer 108 can enhance the adhesion between the insulating layer 104 and the reflective layer 110, further improving the structural strength of the semiconductor device 10. In one embodiment, the reflective layer 110 directly contacts the metal oxide layer 108, the insulating layer 104, and the metal contact structure 102. In one embodiment, the cross-sectional shape of the metal oxide layer 108 may include polygons, such as trapezoids or rectangles.

As shown in Figure 1, a first electrode 106 is located on the semiconductor epitaxial structure 100. The first electrode 106 may include an electrode pad 106a, a plurality of extended electrodes 106b, and a connecting portion 106c. The electrode pad 106a serves as an electrical connection point to an external power supply or other components. The plurality of extended electrodes 106b are separated from each other and connected to the electrode pad 106a through the connecting portion 106c. The plurality of extended electrodes 106b are, for example, finger-shaped, arranged parallel to each other, and extend to the periphery of the semiconductor device 10. As shown in Figures 1 and 3, in one embodiment, the first electrode 106 and the metal contact structure 102 do not overlap in the vertical direction Y. This avoids excessive concentration of the current path directly below the first electrode 106. Furthermore, when the material of the first electrode 106 readily absorbs light emitted by the semiconductor epitaxial structure 100, this configuration reduces light absorption by the first electrode 106. In one embodiment, a protective layer (not shown) can be applied to the first electrode 106 and the semiconductor epitaxial structure 100 to isolate external pollutants and provide further protection for the semiconductor device 10. As shown in Figure 1, viewed from above, the surface of the first electrode 106 has a region _R0 , and the protective layer can cover the portion outside the region _R0 . With this configuration, the portion of the first electrode 106 located in the region _R0 is exposed outside the protective layer for electrical connection with an external power supply. The shape of the region _R0 viewed from above can be circular, elliptical, or polygonal.

As shown in Figure 1, a plurality of metal pillars 102a of the metal contact structure 102 are uniformly distributed between two adjacent extended electrodes 106b. With this design, when operating the semiconductor device 10, the current can be uniformly distributed to the semiconductor epitaxial structure 100, for example, giving the semiconductor device 10 better light emission uniformity. As shown in Figure 1, the plurality of metal pillars 102a of the metal contact structure 102 can be arranged in a two-dimensional point array. According to some embodiments, the shape of each metal pillar 102a is, for example, polygonal (e.g., rectangular, pentagonal, hexagonal), circular, or elliptical. It should be noted that since the metal contact structure 102 is located inside the semiconductor device 10, it cannot be directly observed from the outside of the semiconductor device 10. Therefore, Figure 1 shows a perspective view of the semiconductor device 10, and all figures are drawn with solid lines. In one embodiment, the plurality of metal pillars 102a can be distributed between two adjacent extended electrodes 106b (as shown in Figure 1), or selectively distributed between the extended electrodes 106b and the outer boundary of the semiconductor epitaxial structure 100 to further improve the current distribution effect.

As shown in Figure 2, the semiconductor device 10 further includes a second semiconductor contact layer 101b located between the first electrode 106 and the semiconductor epitaxial structure 100. According to one embodiment, the second semiconductor contact layer 101b may have a higher dopant concentration (e.g., ^1x10¹⁸ / ^cm³ or ^higher ) to form a good electrical contact (e.g., ^ohmic contact) with the first electrode 106. The second semiconductor contact layer 101b may be a patterned semiconductor contact layer. In one embodiment, the second semiconductor contact layer 101b may overlap with a plurality of extended electrodes 106b and a connecting portion 106c of the first electrode 106 in the vertical direction, but not with the electrode pad 106a. As shown in Figure 2, the upper surface and side surface of the second semiconductor contact layer 101b may directly contact the connecting portion 106c (or the plurality of extended electrodes 106b) to increase the contact area.

The semiconductor epitaxial structure 100 includes a first light-emitting layer 100a located between a first electrode 106 and a first semiconductor contact layer 101a. The first light-emitting layer 100a may include a first semiconductor structure 100a1, a second semiconductor structure 100a3, and a first active structure 100a2. The second semiconductor structure 100a3 is located on the first semiconductor structure 100a1, and the first active structure 100a2 is located between the first semiconductor structure 100a1 and the second semiconductor structure 100a3. The first light-emitting layer 100a can emit light with a first peak wavelength Wp1 during operation. The refractive index of the insulating layer 104 may be less than that of the first semiconductor contact layer 101a, and a total internal reflection interface is formed between the insulating layer 104 and the first semiconductor contact layer 101a to improve light extraction efficiency. According to some embodiments, the ratio of the area of the metal contact structure 102 to the area of the first active structure 100a2 may be set to less than 15% to reduce possible light-blocking or light-absorbing effects of the metal contact structure 102; the ratio may be greater than 1% to provide good electrical contact. According to some embodiments, the ratio of the area of the metal contact structure 102 to the area of the first active structure 100a2 is, for example, in the range of 2% to 10%. As shown in Figure 2, each metal pillar 102a in the metal contact structure 102 may have a width W1. The width W1 may be in the range of greater than 0 μm and less than 10 μm, for example, between 1 μm and 6 μm. According to some embodiments, when the width W1 is less than 10 μm, the optical performance of the semiconductor device 10 may be further improved. In one embodiment, the shortest distance in the horizontal direction X between each metal pillar 102a and the nearest extended electrode 106b is greater than the width W1 of each metal pillar 102a, for example, more than twice the width W1, to reduce the light-blocking or light-absorbing effects caused by the extended electrode 106b. The aforementioned shortest distance is, for example, in the range of 5 μm to 30 μm. According to some embodiments, when the aforementioned shortest distance is greater than 5 μm, the light-blocking or light-absorbing effect of the extended electrode 106b can be effectively avoided, further improving the optical performance of the semiconductor device 10. According to some embodiments, when the aforementioned shortest distance is less than 30 μm, the forward voltage of the semiconductor device 10 can be significantly increased due to the excessive distance between the extended electrode 106b and the metal pillar 102a in the horizontal X direction. In one embodiment, the metal contact structure 102 has a reflectivity greater than 80% for the light emitted by the first light-emitting layer 100a, to further reduce the light-blocking or light-absorbing effect of the metal contact structure 102. The metal oxide layer 108 is transparent to light emitted from the first luminescent layer 100a, for example, having a transmittance of at least 70%.

As shown in Figure 2, the semiconductor epitaxial structure 100 may optionally further include a second light-emitting layer 100b stacked on the first light-emitting layer 100a along the vertical direction Y. The second light-emitting layer 100b includes a third semiconductor structure 100b1, a fourth semiconductor structure 100b3, and a second active structure 100b2. The fourth semiconductor structure 100b3 is located on the third semiconductor structure 100b1, and the second active structure 100b2 is located between the third semiconductor structure 100b1 and the fourth semiconductor structure 100b3. When the semiconductor device 10 is operated, the first active structure 100a2 emits light with a first peak wavelength Wp1, and the second active structure 100b2 emits light with a second peak wavelength Wp2. The first peak wavelength Wp1 and the second peak wavelength Wp2 may be the same or different. In one embodiment, the second peak wavelength Wp2 is less than or equal to the first peak wavelength Wp1.

According to one embodiment, when the semiconductor device 10 is a light-emitting device (e.g., a light-emitting diode), the light emitted by the first active structure 100a2 and the second active structure 100b2 during operation of the semiconductor device 10 may include visible light or invisible light. The first peak wavelength Wp1 and the second peak wavelength Wp2 may depend on the material composition of the first active structure 100a2 and the second active structure 100b2. For example, when the material of the first active structure 100a2/second active structure 100b2 contains InGaN series, it can emit blue light or deep blue light with a peak wavelength of 400nm to 490nm, or green light with a peak wavelength of 490nm to 550nm; when the material of the first active structure 100a2/second active structure 100b2 contains AlGaN series, it can emit ultraviolet light with a peak wavelength of 250nm to 40 ... When the material of the active structure 100b2 includes InGaAs, InGaAsP, AlGaAs, or AlGaInAs series, it can emit infrared light with a peak wavelength of 700 to 1700 nm, for example. When the material of the first active structure 100a2/second active structure 100b2 includes InGaP or AlGaInP series, it can emit red light with a peak wavelength of 610 nm to 700 nm, or yellow light with a peak wavelength of 530 nm to 600 nm, for example.

As shown in Figure 2, the semiconductor epitaxial structure 100 may optionally further include a tunneling structure 100c stacked along the vertical direction Y between the first light-emitting layer 100a and the second light-emitting layer 100b for electrically connecting the first light-emitting layer 100a and the second light-emitting layer 100b. The tunneling structure 100c further includes a first tunneling layer 100c1 and a second tunneling layer 100c2, as shown in Figure 2, where the first tunneling layer 100c1 is located between the second tunneling layer 100c2 and the first light-emitting layer 100a. The first tunneling layer 100c1 and the second tunneling layer 100c2 may have different conductivity modes. In one embodiment, the first tunneling layer 100c1 and the second tunneling layer 100c2 have a high doping concentration higher than 1 × ^{10¹⁸ cm⁻³} , for example, a doping concentration between 5 × ^{10¹⁸ cm⁻³} and 1 × ^{10²² cm⁻³} (inclusive). In this embodiment, the first luminescent layer 100a and the second luminescent layer 100b are connected in series by the tunneling structure 100c.

According to one embodiment, the semiconductor epitaxial structure 100 may only have a first light-emitting layer 100a without a second light-emitting layer 100b and a tunneling structure 100c. In this case, the second semiconductor contact layer 101b may be located on the second semiconductor structure 100a3 and in direct contact with the second semiconductor structure 100a3.

The first semiconductor structure 100a1 and the second semiconductor structure 100a3 have opposite conduction modes. For example, the first semiconductor structure 100a1 is a p-type semiconductor, and the second semiconductor structure 100a3 is an n-type semiconductor; or the first semiconductor structure 100a1 is an n-type semiconductor, and the second semiconductor structure 100a3 is a p-type semiconductor. The first tunneling layer 100c1 and the second tunneling layer 100c2 may have opposite conduction modes. For example, the first tunneling layer 100c1 is an n-type semiconductor, and the second tunneling layer 100c2 is a p-type semiconductor; or the first tunneling layer 100c1 is a p-type semiconductor, and the second tunneling layer 100c2 is an n-type semiconductor. The first tunneling layer 100c1 and the second semiconductor structure 100a3 may have the same conduction mode. The third semiconductor structure 100b1 and the fourth semiconductor structure 100b3 have opposite conduction types. For example, the third semiconductor structure 100b1 can be a p-type semiconductor and the fourth semiconductor structure 100b3 can be an n-type semiconductor; or the third semiconductor structure 100b1 can be an n-type semiconductor and the fourth semiconductor structure 100b3 can be a p-type semiconductor. The third semiconductor structure 100b1 and the second tunneling layer 100c2 can have the same conduction type. The aforementioned n-type semiconductor is, for example, a tellurium (Te) or silicon (Si) doped semiconductor, and the p-type semiconductor is, for example, a carbon (C), zinc (Zn), or magnesium (Mg) doped semiconductor.

In one embodiment, the first semiconductor structure 100a1, the second semiconductor structure 100a3, the third semiconductor structure 100b1, and the fourth semiconductor structure 100b3 may each comprise a single layer or multiple layers. The first active structure 100a2 and the second active structure 100b2 may, for example, each comprise a multiple quantum well structure. The first semiconductor structure 100a1, the first active structure 100a2, the second semiconductor structure 100a3, and the first semiconductor contact layer 101a may each comprise a binary, ternary, or quaternary III-V semiconductor material of the same series. The third semiconductor structure 100b1, the fourth semiconductor structure 100b3, the second active structure 100b2, and the second semiconductor contact layer 101b may each comprise a binary, ternary, or quaternary III-V semiconductor material of the same series. The aforementioned binary, ternary, or quaternary III-V group semiconductor materials include, for example, the AlInGaAs series, AlGaInP series, AlInGaN series, or InGaAsP series. The AlInGaAs series can be represented as (Al _x1 In _(1-x1) ) _1-x2 Ga _x2 As; the AlInGaP series can be represented as (Al _y1 In _(1-y1) ) _1-y2 Ga _y2 P; the AlInGaN series can be represented as (Al _z1 In _(1-z1) ) _1-z2 Ga _z2 N; and the InGaAsP series can be represented as In _z3 Ga _1-z3 As _z4 P _1-z4 . Wherein, 0≦x ₁ ,y ₁ ,z ₁ ,x ₂ ,y ₂ ,z ₂ ,z ₃ ,z ₄ ≦1. The first active structure 100a2 and the second active structure 100b2 may contain materials from the same or different series.

The substrate 114 may be a conductive substrate, comprising conductive materials such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge), or silicon (Si).

The insulating layer 104 comprises an electrical insulating material, such as an oxide or a fluoride. The oxide may be, for example, silicon dioxide ( _SiO₂x ), and the fluoride may be, for example, magnesium fluoride ( _MgF₂x ). In one embodiment, the insulating layer 104 comprises an electrical insulating material, such as a low refractive index electrical insulating material with a refractive index less than 1.4, such as magnesium fluoride ( _MgF₂x ). The metal oxide layer 108 may be transparent and includes, but is not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), or gallium aluminum zinc oxide (GAZO). The reflective layer 110 is located on the bonding layer 112 and may have a reflectivity of at least 80% relative to the light emitted by the semiconductor epitaxial structure 100. The reflective layer 110 comprises a conductive material, such as a metal or alloy. The metal may include, for example, silver (Ag), gold (Au), or aluminum (Al). The bonding layer 112 may comprise a conductive material, such as a metal or alloy. According to one embodiment, the material used to form the bonding layer 112 has a melting point below 400°C to facilitate bonding of the substrate 114 and the reflective layer 110 by, for example, welding, eutectic bonding, or hot pressing.

The materials of the first electrode 106 and the second electrode 116 may include, for example, metal oxides, metals, or alloys. The metal oxides may include, for example, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO). The metals may include, for example, germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni), or copper (Cu). The alloy may include, for example, at least two metals selected from the group consisting of the aforementioned metals, such as germanium-nickel (GeAuNi), beryllium (BeAu), germanium (GeAu), and zinc (ZnAu).

Figure 4 is a schematic cross-sectional view of the semiconductor device 10A according to one embodiment of this disclosure. The main difference between semiconductor device 10A and semiconductor device 10 lies in the distribution of the metal contact structure 102, the insulating layer 104, and the metal oxide layer 108. In this embodiment, the metal oxide layer 108 overlaps with both the insulating layer 104 and the metal contact structure 102 in the vertical direction Y. The metal oxide layer 108 can be continuously distributed below the semiconductor epitaxial structure 100, located between the reflective layer 110 and the metal contact structure 102 and the insulating layer 104. The thickness of the metal oxide layer 108 can be greater than, less than, or equal to the thickness of the metal pillar 102a. As shown in Figure 4, a portion of the insulating layer 104 covers the first surface s1 where the metal pillar 102a and the metal oxide layer 108 meet. In this embodiment, an electrical connection can be formed by the portion of the metal pillar 102a not covered by the insulating layer 104 directly contacting the metal oxide layer 108. In one embodiment, the metal oxide layer 108 may undergo a polishing process to make it flush with the insulating layer 104 as shown in Figure 2. The reflective layer 110 is in direct contact with both the metal oxide layer 108 and the insulating layer 104, but not with the metal pillar 102a.

The positions, relative relationships, material compositions, and structural variations of the other layers or structures in semiconductor device 10A have been described in detail in previous embodiments and will not be repeated here.

Figure 5 is a schematic cross-sectional view of a semiconductor device 10B according to an embodiment of this disclosure. In the semiconductor device 10B, the metal contact structure 102 and the insulating layer 104 are not in direct contact but are separated by a distance. As shown in Figure 5, the metal contact structure 102 and the insulating layer 104 do not overlap in the vertical direction Y, but overlap in the horizontal direction X. In some embodiments, the thickness of the metal oxide layer 108 may be greater than, less than, or equal to the thickness of the metal pillar 102a. In this embodiment, as shown in Figure 5, the thickness of the metal pillar 102a may be greater than the thickness of the insulating layer 104. As shown in Figure 5, the first surface s1 of the metal pillar 102a and the surface 104s of the insulating layer 104 that contacts the metal oxide layer 108 are not flush. In this embodiment, the metal oxide layer 108 directly contacts the first surface s1 and the side surface s3 of the metal pillar 102a, thereby forming an electrical connection between the metal pillar 102a and the metal oxide layer 108. In another embodiment, the metal oxide layer 108 in Figure 5 is further subjected to a polishing process, making one surface of the metal oxide layer 108 flush with the first surface s1 of the metal pillar 102a. The reflective layer 110 is in direct contact with both the metal oxide layer 108 and the metal pillar 102a, but not with the insulating layer 104.

In another embodiment, the thickness of the metal pillar 102a is substantially equal to the thickness of the insulating layer 104, and the first surface s1 and surface 104s are substantially flush. In this embodiment, the metal oxide layer 108 may undergo a further polishing process to make the metal oxide layer 108 flush with the insulating layer 104 and the metal pillar 102a. The reflective layer 110 is in direct contact with the metal oxide layer 108, the metal pillar 102a, and the insulating layer 104. The metal oxide layer 108 is located between the insulating layer 104 and the metal pillar 102a. The metal contact structure 102, the insulation layer 104, and the metal column 102a overlap in the horizontal direction X but do not overlap in the vertical direction Y.

The positions, relative relationships, material compositions, and structural variations of the other layers or structures in semiconductor device 10B have been described in detail in previous embodiments and will not be repeated here.

Figure 6 is a cross-sectional schematic diagram of a semiconductor device 10C according to an embodiment of this disclosure. The semiconductor device 10C may have a patterned first semiconductor contact layer 101a. As shown in Figure 6, the first semiconductor contact layer 101a may include multiple mutually separated portions 101a1, each portion 101a1 overlapping and directly contacting the metal pillar 102a in the vertical direction Y. In this embodiment, an insulating layer 104 simultaneously covers the side surfaces of each portion 101a1 and the first surface s1 and side surface s3 of the metal pillar 102a. The metal oxide layer 108 directly contacts the insulating layer 104 but does not directly contact the first semiconductor contact layer 101a or the metal contact structure 102. As shown in Figure 6, in cross-section, the portions 101a1 and/or metal pillars 102a of the first semiconductor contact layer 101a can be generally inverted trapezoidal in shape. The width of the portions 101a1 and/or metal pillars 102a of the first semiconductor contact layer 101a can gradually decrease from the side closer to the first semiconductor structure 100a1 towards the side farther away from the first semiconductor structure 100a1. In this embodiment, the semiconductor epitaxial structure 100 and the reflective layer 110 can be electrically connected through the patterned first semiconductor contact layer 101a and the metal contact structure 102. Since the first semiconductor contact layer 101a absorbs light emitted by the semiconductor epitaxial structure 100, the patterned first semiconductor contact layer 101a can reduce light absorption and increase light extraction efficiency.

The positions, relative relationships, material compositions, and structural variations of the other layers or structures in semiconductor device 10C have been described in detail in previous embodiments and will not be repeated here.

Figure 7 is a cross-sectional schematic diagram of the packaging structure 20 of a semiconductor device according to an embodiment of this disclosure. Referring to Figure 7, the packaging structure 20 includes a semiconductor device 10, a packaging substrate 21, a first conductive structure 23, a conductive line 25, a second conductive structure 26, and a packaging layer 28. The packaging substrate 21 may contain ceramic or glass material. The packaging substrate 21 has a plurality of through-holes 22. The through-holes 22 may be filled with a conductive material such as a metal to facilitate electrical conduction and/or heat dissipation. The first conductive structure 23 is located on one side of the surface of the packaging substrate 21 and also contains a conductive material, such as a metal. The second conductive structure 26 is located on the other side of the surface of the packaging substrate 21. In this embodiment, the second conductive structure 26 includes a third contact pad 26a and a fourth contact pad 26b, and the third contact pad 26a and the fourth contact pad 26b can be electrically connected to the first conductive structure 23 through the through-hole 22. In one embodiment, the second conductive structure 26 may further include a thermal pad (not shown), for example, located between the third contact pad 26a and the fourth contact pad 26b. The semiconductor element 10 is located on the first conductive structure 23 and may have the structure described in any embodiment of this disclosure or a variation thereof. In this embodiment, the first conductive structure 23 includes a first contact pad 23a and a second contact pad 23b. The semiconductor element 10 is electrically connected to the second contact pad 23b of the first conductive structure 23 via a conductive wire 25. The material of the conductive wire 25 may include metals, such as gold, silver, copper, aluminum, or alloys of the above elements. A packaging layer 28 covers the semiconductor element 10 to protect it. The packaging layer 28 may contain a resin material such as epoxy resin or silicone resin. In one embodiment, the packaging layer 28 may further include a plurality of wavelength-converting particles (not shown) to convert the light emitted by the semiconductor epitaxial structure 100.

Based on the above, this disclosure provides a semiconductor device and its packaging structure, the design of which helps improve the optoelectronic characteristics of the semiconductor device. The semiconductor device or semiconductor packaging structure disclosed herein can be applied to products in fields such as lighting, medical, display, communication, sensing, and power systems, including lamps, surveillance cameras, mobile phones, tablets, automotive dashboards, televisions, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signals, outdoor displays, and medical equipment.

Although the present invention has been disclosed above by way of embodiments, some modifications or changes may be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. The above embodiments may be combined or substituted with each other where appropriate, and are not limited to the specific embodiments described. For example, the parameters of a specific component or the connection relationship between a specific component and other components disclosed in one embodiment may also be applied to other embodiments, and all shall fall within the scope of protection of the present invention.

10: Semiconductor Devices

100: Semiconductor epitaxial structure

100a: First luminescent layer

100b: Second luminescent layer

100b1: Third Semiconductor Structure

100b2: Second active structure

100b3: Fourth Semiconductor Structure

100c: Tunneling structure

100c1: First tunnel level

100c2: Second tunnel level

100a1: First Semiconductor Structure

100a2: First active structure

100a3: Second Semiconductor Structure

101a: First semiconductor contact layer

101b: Second semiconductor contact layer

101s: Lower surface

102: Metal Contact Structure

102a: Metal Column

104: The Insulation Layer

106: First Electrode

106a: Electrode Pad

106b: Extended electrode

106c: Connector

108: Metal oxide layer

110: Reflective layer

110a: Upper surface

112: Bonding layer

114: Base

116: Second Electrode

R: Region

W1: Width

X: Horizontal direction

Y: Vertical direction

Claims (10)

A semiconductor device, comprising: a semiconductor epitaxial structure including an active structure and a first semiconductor structure located beneath the active structure, the first semiconductor structure including a first semiconductor contact layer having a lower surface; a metal contact structure directly contacting the lower surface and including a plurality of mutually separated metal pillars, one of the plurality of metal pillars including a first surface, a second surface, and a side surface; an insulating layer directly contacting the lower surface and not directly contacting the metal contact structure but separated by a distance; and a metal oxide layer located beneath the first semiconductor contact layer and overlapping the metal contact structure in a horizontal direction; The metal contact structure does not overlap with the insulating layer in a vertical direction, but overlaps in a horizontal direction. The second surface directly contacts the lower surface of the semiconductor contact layer, the first surface is opposite the second surface, and the side surface connects the first surface and the second surface. The semiconductor device as described in claim 1, wherein the first surface and one of the surfaces of the metal oxide layer are not flush. The semiconductor device as described in claim 1, wherein the thickness of the metal oxide layer is greater than or less than the thickness of one of the plurality of metal pillars. The semiconductor device as described in claim 1, wherein the metal oxide layer directly contacts the first surface and the side surface. The semiconductor element as described in claim 1, wherein the first semiconductor contact layer comprises a plurality of mutually separated portions, each portion overlapping and directly contacting each of the plurality of metal pillars in the vertical direction. As described in claim 1, in a semiconductor element, the width of one of the plurality of metal pillars may gradually decrease from the side closer to the first semiconductor structure toward the side farther from the first semiconductor structure. The semiconductor device as described in claim 1, wherein the width of each of the metal pillars is in the range of greater than 0 µm and less than 10 µm. The semiconductor device as described in claim 1 further includes a reflective layer located beneath the metal oxide layer. The semiconductor device as described in claim 1, wherein the metal contact structure includes a main contact layer that is in direct contact with the first semiconductor contact layer, and neither beryllium nor zinc is present in the main contact layer. A packaging structure for a semiconductor device includes: a packaging substrate; a semiconductor device as described in any one of claims 1-9, disposed on the packaging substrate; and a packaging layer covering the semiconductor device.