TWI911785B - Semiconductor device - Google Patents

Abstract

The present disclosure provides a semiconductor device which includes an active structure, a first semiconductor layer, a second semiconductor layer, an intermediate layer, a transition layer and a contact layer. The active structure includes an active region. The first semiconductor layer and the second semiconductor layer are on two sides of the active structure. The intermediate layer is located between the second semiconductor layer and the active structure. The transition layer is located on the second semiconductor layer. The contact layer is located on the transition layer. The second semiconductor layer includes a first dopant. The first semiconductor layer includes a second dopant different from the first dopant.

Description

semiconductor devices

This invention relates to semiconductor devices, and more particularly to semiconductor light-emitting devices, such as light-emitting diodes.

Semiconductor devices have a wide range of applications, and the development and research of related materials are ongoing. For example, III-V semiconductor materials containing group III and group V elements can be used in various optoelectronic semiconductor devices such as light-emitting diodes (LEDs), laser diodes (LDs), photoelectric detectors, or solar cells. They can also be used as power devices such as switches or rectifiers in fields such as lighting, medical applications, displays, communications, sensing, and power supply systems. As one of the semiconductor light-emitting elements, LEDs have advantages such as low power consumption and long lifespan, and are therefore widely used in various fields. With the development of technology, there is still a great demand for technological research and development in semiconductor devices.

This invention provides a semiconductor device comprising an active structure, a first semiconductor layer, a second semiconductor layer, an intermediate layer, a transition layer, and a contact layer. The active structure includes an active region. The first and second semiconductor layers are located on either side of the active structure. The intermediate layer is located between the second semiconductor layer and the active structure. The transition layer is located on the second semiconductor layer. The contact layer is located on the transition layer. The second semiconductor layer includes a first dopant. The first semiconductor layer includes a second dopant different from the first dopant. The contact layer includes a ternary III-V semiconductor material. The second semiconductor layer includes a binary III-V semiconductor material. The active region includes a quaternary semiconductor material.

In one embodiment, the quaternary semiconductor material comprises InGaAsP or AlGaInAs.

In one embodiment, the transition layer and the contact layer contain at least two identical elements selected from the group consisting of indium (In), gallium (Ga) and arsenic (As).

In one embodiment, the ternary III-V semiconductor material comprises InGaAs.

In one embodiment, the semiconductor device emits radiation with a peak wavelength between 800 nm and 2000 nm.

In one embodiment, the active region includes a first dopant, and the doping concentration of the first dopant in the active region is less than or equal to 1 x ^{10¹⁸ cm⁻³} .

In one embodiment, the semiconductor device further includes a substrate located below the first semiconductor layer, and the substrate has a thickness greater than or equal to 60 µm and less than or equal to 250 µm.

In one embodiment, when the semiconductor device emits radiation greater than 1000 nm, the substrate has a transmittance of greater than 30% to the radiation, or an absorption rate of less than 30%.

In one embodiment, a reflective structure is also included, located between the substrate and the first semiconductor layer, and the reflective structure includes a first metal layer, a second metal layer and a third metal layer.

The present invention provides a packaging structure for a semiconductor device, comprising a carrier, a semiconductor device disposed on the carrier, and a packaging material layer covering the semiconductor device.

The following embodiments will be illustrated with drawings to illustrate the concepts of the present invention. In the drawings or description, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shapes or dimensions of the components in the drawings are illustrative only and are not actually limited thereto. It should be noted that components not shown or described in the drawings may be in forms known to those skilled in the art.

Unless otherwise specified, the general formula InGaAs represents In _z1 Ga _1-z1 As, where 0 < z1 <1; the general formula InAlAs represents In _z2 Al _1-z2 As, where 0 < z2 <1; InGaAsP represents In _z3 Ga _1-z3 As _z4 P _1-z4 , where 0 < z3 < 1, 0 < z4 <1; AlGaInAs represents (Al _z5 Ga _(1-z5) ) _z6 In _1-z6 As, where 0 < z5 < 1, 0 < z6 <1; the general formula AlGaInP represents (Al _z7 Ga _(1-z7) ) _z8 In _1-z8 P, where 0 < z7 < 1, 0 < z8 < 1. The layer composition and dopants of the semiconductor devices disclosed herein can be analyzed using any suitable method, such as secondary ion mass spectrometry (SIMS), and the thickness of each layer can also be analyzed using any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscopy (SEM). Furthermore, the dopants mentioned in this disclosure may be intentionally or unintentionally added. Intentional addition is, for example, through in-situ doping during epitaxial growth and/or through implantation using P-type or N-type dopants after epitaxial growth. Unintentional addition is, for example, due to processes occurring during fabrication.

Those skilled in the art will understand that additional components can be added to the embodiments described below. For example, unless otherwise specified, a description such as "the first layer (or structure) is located on the second layer (or structure)" can include embodiments where the first layer (or structure) and the second layer (or structure) are in direct contact, or embodiments where there are other structures between the first layer (or structure) and the second layer (or structure) and they are not in direct contact with each other. Furthermore, it should be understood that the vertical relationship between the layers (or structures) may change depending on the viewing angle. Furthermore, in this disclosure, the statement that a layer or structure is "substantially composed of X" indicates that X is the main component of the layer or structure, but does not exclude the possibility that the layer or structure contains dopants or unavoidable impurities.

Figure 1 is a top view of the structure of a semiconductor device 100 according to an embodiment of this disclosure. Figure 2 is a schematic cross-sectional view of the semiconductor device 100 in Figure 1 along line A-A'. As shown in Figure 1, the semiconductor device 100 is rectangular when viewed from above. In one embodiment, the length and width of the semiconductor device 100 may be greater than or equal to 100 µm and less than or equal to 500 µm, for example, 200 µm, 250 µm, 300 µm, 350 µm, 400 µm, or 450 µm. In one embodiment, the length and width of the semiconductor device 100 are approximately equal. As shown in Figure 2, the semiconductor device 100 of this embodiment includes a substrate 10, an active structure 12, a first semiconductor layer 14, a second semiconductor layer 16, a first electrode 18, and a second electrode 20. In some embodiments, the first semiconductor layer 14, the active structure 12, and the second semiconductor layer 16 can be grown on or bonded to the substrate 10 by epitaxy; that is, the substrate 10 can be a growth substrate or a non-growth substrate. The substrate 10 can be used to support semiconductor stacks and other layers or structures located thereon. The active structure 12 is located on the first side 10a of the substrate 10. The second electrode 20 is located on the second side 10b of the substrate 10. In this embodiment, the second electrode 20 is adjacent to the substrate 10 and directly contacts the surface of the substrate 10. The first semiconductor layer 14 is located below the active structure 12. As shown in Figure 2, the first semiconductor layer 14 is located between the substrate 10 and the active structure 12. The second semiconductor layer 16 is located on the active structure 12. The first electrode 18 is located on the second semiconductor layer 16. The semiconductor device 100 emits radiation during operation.

In one embodiment, the substrate 10 is a growth substrate and may be a conductive substrate, comprising conductive materials such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge), or silicon (Si). The substrate 10 may be transparent, translucent, or opaque to the aforementioned radiation. For example, when the radiation emitted by the semiconductor device 100 is greater than 1000 nm, the substrate 10 preferably has a transmittance greater than 30% or an absorption rate of less than 30% to the aforementioned radiation. In some embodiments, the substrate 10 may have a thickness greater than or equal to 60 µm and less than or equal to 250 µm, such as 100 µm, 130 µm, 140 µm, 150 µm, 160 µm, 170 µm, 180 µm, 200 µm, 230 µm.

Semiconductor device 100 may include a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantum well (MQW) structure. The radiation emitted by semiconductor device 100 may be cohomological or nonhomological visible or invisible light, preferably red or infrared light, such as near-infrared (NIR) light. When the aforementioned radiation is near-infrared light, it may have a peak wavelength between 800 nm and 2000 nm (inclusive), for example: approximately 810 nm, 850 nm, 910 nm, 940 nm, 1050 nm, 1070 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1450 nm, 1500 nm, 1550 nm, 1600 nm, 1650 nm, 1700 nm, etc. In one embodiment, the semiconductor device 100 can only emit non-coherent radiation and cannot emit coherent radiation, meaning that the semiconductor device 100 does not have a threshold current (Ith).

In this embodiment, the active structure 12 includes a first confinement layer 120, a second confinement layer 122, and an active region 124 located between the first confinement layer 120 and the second confinement layer 122. The active structure 12 may have a first width w1, and the substrate 10 may have a second width w2 greater than the first width w1. In one embodiment, the first confinement layer 120, the active region 124, and the second confinement layer 122 all contain ternary or quaternary semiconductor materials. The ternary or quaternary semiconductor materials may contain aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In), such as InGaAs, InGaAsP, or AlGaInAs. In one embodiment, the first confinement layer 120, the active region 124, and the second confinement layer 122 all contain arsenic (As). Preferably, the first confinement layer 120, the active region 124, and the second confinement layer 122 are substantially composed of a quaternary semiconductor material, such as InGaAsP or AlGaInAs.

In one embodiment, the first confinement layer 120 comprises In _x1 Ga _1-x1 As _y1 P _1-y1 , where 0 < x1 < 1, 0 < y1 <1; preferably, 0.5 ≤ x1 ≤ 0.9 or/and 0.1 ≤ y1 ≤ 0.4. In one embodiment, the second confinement layer 122 comprises In _x2 Ga _1-x2 As _y2 P _1-y2 , where 0 < x2 < 1, 0 < y2 <1; preferably, 0.5 ≤ x2 ≤ 0.9 or/and 0.1 ≤ y2 ≤ 0.4. In one embodiment, the active region 124 comprises In _x3 Ga _1-x3 As _y3 P _1-y3 , where 0 < x3 < 1, 0 < y3 <1; preferably, 0.5 ≤ x3 ≤ 0.9 or/and 0.5 ≤ y3 ≤ 0.9. In one embodiment, x1 > x3 and x2 > x3, y3 > y1 and y3 > y2. Preferably, the band gap of the first confinement layer 120 and the second confinement layer 122 is larger than the band gap of the active region 124. In one embodiment, the first confinement layer 120 has a first thickness t1, the second confinement layer 122 has a second thickness t2, and the active region 124 has a third thickness t3, the third thickness t3 being greater than the first thickness t1 or/and the second thickness t2. In one embodiment, the third thickness t3 can be more than 3 times but less than 10 times the first thickness t1 or the second thickness t2, for example, 4 times, 5 times, 6 times, 7 times, 8 times, or 9 times. By having a relatively thicker active region 124, the luminescent volume of the semiconductor device can be increased, thereby improving the luminescence efficiency. In one embodiment, the first thickness t1 and the second thickness t2 can be less than or equal to 90 nm and greater than 1 nm, for example, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, 20 nm, or 10 nm. In some embodiments, at a fixed operating current, the forward voltage (Vf) of a semiconductor device with a first thickness t1 or a second thickness t2 greater than 90 nm may be larger than that of a semiconductor device with a first thickness t1 or a second thickness t2 not greater than 90 nm.

The first semiconductor layer 14 and the second semiconductor layer 16 are respectively located on both sides of the active structure 12 and adjacent to the active structure 12. In one embodiment, the first semiconductor layer 14 has a fourth thickness t4, and the second semiconductor layer has a fifth thickness t5 greater than or equal to the fourth thickness t4. In one embodiment, the fifth thickness t5 may be more than 2 times and less than 10 times the fourth thickness t4, for example, 3 times, 4 times, 5 times, 6 times, 7 times, 8 times, or 9 times. The first semiconductor layer 14 and the second semiconductor layer 16 may respectively contain binary, ternary, or quaternary III-V group semiconductor materials, preferably containing aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In), and may not contain nitrogen (N). Preferably, the first semiconductor layer 14 and the second semiconductor layer 16 each comprise at least two elements selected from the group consisting of aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P) and indium (In).

In one embodiment, the first semiconductor layer 14 and the second semiconductor layer 16 respectively comprise binary or ternary semiconductor materials, such as InP, GaAs, InGaAs, or InAlAs. Preferably, the first semiconductor layer 14 and the second semiconductor layer 16 are substantially composed of binary or ternary semiconductor materials (such as InP, GaAs, InGaAs, or InAlAs). In one embodiment, the first semiconductor layer 14 and the second semiconductor layer 16 can be doped by in-situ doping during epitaxial growth and/or by implanting with a dopant after epitaxial growth. The second semiconductor layer 16 may include a first dopant to give it a first conductivity type. The first semiconductor layer 14 may include a second dopant to give it a second conductivity type. The second conductivity type is different from the first conductivity type. The first conductivity type is, for example, p-type and the second conductivity type is, for example, n-type to provide holes or electrons, or the first conductivity type is, for example, n-type and the second conductivity type is, for example, p-type to provide electrons or holes. In one embodiment, the first or second dopant may be magnesium (Mg), zinc (Zn), silicon (Si), or tellurium (Te).

In one embodiment, the active structure 12 includes a first dopant. Specifically, the first dopant is distributed at least in the active region 124. In one embodiment, the active region 124 has a uppermost surface and a lowermost surface, and the first dopant is distributed from the uppermost surface to the lowermost surface of the active region 124. In some embodiments, the active region 124 includes a plurality of alternating well layers and a plurality of barrier layers, and the first dopant is distributed in each well layer and each barrier layer. Furthermore, the aforementioned uppermost surface is the upper surface of the uppermost layer (well layer or barrier layer) of the active region 124, and the aforementioned lowermost surface is the lower surface of the lowermost layer (well layer or barrier layer) of the active region 124. Preferably, the first dopant is continuously distributed in the active structure 12 (as shown by line S1 in region II of Figure 4). In one embodiment, the distribution range of the first dopant in the active structure 12 may be between the first confining layer 120 and the second confining layer 122 (inclusive of both). In other words, in one embodiment, the first confining layer 120, the active region 124, and the second confining layer 122 all have the first dopant. In one embodiment, the distribution range of the first dopant in the active structure 12 is only located in the active region 124 and the second confining layer 122, and the first confining layer 120 does not have the first dopant. In one embodiment, the first dopant is distributed only within the active region 124 of the active structure 12, while the second confinement layer 122 and the first confinement layer 120 do not contain the first dopant. In the active region 124, the doping concentration of the first dopant can range from 5 x ^{10¹⁵ cm⁻³} to 1.5 x ^{10¹⁸ cm⁻³} , preferably less than or equal to 1 x ^{10¹⁸ cm⁻³} , more preferably less than or equal to 5 x ^{10¹⁷ cm⁻³} , and even more preferably greater than or equal to 1 x ^{10¹⁶ cm⁻³} , more preferably greater than or equal to 5 x ^{10¹⁶ cm⁻³} , and even more preferably greater than or equal to 1 x ^{10¹⁷ cm⁻³} . In some embodiments, by including a first dopant in the active structure 12, device characteristics can be further improved, such as increasing luminous efficiency. Specifically, the first dopant can diffuse from the second semiconductor layer 16 into the first confinement layer 120, the active region 124, and/or the second confinement layer 122. That is, the first dopant is not intentionally added to the first confinement layer 120, the active region 124, and/or the second confinement layer 122. For example, the first dopant may not be added at all during the epitaxial formation of the first confinement layer 120, the active region 124, and/or the second confinement layer 122. Alternatively, the first dopant may be intentionally added to the first confinement layer 120, the active region 124, and/or the second confinement layer 122. In another embodiment, the active structure 12 may substantially consist of the active region 124, meaning that the active structure 12 does not include the first confinement layer 120 and the second confinement layer 122. This simplifies the manufacturing process and contributes to the stability of device production. In this case, the first dopant may be continuously distributed in the active region 124 by diffusion or intentional addition.

As previously mentioned, the first semiconductor layer 14 can provide electrons or holes. Furthermore, the first semiconductor layer 14 can also serve as a window layer (light extraction layer) to increase light extraction efficiency. According to one embodiment, the doping concentration of the second dopant in the first semiconductor layer 14 can be in the range of 1 x ^{10¹⁵ cm⁻³} to 1 x ^{10¹⁹ cm⁻³} , preferably less than or equal to 1 x ^{10¹⁸ cm⁻³} , more preferably less than or equal to 5 x ^{10¹⁷ cm⁻³} , and even more preferably greater than or equal to 1 x ^{10¹⁶ cm⁻³} . In some embodiments, the maximum doping concentration of the second dopant in the first semiconductor layer 14 is greater than or equal to the maximum doping concentration of the first dopant in the active region 124. The doping concentration of the first dopant in the first semiconductor layer 14 is less than or equal to the doping concentration of the second dopant. Preferably, at all locations in the first semiconductor layer 14, the doping concentration of the first dopant is less than the doping concentration of the second dopant (see Figure 4). In one embodiment, the doping concentration of the first dopant in the second semiconductor layer 16 may be less than or equal to the maximum doping concentration of the second dopant in the first semiconductor layer 14. In one embodiment, the doping concentration of the first dopant in the second semiconductor layer 16 is greater than or equal to the doping concentration of the first dopant in the active region 124. The doping concentration of the first dopant in the second semiconductor layer 16 can be in the range of 1 x ^{10¹⁷ cm⁻³} to 1 x ^{10¹⁹ cm⁻³} , preferably greater than or equal to 5 x ^{10¹⁷ cm⁻³} , more preferably greater than or equal to 1 x ^{10¹⁸ cm⁻³} , and more preferably less than or equal to 5 x ^{10¹⁸ cm⁻³} .

The first electrode 18 and the second electrode 20 are used for electrical connection to an external power supply and the active structure 12. The first electrode 18 may include a main electrode 18a and a plurality of extended electrodes 18b. As shown in Figure 1, the main electrode 18a is located at the center of the semiconductor device 100, and the plurality of extended electrodes 18b surround the main electrode 18a and are connected to the main electrode 18a. In this embodiment, each extended electrode 18b is T-shaped. The materials of the first electrode 18 and the second electrode 20 may include metal oxide materials, metals, or alloys. Metal oxide materials include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO), etc. Metals that can be listed include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni), copper (Cu), etc. The alloy may contain at least two of the metals selected from the group consisting of the above metals, such as nickel-sterile metal (GeAuNi), beryllium metal (BeAu), sterile metal (GeAu), zinc metal (ZnAu), etc.

Figure 3 is a schematic cross-sectional view of a semiconductor device 200 according to an embodiment of this disclosure. The semiconductor device 200 differs from semiconductor device 100 in that it further includes a window layer 17 and an intermediate layer 24. The window layer 17 is located between the second semiconductor layer 16 and the first electrode 18, and can serve as a light extraction layer to improve the light emission efficiency of the device. The window layer 17 may contain binary, ternary, or quaternary semiconductor materials, preferably aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In), and may not contain nitrogen (N). For example, it may contain phosphorus (P), indium (In), gallium (Ga), or arsenic (As). For instance, the window layer 17 may contain InP, GaAs, InAlAs, or AlGaInAs. The window layer 17 and the second semiconductor layer 16 may contain the same or different binary, ternary, or quaternary III-V group semiconductor materials. Preferably, the window layer 17 is substantially composed of binary, ternary, or quaternary semiconductor materials, such as InP, GaAs, InAlAs, or AlGaInAs. The window layer 17 may also contain a first dopant. Preferably, the dopant concentration of the first dopant in the window layer 17 is higher than the dopant concentration of the first dopant in the second semiconductor layer 16. In one embodiment, the window layer 17 may have a first region and a second region (not shown), with the first region being closer to the first electrode 18 than the second region, and preferably, the concentration of the first dopant in the first region is higher than the concentration of the first dopant in the second region. This further improves the electrical contact characteristics between the window layer 17 and the first electrode 18.

The intermediate layer 24 may be located between the second semiconductor layer 16 and the active structure 12, for example, between the second semiconductor layer 16 and the second confinement layer 122. The intermediate layer 24 may contain a binary semiconductor material, preferably aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In), and may not contain nitrogen (N). For example, it may contain phosphorus (P), indium (In), or gallium (Ga) and arsenic (As). In one embodiment, the intermediate layer 24 and the second semiconductor layer 16 contain the same binary III-V group semiconductor material, such as InP or GaAs. Preferably, the intermediate layer 24 is substantially composed of a binary semiconductor material, such as InP or GaAs. In some embodiments, when the intermediate layer and the second semiconductor layer 16 contain the same semiconductor material, the interface between the intermediate layer 24 and the second semiconductor layer 16 may not be obvious under SEM or TEM analysis, i.e., the intermediate layer 24 and the second semiconductor layer 16 as a whole present a structure similar to a single layer.

In some embodiments, the intermediate layer 24 may also include a first dopant. The first dopant may enter the intermediate layer 24 from the second semiconductor layer 16 by diffusion, for example, it is not formed by intentionally adding the first dopant to the intermediate layer 24, but rather by not adding the first dopant at all during the epitaxial formation of the intermediate layer 24. Specifically, the intermediate layer 24 may serve as a diffusion control layer to adjust the diffusion distance of the first dopant towards the active structure 12 and the first semiconductor layer 14. In some embodiments, when the first dopant diffuses excessively through the active structure 12 to the first semiconductor layer 14, resulting in a high dopant concentration (e.g., above 1 x ^{10¹⁷ cm⁻³} ) in the first semiconductor layer 14, it may lead to device failure. Therefore, it is preferable that the dopant concentration of the first dopant in the first semiconductor layer 14 is less than 1 x ^{10¹⁷ cm⁻³} , more preferably less than 5 x ^{10¹⁶ cm⁻³} . In some embodiments, the intermediate layer 24 may have a thickness in the range of 30 nm to 250 nm, such as about 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm or 240 nm.

In some embodiments, when the thickness of the intermediate layer 24 is less than 30 nm, the effect of controlling diffusion is less significant, resulting in a high dopant concentration (e.g., 1 x ^{10¹⁷ cm⁻³} or more) of the first dopant in the first semiconductor layer 14. In some embodiments, such as when the active structure 12 is substantially composed of the active region 124 (i.e., the active structure 12 does not include the first confinement layer 120 and the second confinement layer 122), the thickness of the intermediate layer 24 is preferably in the range of 100 nm to 250 nm, more preferably in the range of 150 nm to 250 nm. This allows the semiconductor device to have better luminescence efficiency. In some embodiments, when the active structure 12 includes a first confinement layer 120, an active region 124, and a second confinement layer 122, if the thickness of the intermediate layer 24 exceeds 150 nm, the peak wavelength of the radiation emitted by the semiconductor device may shift. Therefore, it is preferable that the thickness of the intermediate layer 24 is below 150 nm. Based on the above, by providing the intermediate layer 24, it is easier to control the dopant concentration of the first dopant in the active structure 12, thereby adjusting the photoelectric characteristics of the device.

Figure 4 is a SIMS epitaxial structure diagram of a portion of semiconductor device 200. Referring to Figure 4, region I corresponds to the second semiconductor layer 16 and the intermediate layer 24, region II corresponds to the active structure 12, and region III corresponds to the first semiconductor layer 14. Line S1 in Figure 4 represents the dopant concentration curve of the first dopant, and line S2 represents the dopant concentration curve of the second dopant. In this embodiment, the first semiconductor layer 14, the intermediate layer 24, and the second semiconductor layer 16 all contain In and P, and the active structure 12 contains In, Ga, As, and P. In this embodiment, the intermediate layer 24 and the second semiconductor layer 16 are essentially composed of the same semiconductor material. Therefore, the interface between the intermediate layer 24 and the second semiconductor layer 16 is less obvious under SEM or TEM analysis and presents a structure similar to a single layer.

As shown in Figure 4, the first dopant is mainly distributed in regions I and II, with a higher concentration in region I than in region II. The second dopant is mainly distributed in region III, and its maximum concentration ( _CM) in region III is greater than that of the first dopant (BM ₎ in region II. In region III, the concentration of the first dopant is significantly lower than that of the second dopant ( _CM ). In region III, the concentration of the first dopant is, for example, less than 1/10 of the maximum concentration ( _CM) of the second dopant. Region III can be divided into a first region R1 (left side) close to region II and a second region R2 (right side) far from region II. As shown in Figure 4, in the first region R1, the concentration of the first dopant is less than or equal to the concentration of the second dopant; in the second region R2, the concentration of the second dopant is less than or equal to the concentration of the first dopant. The concentration of the first dopant in region III may be less than 1 x ^{10¹⁷ cm⁻³} .

In some embodiments, the semiconductor device 200 may also have a form that includes a window layer 17 but does not include an intermediate layer 24, or only includes an intermediate layer 24 but does not include a window layer 17. The positions, relative relationships, material compositions, and structural variations of the other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

Figure 5 is a schematic cross-sectional view of a semiconductor device 300 according to an embodiment of this disclosure. The difference between the semiconductor device 300 and the semiconductor device 100 in this embodiment is that the semiconductor device 300 further includes an intermediate layer 24, a contact layer 26, and a transition layer 28. In this embodiment, the contact layer 26 is located between the second semiconductor layer 16 and the first electrode 18. By providing the contact layer 26, the electrical contact characteristics between the second semiconductor layer 16 and the first electrode 18 can be further improved. The contact layer 26 may contain binary or ternary semiconductor materials, preferably aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In), and may not contain nitrogen (N). In one embodiment, the contact layer 26 and the second semiconductor layer 16 contain at least one of the same elements, such as indium (In), gallium (Ga), or arsenic (As). In one embodiment, the contact layer 26 contains a ternary III-V semiconductor material, while the second semiconductor layer 16 contains a binary III-V semiconductor material. In one embodiment, the contact layer 26 contains a binary III-V semiconductor material, while the second semiconductor layer 16 contains a ternary III-V semiconductor material. In one embodiment, the contact layer 26 contains GaAs or InGaAs. Preferably, the contact layer 26 is substantially composed of a binary or ternary semiconductor material (such as GaAs or InGaAs). The contact layer 26 may further include a third dopant, and the dopant concentration of the third dopant in the contact layer 26 may be greater than the dopant concentration of the first dopant in the second semiconductor layer 16. The contact layer 26 may have the same conductivity type (p-type or n-type) as the second semiconductor layer 16. The third dopant may be magnesium (Mg), zinc (Zn), silicon (Si), or tellurium (Te), and may be the same as or different from the first dopant. The concentration of the third dopant in the contact layer 26 may be greater than or equal to 1 x ^{10¹⁸ cm⁻³} , preferably greater than or equal to 2 x ^{10¹⁸ cm⁻³} , for example greater than or equal to 4 x ^{10¹⁸ cm⁻³} , or less than or equal to 2 x ^{10¹⁹ cm⁻³} , preferably less than or equal to 1 x ^{10¹⁹ cm⁻³} .

Specifically, the thickness of the transition layer 28 may be greater than that of the contact layer 26. In one embodiment, the transition layer 28 comprises a quaternary semiconductor material, preferably aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In), and may not contain nitrogen (N). Preferably, the transition layer 28 is substantially composed of a quaternary semiconductor material. In one embodiment, the transition layer 28 and the contact layer 26 contain at least two or more of the same elements, for example, selected from the group consisting of indium (In), gallium (Ga), and arsenic (As). The transition layer 28 may contain the same quaternary semiconductor material as the active region 124. In one embodiment, the transition layer 28 comprises In _x4 Ga _1-x4 As _y4 P _1-y4 , where 0 < x4 < 1, 0 < y4 < 1. Preferably, 0.5 ≤ x4 ≤ 0.9, 0.5 ≤ y4 ≤ 0.9. In one embodiment, when the transition layer 28 comprises In _x4 Ga _1-x4 As _y4 P _1-y4 and the active region 124 comprises In _x3 Ga _1-x3 As _y3 P _1-y3 , preferably x4 ≥ x3 and y4 ≥ y3. In one embodiment, the transition layer 28 may further comprise a fourth dopant. The dopant concentration of the fourth dopant in the transition layer 28 may be greater than or equal to the dopant concentration of the first dopant in the second semiconductor layer 16. The transition layer 28 has the same conductivity type (p-type or n-type) as the second semiconductor layer 16. The fourth dopant can be magnesium (Mg), zinc (Zn), silicon (Si) or tellurium (Te), and can be the same as or different from the first dopant.

In some embodiments, the semiconductor device 300 may also have a form that includes a contact layer 26 but not a transition layer 28, or only includes a transition layer 28 but not a contact layer 26. The positions, relative relationships, material compositions, and structural variations of the other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

Figure 6 is a schematic cross-sectional view of a semiconductor device 400 according to an embodiment of this disclosure. The difference between the semiconductor device 400 and the semiconductor device 200 in this embodiment is that the semiconductor device 400 further includes a reflective structure 30 and an adhesive layer 40. In this embodiment, the substrate 10 is a non-growing substrate, and the first semiconductor layer 14, the second semiconductor layer 16, the active structure 12, the other semiconductor layers, and the reflective structure 30 are bonded to the substrate 10 through the adhesive layer 40.

The reflective structure 30 is located between the adhesive layer 40 and the first semiconductor layer 14. Specifically, the reflective structure 30 can be a single layer or multiple layers. In one embodiment, the reflective structure 30 can reflect radiation emitted by the semiconductor element 400 and project it outwards towards the second semiconductor layer 16. The reflective structure 30 is made of a conductive material and may contain a metal or alloy. Metals include, for example, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W). Alloys may contain at least two selected from the group consisting of the aforementioned metals. In one embodiment, the reflective structure 30 includes at least a first metal layer, a second metal layer, and a third metal layer (not shown). The first metal layer may be adjacent to the first semiconductor layer 14, the second metal layer may be adjacent to the adhesive layer 40, and the third metal layer may be located between the first and second metal layers. According to one embodiment, the materials of the first, second, and third metal layers may respectively include aluminum (Al), gold (Au), silver (Ag), titanium (Ti), or platinum (Pt). Preferably, the first, second, and third metal layers are substantially composed of aluminum (Al), gold (Au), silver (Ag), titanium (Ti), or platinum (Pt), respectively. Preferably, the first, second, and third metal layers are made of different materials. In one embodiment, the reflective structure 30 may include a distributed Bragg reflector structure (DBR).

The adhesive layer 40 is used to connect the substrate 10 and the reflective structure 30. In one embodiment, the adhesive layer 40 may include two or more sublayers (not shown). The adhesive layer 40 is made of conductive material and may include transparent conductive material, metal, or alloy. Transparent conductive materials include, but are not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene, or combinations of the above materials. The metals include, but are not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W). The alloy may contain at least two of the metals selected from the group consisting of the above-mentioned metals.

In another embodiment, similar to Figure 6, the intermediate layer 24 is not located between the second semiconductor layer 16 and the active structure 12, but is located between the first semiconductor layer 14 and the active structure 12. For example, the intermediate layer 24 is located between the first semiconductor layer 14 and the first confinement layer 120. In this case, the distribution of the first dopant and the second dopant in the first semiconductor layer 14 and the intermediate layer 24 can correspond to region I shown in Figure 4, the distribution of the first dopant and the second dopant in the active structure 12 can correspond to region II shown in Figure 4, and the distribution of the first dopant and the second dopant in the second semiconductor layer 16 can correspond to region III shown in Figure 4. That is, the first dopant enters the intermediate layer 24 and the active structure 12 from the first semiconductor layer 14 by diffusion, or enters the intermediate layer 24 and the active structure 12 by doping. The intermediate layer 24 can serve as a diffusion control layer to adjust the distance at which the first dopant diffuses toward the active structure 12 and the second semiconductor layer 16.

Figure 7 is a schematic cross-sectional view of a semiconductor device 500 according to an embodiment of this disclosure. Semiconductor device 500 is similar to semiconductor device 400. Semiconductor device 500 further includes an insulating layer 32 located between the reflective structure 30 and the first semiconductor layer 14. As shown in Figure 7, the insulating layer 32 may cover a portion of the lower surface of the first semiconductor layer 14. In this embodiment, the width of the first semiconductor layer 14 is greater than the width of the active structure 12. The material of the insulating layer 32 may include an oxide insulating material or a non-oxide insulating material. For example, oxide insulating materials may include silicon oxide (SiO _{_x} ) or similar materials; non-oxide insulating materials may include silicon nitride (SiN _{_x} ), benzocyclobutene (BCB), cyclo olefin copolymer (COC), fluorocarbon polymer, calcium fluoride (CaF_₂), or magnesium fluoride (MgF_₂ ). In this embodiment, the first electrode 18 does not overlap with the insulating layer 32 in the vertical direction. In one embodiment, the insulating layer 32 does not overlap with the main electrode 18a of the first electrode 18 in the vertical direction but overlaps with the extended electrode 18b in the vertical direction.

As shown in Figure 7, the semiconductor device 500 may further include a conductive layer 34 covering the insulating layer 32. In this embodiment, the conductive layer 34 and the first semiconductor layer 14 may form a current path at their contact points. The conductive layer 34 may comprise a transparent conductive material, a metal, or an alloy. Transparent conductive materials include, but are not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene, or combinations of the above materials. The metals include, but are not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W). The alloy may contain at least two of the metals selected from the group consisting of the above-mentioned metals.

In some embodiments, the semiconductor device 500 may also have a form that includes only the insulating layer 32 and not the conductive layer 34, or a form that includes only the conductive layer 34 and not the insulating layer 32. The positions, relative relationships, material compositions, and structural variations of the other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

Figure 8 is a schematic diagram of a semiconductor device packaging structure 600 according to an embodiment of this disclosure. Referring to Figure 8, the packaging structure 600 includes a semiconductor device 60, a packaging substrate 61, a carrier 63, bonding wires 65, contact structures 66, and a packaging material layer 68. The packaging substrate 61 may contain ceramic or glass material. The packaging substrate 61 has multiple through-holes 62. The through-holes 62 may be filled with a conductive material such as a metal to facilitate electrical conduction and/or heat dissipation. The carrier 63 is located on one side of the surface of the packaging substrate 61 and also contains a conductive material such as a metal. The contact structures 66 are located on the other side of the surface of the packaging substrate 61. In this embodiment, the contact structure 66 includes a first contact pad 66a and a second contact pad 66b, and the first contact pad 66a and the second contact pad 66b can be electrically connected to the carrier 63 through the through hole 62. In one embodiment, the contact structure 66 may further include a thermal pad (not shown), for example, located between the first contact pad 66a and the second contact pad 66b.

A semiconductor element 60 is located on a carrier 63. The semiconductor element 60 can be any of the semiconductor elements described in any embodiment of this disclosure (such as semiconductor elements 100, 200, 300, 400, 500). In this embodiment, the carrier 63 includes a first portion 63a and a second portion 63b, and the semiconductor element 60 is electrically connected to the second portion 63b of the carrier 63 via a bonding wire 65. The bonding wire 65 may be made of a metal, such as gold, silver, copper, aluminum, or an alloy containing at least any of the above elements. A packaging material layer 68 covers the semiconductor element 60, providing protection for the semiconductor element 60. Specifically, the packaging material layer 68 may contain a resin material such as epoxy resin, silicone resin, etc. The packaging material layer 68 may further contain a plurality of wavelength-converting particles (not shown) to convert the first light emitted by the semiconductor device 60 into a second light. The wavelength of the second light is greater than the wavelength of the first light.

Based on the above, according to the embodiments of this disclosure, a semiconductor device can be provided that has good epitaxial quality and optoelectronic characteristics, such as further improvements in luminous efficiency, wavelength stability, and device reliability. Specifically, the semiconductor device disclosed herein can be applied to products in fields such as lighting, medical, display, communication, sensing, and power supply systems, such as lamps, surveillance cameras, mobile phones, tablet computers, automotive dashboards, televisions, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signals, outdoor displays, and medical equipment.

Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art should understand that modifications or changes can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. Furthermore, the above embodiments can be combined or substituted for each other where appropriate, and are not limited to the specific embodiments described. For example, parameters of a specific component or the connection relationship between a specific component and other components disclosed in one embodiment can also be applied to other embodiments, and all fall within the scope of protection of the present invention.

100, 200, 300, 400, 500, 60: Semiconductor Components; 10: Substrate; 10a: First Side; 10b: Second Side; 12: Active Structure; 14: First Semiconductor Layer; 16: Second Semiconductor Layer; 17: Window Layer; 18: First Electrode; 18a: Main Electrode; 18b: Extended Electrode; 20: Second Electrode; 24: Intermediate Layer; 26: Contact Layer; 28: Transition Layer; 30: Reflective Structure; 32: Insulating Layer; 34: Conductive Layer; 40: Adhesive Layer; 61: Packaging Substrate; 62: Via; 63: Carrier; 63a: Part 1 63b: Part 2 65: Bonding Line 66: Contact Structure 66a: First Contact Pad 66b: Second Contact Pad 68: Encapsulation Material Layer 120: First Confinement Layer 122: Second Confinement Layer 124: Active Region 600: Encapsulation Structure R1: First Region R2: Second Region S1, S2: Line t1: First Thickness A-A': Line t2: Second Thickness t3: Third Thickness t4: Fourth Thickness t5: Fifth Thickness w1: First Width w2: Second Width I, II, III: Regions _BM , _CM : Maximum Concentration

Figure 1 is a top view of the structure of a semiconductor device according to an embodiment of this disclosure.

Figure 2 is a schematic cross-sectional view of the semiconductor device in Figure 1 along line A-A'.

Figure 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of this disclosure.

Figure 4 is an epitaxial structure (SIMS) diagram of a semiconductor device portion of an embodiment disclosed herein.

Figure 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of this disclosure.

Figure 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of this disclosure.

Figure 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of this disclosure.

Figure 8 is a schematic diagram of the packaging structure of a semiconductor device according to an embodiment of this disclosure.

100: Semiconductor Devices

10: Base

10a: First side

10b: Second side

12: Active Structure

14: First Semiconductor Layer

16: Second Semiconductor Layer

18: First Electrode

20: Second Electrode

120: First Limitation Layer

122: Second Limitation Layer

124: Active Region

t1: First thickness

t2: Second thickness

t3: Third thickness

t4: Fourth thickness

t5: Fifth thickness

w1: First width

w2: Second width

Claims (10)

A semiconductor device includes: an active structure comprising an active region; a first semiconductor layer and a second semiconductor layer located on opposite sides of the active structure; an intermediate layer located between the second semiconductor layer and the active structure; a transition layer located on the second semiconductor layer; and a contact layer located on the transition layer; wherein, the second semiconductor layer comprises a first dopant, and the first semiconductor layer comprises a second dopant different from the first dopant; the contact layer comprises a ternary III-V semiconductor material; the second semiconductor layer comprises a binary III-V semiconductor material; and the active region comprises a quaternary semiconductor material. The semiconductor device described in claim 1, wherein the quaternary semiconductor material comprises InGaAsP or AlGaInAs. The semiconductor device as described in claim 1, wherein the transition layer and the contact layer contain at least two or more identical elements selected from the group consisting of indium (In), gallium (Ga) and arsenic (As). The semiconductor device described in claim 1 or 3, wherein the ternary III-V semiconductor material comprises InGaAs. The semiconductor device described in claim 1, wherein the semiconductor device emits radiation with a peak wavelength between 800 nm and 2000 nm. The semiconductor device as described in claim 1, wherein the active region includes the first dopant, and the doping concentration of the first dopant in the active region is less than or equal to 1 x ^{10¹⁸ cm⁻³} . The semiconductor device as described in claim 1 further includes a substrate located below the first semiconductor layer, and the substrate has a thickness greater than or equal to 60 µm and less than or equal to 250 µm. The semiconductor device as described in claim 7, wherein when the semiconductor device emits radiation greater than 1000 nm, the substrate has a transmittance greater than 30% or an absorption rate less than 30% for the radiation. The semiconductor device as described in claim 7 further includes a reflective structure located between the substrate and the first semiconductor layer, and the reflective structure includes a first metal layer, a second metal layer and a third metal layer. A packaging structure for a semiconductor device includes: a carrier; a semiconductor device as described in any one of claims 1 to 9, disposed on the carrier; and an encapsulating material layer covering the semiconductor device.