TWI839891B - Semiconductor substrate with balance stress - Google Patents

Abstract

Provided is a semiconductor substrate with a balance stress. The semiconductor substrate includes a ceramics base, a nucleation layer and a first buffer layer doped with a first dopant. The ceramics base has an off-cut angle other than 0 degree. The nucleation layer is disposed on the ceramics base. The first buffer layer is disposed on the nucleation layer. The first dopant includes C, Fe or a combination thereof. The first buffer layer provides compressive stress to the ceramic base. The concentration of the first dopant in the first buffer layer is increased away from the ceramics base. The curvature of the semiconductor substrate is between +16 km ^-1and -16 km ^-1.

Description

Semiconductor substrate with balanced stress

The present invention relates to a semiconductor device, and more particularly to a semiconductor substrate with balanced stress.

In order to enable power devices to have low on-resistance, high switching frequency, high breakdown voltage and high temperature operation performance, gallium nitride (GaN) semiconductor devices are currently the preferred choice for high-power devices.

In gallium nitride semiconductor devices, the semiconductor substrate affects the quality of the film formed thereon. For example, when the semiconductor substrate has an excessively large curvature, the warpage is severe, and the film formed on the semiconductor substrate subsequently cannot have good quality.

The present invention provides a semiconductor substrate with balanced stress, wherein a buffer layer with a gradient doping concentration can make the tensile stress and compressive stress experienced by the substrate similar, and can effectively prevent the substrate and the film layer thereon from being damaged by suddenly experiencing excessive counter stress.

A semiconductor substrate with balanced stress in an embodiment of the present invention includes a ceramic substrate, a nucleation layer, and a first buffer layer doped with a first dopant. The ceramic substrate has an off-cut angle of non-0 degrees. The nucleation layer is disposed on the ceramic substrate. The first buffer layer is disposed on the nucleation layer. The first dopant includes carbon, iron, or a combination thereof. The first buffer layer provides compressive stress to the ceramic substrate. The concentration of the first dopant in the first buffer layer increases in a direction away from the ceramic substrate. The curvature of the semiconductor substrate is between +16 km ^-1 and -16 km ^-1 .

Another embodiment of the present invention is a semiconductor substrate with balanced stress, comprising a ceramic substrate, a nucleation layer, a composite transition layer, a first buffer layer doped with a first dopant, and a second buffer layer doped with a second dopant. The nucleation layer is disposed on the ceramic substrate. The composite transition layer comprises a plurality of aluminum-containing layers sequentially stacked on the nucleation layer. The first buffer layer is disposed on the composite transition layer and provides compressive stress to the ceramic substrate. The second buffer layer is disposed on the first buffer layer and provides tensile stress to the ceramic substrate. In the composite transition layer, the aluminum content of the aluminum-containing layer relatively far from the ceramic substrate is higher than the aluminum content of the aluminum-containing layer relatively adjacent to the ceramic substrate. The first dopant includes carbon, iron or a combination thereof. The second dopant includes silicon, germanium or a combination thereof. The concentration of the second dopant in the second buffer layer increases in a direction away from the ceramic substrate. The curvature of the semiconductor substrate is between -10 km ^-1 and +10 km ^-1 .

In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

The following is a detailed description of the embodiments and accompanying drawings, but the embodiments provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn in their original size. For ease of understanding, the same components will be indicated by the same symbols in the following description.

The terms "include", "including", "have", etc. mentioned in this article are open terms, which means "including but not limited to".

When using the terms "first", "second", etc. to describe an element, it is only used to distinguish these elements from each other, and does not limit the order or importance of these elements. Therefore, in some cases, the first element can also be called the second element, and the second element can also be called the first element, and this does not deviate from the scope of the present invention.

In addition, in this article, the range expressed by "a numerical value to another numerical value" is a summary expression method to avoid listing all numerical values in the range one by one in the specification. Therefore, the description of a specific numerical range covers any numerical value in the numerical range, and covers a smaller numerical range defined by any numerical value in the numerical range.

1A to 1B are schematic cross-sectional views of a manufacturing process of a semiconductor substrate of an embodiment of the present invention. First, referring to FIG. 1A , a composite substrate 100 is provided. In this embodiment, the composite substrate 100 includes a substrate 100a, an insulating layer 100b, and a semiconductor layer 100c. The material of the substrate 100a is, for example, silicon, aluminum nitride, silicon carbide (SiC), sapphire, or a combination thereof. The insulating layer 100b is disposed on the substrate 100a. The insulating layer 100b is, for example, a silicon oxide layer, but the present invention is not limited thereto. The thickness of the insulating layer 100b is, for example, between 100 nm and 200 nm. The semiconductor layer 100c is disposed on the insulating layer 100b. The semiconductor layer 100c is, for example, a silicon layer, a silicon carbide layer or a combination thereof. The thickness of the semiconductor layer 100c is, for example, between 30 nm and 3 μm, preferably between 70 nm and 200 μm. In other words, in this embodiment, the composite substrate 100 may be a generally known silicon-on-insulator (SOI) substrate or a QST substrate, which has a high resistance and is particularly suitable for high-frequency components. In this embodiment, the substrate 100a may have a thermal conductivity greater than 1.4 W/cm·K, so the composite substrate 100 can be used as a heat dissipation substrate in addition to being a supporting substrate.

Next, a wide energy gap diffusion buffer layer 102 is formed on the semiconductor layer 100c of the composite substrate 100. In the present embodiment, the energy gap of the wide energy gap diffusion buffer layer 102 is higher than 2.5 eV, preferably between 3.2 eV and 9.1 eV, and more preferably between 4.5 eV and 5.5 eV. The wide energy gap diffusion buffer layer 102 is, for example, a silicon nitride layer, a silicon oxide layer, a zinc oxide layer, an aluminum oxide layer, a gallium oxide layer, or a combination thereof. In the present embodiment, the wide energy gap diffusion buffer layer 102 may be an amorphous layer, such as an amorphous silicon nitride layer. In the present embodiment, the thickness of the wide energy gap diffusion buffer layer 102 is between 30 nm and 120 nm, preferably between 35 nm and 100 nm, and more preferably between 40 nm and 90 nm. In the present embodiment, the wide energy gap diffusion buffer layer 102 is formed by, for example, a plasma-enhanced chemical vapor deposition (PECVD) process, an electron gun evaporation (E-gun evaporation) process, or a sputtering deposition process. In addition, in the present embodiment, the wide energy gap diffusion buffer layer 102 may have a resistance value between 1×10 ⁴ ohm·cm and 1×10 ¹⁴ ohm·cm.

1B, a nucleation layer 104 is formed on the wide energy gap diffusion buffer layer 102 to manufacture the semiconductor substrate 10 of this embodiment. In this embodiment, the nucleation layer 104 is an aluminum-containing layer, such as an aluminum nitride layer, but the present invention is not limited thereto.

Generally speaking, when the nucleation layer 104 is formed in a high temperature process, the aluminum contained in the nucleation layer 104 diffuses into the film layer below. The aluminum diffuses into the semiconductor layer 100c to form a P-type doped conductive layer. In this embodiment, since a wide energy gap diffusion buffer layer 102 is formed between the semiconductor layer 100c and the nucleation layer 104 of the composite substrate 100, the aluminum in the nucleation layer 104 diffuses into the wide energy gap diffusion buffer layer 102 during the high temperature process. When the thickness of the wide energy gap diffusion buffer layer 102 is close to the depth of aluminum diffusion, the aluminum contained in the nucleation layer 104 can be prevented from diffusing into the semiconductor layer 100c to form a P-type doped conductive layer, thereby preventing the formed semiconductor device from generating leakage at the composite substrate 100 during operation. In this embodiment, the thickness of the wide energy gap diffusion buffer layer 102 is greater than the depth of aluminum diffusion, so that the aluminum contained in the nucleation layer 104 can be prevented from diffusing into the semiconductor layer 100c. In addition, since the energy gap of the wide energy gap diffusion buffer layer 102 is higher than 2.5 eV, even if aluminum diffuses into the wide energy gap diffusion buffer layer 102, a P-type doped conductive layer is not formed.

In addition, in the present embodiment, the material of the wide energy gap diffusion buffer layer 102 may be amorphous. Compared with a single crystal material, the amorphous wide energy gap diffusion buffer layer 102 may effectively reduce the diffusion speed of aluminum contained in the nucleation layer 104 into the semiconductor layer 100c and the depth of aluminum diffusion into the wide energy gap diffusion buffer layer 102. Generally speaking, the depth of aluminum diffusion is between 50 nm and 100 nm. The wide energy gap diffusion buffer layer 102 can reduce the diffusion speed and depth of aluminum, reducing the diffusion depth of aluminum to between 40 nm and 90 nm. In the best case, the thickness of the wide-gap diffusion buffer layer 102 can be designed to be 40 nm to 90 nm to prevent aluminum from diffusing into the semiconductor layer 100c.

In the present embodiment, during the process of forming the nucleation layer 104 or in the subsequent high temperature process, the aluminum contained in the nucleation layer 104 diffuses into the wide energy gap diffusion buffer layer 102, thereby forming the diffusion layer 104a. As shown in FIG. 1B , in the present embodiment, the aluminum contained in the nucleation layer 104 diffuses only into the upper portion of the wide energy gap diffusion buffer layer 102, so that the diffusion layer 104a is formed adjacent to the upper surface of the wide energy gap diffusion buffer layer 102, but the present invention is not limited thereto. In other embodiments, the aluminum contained in the nucleation layer 104 may diffuse into the entire wide energy gap diffusion buffer layer 102, that is, the thickness of the diffusion layer 104a may be substantially equal to the thickness of the wide energy gap diffusion buffer layer 102.

FIG2 is a graph showing the relationship between the aluminum ion concentration and the aluminum ion diffusion depth in the semiconductor substrate of the embodiment of the present invention. Referring to FIG2, a buffer layer 200 (e.g., an AlGaN layer) is formed on the nucleation layer 104 of the semiconductor substrate 10, and the wide energy gap diffusion buffer layer 102 and the nucleation layer 104 are sequentially disposed on the semiconductor layer 100c. During the high temperature process, the aluminum contained in the nucleation layer 104 diffuses upward into the buffer layer 200 and diffuses downward into the wide energy gap diffusion buffer layer 102. After the aluminum contained in the nucleation layer 104 diffuses into the wide energy gap diffusion buffer layer 102, the aluminum concentration in the wide energy gap diffusion buffer layer 102 will be distributed in a gradient. That is, in the wide energy gap diffusion buffer layer 102, a relatively large amount of aluminum will be accumulated in the portion of the wide energy gap diffusion buffer layer 102 near the surface, and the aluminum concentration will be greatly reduced as the diffusion depth increases, so that the aluminum concentration of the portion of the wide energy gap diffusion buffer layer 102 near the nucleation layer 104 will be greater than the aluminum concentration of the portion far from the nucleation layer 104. In addition, since the wide energy gap diffusion buffer layer 102 can reduce (or even prevent) the aluminum contained in the nucleation layer 104 from diffusing into the semiconductor layer 100c, even when the aluminum contained in the nucleation layer 104 penetrates the wide energy gap diffusion buffer layer 102 and diffuses into the semiconductor layer 100c, the semiconductor layer 100c will only contain a very small amount of aluminum. At this time, the aluminum content is, for example, less than 10 ¹⁷ atoms/cm ³ , or even close to 0. In this way, when the semiconductor substrate 10 is used as a substrate for transistors, light-emitting diodes or other electronic components, the leakage current and loss of electrical signals during the operation of the transistors or light-emitting diodes can be effectively reduced or avoided.

The following will describe a transistor including the semiconductor substrate of the present invention by taking the semiconductor substrate 10 as an example.

FIG3 is a schematic cross-sectional view of a transistor of an embodiment of the present invention. Referring to FIG3 , during the manufacturing process of the transistor 20, a buffer layer 200 may be formed on the nucleation layer 104 of the semiconductor substrate 10. The buffer layer 200 is, for example, an AlGaN layer, but the present invention is not limited thereto. Because the difference in lattice constants between the composite substrate 100 and the GaN layer grown thereon will cause stress and affect the quality of the epitaxial layer on the composite substrate 100, the buffer layer 200 is added between the composite substrate 100 and the channel layer 202 to balance the stress between the composite substrate 100 and the epitaxial layer (e.g., the channel layer 202) subsequently formed thereon. In this embodiment, the thickness of the buffer layer 200 is, for example, between 100 nm and 2.3 μm. In other embodiments, the buffer layer 200 may be omitted, so that the channel layer 202 is in direct contact with the nucleation layer 104.

Then, a channel layer 202 and a barrier layer 204 are sequentially formed. The channel layer 202 is, for example, a GaN layer. The thickness of the channel layer 202 is, for example, between 20 nm and 100 nm. The barrier layer 204 is, for example, an AlGaN layer, an AlInN layer, an AlN layer, an AlGaInN layer, or a combination thereof. The thickness of the barrier layer 204 is, for example, between 5 nm and 50 nm. The channel layer 202 has a two-dimensional electron gas (2DEG) 202a, which is located below the interface between the channel layer 202 and the barrier layer 204. Then, a gate 206, a source 208s, and a drain 208d are formed on the barrier layer 204, wherein the gate 206 is located between the source 208s and the drain 208d. The material of the gate 206 is, for example, Ni, Mo, W, TiN, or a combination thereof. The material of the source 208s and the drain 208d is, for example, Al, Ti, Au, or an alloy thereof, or other materials that can form ohmic contact with the III-V compound.

In the transistor 20, since the semiconductor substrate 10 is used as its substrate, the generation of leakage current can be effectively reduced or avoided during operation, and the loss of electrical signals can be reduced or avoided.

It is particularly noted that in this embodiment, the transistor 20 is exemplified by a high electron mobility transistor (HEMT), but the structure of the transistor of the present invention is not limited to HEMT. In other embodiments, the transistor may have various well-known structures as long as the semiconductor substrate of the present invention is used as its substrate.

In addition, when the semiconductor substrate of the present invention is used as a substrate of a light-emitting diode, various structures of light-emitting diodes can be formed on the semiconductor substrate of the present invention, and the present invention is not limited thereto. For example, as shown in FIG4 , the light-emitting diode 30 includes a semiconductor substrate 10, a buffer layer 200, a first conductive GaN layer 300, a light-emitting layer 302, a second conductive GaN layer 304, a first electrode 306, and a second electrode 308. The light-emitting layer 302 is disposed between the first conductive GaN layer 300 and the second conductive GaN layer 304. The first electrode 306 is disposed on the first conductive GaN layer 300. The second electrode 308 is disposed on the second conductive GaN layer 304. The materials of the first conductivity type GaN layer 300 , the light emitting layer 302 , the second conductivity type GaN layer 304 , the first electrode 306 and the second electrode 308 are well known to those skilled in the art and will not be further described herein.

On the other hand, in the following embodiments, the substrate will be warped upward (in the growth direction of the film layer on the substrate) after being subjected to tensile stress, and the curvature of the semiconductor substrate will be positive. Conversely, the substrate will be warped downward after being subjected to compressive stress, and the curvature of the semiconductor substrate will be negative.

5A to 5B are schematic cross-sectional views of a semiconductor substrate manufacturing process according to an embodiment of the present invention. In this embodiment, the manufactured semiconductor substrate can have balanced stress and thus can have a lower curvature, which is beneficial to the epitaxial growth of subsequent film layers. In this embodiment, the curvature of the semiconductor substrate with balanced stress is between +16 km ^-1 and -16 km ^-1 .

First, referring to FIG. 5A , a ceramic substrate 500 is provided. The ceramic substrate 500 is, for example, a QST substrate, an AlN substrate, an Al ₂ O ₃ substrate, a ZnO substrate, or a silicon carbide substrate. In the present embodiment, the ceramic substrate 500 is a silicon carbide substrate and has a non-0 degree bevel angle, but the present invention is not limited thereto. For example, the ceramic substrate 500 may have a 4 degree bevel angle, but the present invention is not limited thereto. In other embodiments, the ceramic substrate 500 may have a bevel angle of 8 degrees, 12 degrees, etc. In addition, the thickness of the ceramic substrate 500 is, for example, less than 500 μm. In the present embodiment, the thickness of the ceramic substrate 500 is less than 450 μm. For example, the thickness of the ceramic substrate 500 may be 350 μm. In addition, in the present embodiment, the diameter of the ceramic substrate 500 is, for example, between 4 inches and 6 inches. When the stress of the ceramic substrate is unbalanced, warping will occur. The warping phenomenon will become more serious as the thickness of the ceramic substrate decreases and the diameter increases. The semiconductor substrate of the present invention has balanced stress. Therefore, in this embodiment, even if the thickness of the ceramic substrate 500 is less than 350 μm and the diameter is between 4 inches and 6 inches, because there is an epitaxial structure on the substrate that can balance the stress. Therefore, the final semiconductor substrate will not produce severe warping, and the curvature of the semiconductor substrate can be controlled between +16 km ^-1 and -16 km ^-1 .

Next, a nucleation layer 502 is formed on the ceramic substrate 500. In this embodiment, the nucleation layer 502 is an aluminum nitride layer, but the present invention is not limited thereto. The thickness of the nucleation layer 502 is, for example, between 10 nm and 100 nm. The nucleation layer 502 can provide tensile stress to the ceramic substrate 500. At this time, the curvature of the ceramic substrate 500 is, for example, between 20 km ^-1 and +50 km ^-1 .

Then, an undoped buffer layer 504 may be formed on the nucleation layer 502. The buffer layer 504 may be formed by, for example, performing an epitaxial growth process. In the present embodiment, the buffer layer 504 is a gallium nitride layer, but the present invention is not limited thereto. The thickness of the buffer layer 504 may be, for example, between 50 nm and 500 nm. The buffer layer 504 may provide compressive stress to the ceramic substrate 500. At this time, the curvature of the ceramic substrate 500 may be, for example, between -10 km ^-1 and +20 km ^-1 . The undoped buffer layer 504 is optional. In other embodiments, the undoped buffer layer 504 may be omitted according to actual needs.

Thereafter, referring to FIG. 5B , a buffer layer 506 doped with a first dopant is formed on the buffer layer 504. The method for forming the buffer layer 506 is, for example, an epitaxial growth process. In the present embodiment, the first dopant may be carbon, iron, or a combination thereof. In addition, in the present embodiment, the buffer layer 506 is a gallium nitride layer, but the present invention is not limited thereto. The thickness of the buffer layer 506 is, for example, between 50 nm and 500 nm. In the present embodiment, since the size of carbon or iron as the first dopant is larger than that of nitrogen or gallium, the formed buffer layer 506 may have a larger lattice. Therefore, the buffer layer 506 can provide compressive stress to the ceramic substrate 500. In detail, when the first dopant is carbon, carbon can replace nitrogen from gallium nitride in the buffer layer 506 to generate a larger lattice. In addition, when the first dopant is iron, iron can replace gallium from gallium nitride in the buffer layer 506 to generate a larger lattice.

Importantly, in the buffer layer 506, the concentration of the first dopant increases in the direction away from the ceramic substrate 500. In the present embodiment, the concentration of the first dopant in the buffer layer 506 increases from 5×10 ¹⁶ atom/cm ³ to 8×10 ¹⁸ atom/cm ^3. In other words, in the process of forming the buffer layer 506, the concentration of the first dopant gradually increases, thereby gradually providing an increased compressive stress to the ceramic substrate 500, so as to prevent the ceramic substrate 500 and the film layer thereon from suddenly being subjected to excessive counter stress (compressive stress) and being damaged.

Next, a buffer layer 508 doped with a first dopant is formed on the buffer layer 506 to form the semiconductor substrate 50 of the present embodiment. The buffer layer 508 is formed by, for example, performing an epitaxial growth process. In the present embodiment, the buffer layer 508 is a gallium nitride layer, which is the same as the buffer layer 506, and the first dopant in the buffer layer 508 can be carbon, iron or a combination thereof. Therefore, the buffer layer 508 can provide compressive stress to the ceramic substrate 500. In addition, the thickness of the buffer layer 508 is, for example, greater than 500 nm.

In the buffer layer 508, the concentration of the first dopant is fixed and not lower than the maximum concentration of the first dopant in the buffer layer 506. In the present embodiment, the concentration of the first dopant in the buffer layer 508 is not lower than 8×10 ¹⁸ atom/cm ³ . Since the buffer layer 506 having a gradient first dopant concentration is formed before the buffer layer 508 having a higher first dopant concentration is formed (increasing a larger compressive stress), the ceramic substrate 500 and the film layer thereon can be effectively prevented from being suddenly subjected to an excessively large counter stress (compressive stress) and being damaged.

In the semiconductor substrate 50 of the present embodiment, the nucleation layer 502 provides tensile stress to the ceramic substrate 500, and the buffer layer 504, the buffer layer 506, and the buffer layer 508 formed on the nucleation layer 502 provide compressive stress to the ceramic substrate 500. Therefore, the tensile stress and the compressive stress experienced by the ceramic substrate 500 can be made similar by adjusting the first doping concentration in the buffer layer 506 and the buffer layer 508. Since the ceramic substrate 500 has balanced stress, the ceramic substrate 500 can have a lower curvature, which is beneficial to the epitaxial growth of subsequent film layers.

In this embodiment, the buffer layer 506 with a gradient first doping concentration and the buffer layer 508 with a fixed first doping concentration are sequentially disposed on the buffer layer 504, but the present invention is not limited thereto. In other embodiments, only the buffer layer with a gradient first doping concentration may be disposed on the buffer layer 504.

Fig. 6 is a cross-sectional schematic diagram of a semiconductor substrate of an embodiment of the present invention. In this embodiment, the same elements as those in Fig. 5B are represented by the same reference symbols and will not be described again.

6 , in the semiconductor substrate 60 of the present embodiment, a buffer layer 506a having a gradient first dopant concentration is disposed on the buffer layer 504. The buffer layer 506a is formed by, for example, performing an epitaxial growth process. The first dopant may be carbon, iron, or a combination thereof. In addition, in the present embodiment, the buffer layer 506a is a gallium nitride layer, but the present invention is not limited thereto. The first dopant concentration of the buffer layer 506a increases in a direction away from the ceramic substrate 500, and the first dopant concentration increases to provide a compressive stress sufficient to make the tensile stress experienced by the ceramic substrate 500 similar to the compressive stress. For example, referring to the first embodiment, the concentration of the first dopant in the buffer layer 506a can be increased from 5×10 ¹⁶ atom/cm ³ to 8×10 ¹⁸ atom/cm ³ or more. In addition, in this case, the thickness of the buffer layer 506a can be the sum of the thicknesses of the buffer layer 506 and the buffer layer 508 in the semiconductor substrate 50.

The following will take a semiconductor substrate 50 as an example to explain the application of the present invention with balanced stress. For example, the semiconductor substrate 50 can be used in the manufacture of transistors. Depending on actual needs, the semiconductor substrate 50 can be replaced by a semiconductor substrate 60.

Fig. 7 is a cross-sectional schematic diagram of a transistor according to an embodiment of the present invention. In this embodiment, the same elements as those in Fig. 5B are denoted by the same reference symbols and will not be described again.

7 , in the manufacturing process of the transistor 70, a channel layer 700 and a barrier layer 702 may be sequentially formed on the buffer layer 508 of the semiconductor substrate 50. The channel layer 700 may be formed by, for example, performing an epitaxial growth process. In the present embodiment, the channel layer 700 is a gallium nitride layer, but the present invention is not limited thereto. The thickness of the channel layer 700 may be, for example, between 150 nm and 300 nm. The barrier layer 702 may be formed by, for example, performing an epitaxial growth process. In the present embodiment, the barrier layer 702 may be an aluminum gallium nitride layer (Al _x Ga _1-x N, X is the mole fraction, and X may be between 0.2 and 0.25), but the present invention is not limited thereto. The thickness of the barrier layer 702 is, for example, between 15 nm and 25 nm. Then, a gate 703, a source 704a, and a drain 704b are formed on the barrier layer 702, wherein the gate 703 is located between the source 704a and the drain 704b. The material of the gate 703 is, for example, Ni, Pt, Pd, Au, or a combination thereof. The material of the source 704a and the drain 704b is, for example, Al, Ti, In, Cr, V, Ta, TiN, Au, or an alloy thereof, or other materials that can form an ohmic contact with the III-V compound.

In the transistor 70 , since the ceramic substrate 500 has a balanced stress and can have a lower curvature, the channel layer 700 and the barrier layer 702 formed on the ceramic substrate 500 can have good quality, and thus the transistor 70 can have good electrical performance.

The aluminum-containing barrier layer 702 of the transistor 70 is tested. Compared with the poor uniformity of aluminum content in the barrier layer of a general transistor (the difference is greater than 2.0%), the aluminum content of the barrier layer 702 in the transistor 70 has a higher uniformity (the difference is less than 2.0%), that is, the barrier layer 702 has good quality.

8A to 8D are schematic cross-sectional views of the manufacturing process of a semiconductor substrate according to an embodiment of the present invention. In this embodiment, the manufactured semiconductor substrate can have balanced stress and thus can have a lower curvature, which is beneficial to the epitaxial growth of subsequent film layers. In this embodiment, the curvature of the semiconductor substrate with balanced stress is between -10 km ^-1 and +10 km ^-1 .

First, referring to FIG. 8A , a ceramic substrate 800 is provided. The ceramic substrate 800 is, for example, a QST substrate, an AlN substrate, an Al ₂ O ₃ substrate, a ZnO substrate or a SiC substrate. In this embodiment, the ceramic substrate 800 is a QST substrate, but the present invention is not limited thereto.

Next, a nucleation layer 802 is formed on the ceramic substrate 800. In this embodiment, the nucleation layer 802 is an aluminum nitride layer, but the present invention is not limited thereto. The thickness of the nucleation layer 802 is, for example, between 15 nm and 150 nm. The nucleation layer 802 can provide tensile stress to the ceramic substrate 800. At this time, the curvature of the ceramic substrate 800 is, for example, between +50 km ^-1 and +80 km ^-1 .

Next, referring to FIG. 8B , a composite transition layer 804 is formed on the nucleation layer 802. The composite transition layer 804 is formed by, for example, performing an epitaxial growth process. The thickness of the composite transition layer 804 is, for example, greater than 300 nm. The composite transition layer 804 includes a plurality of aluminum-containing layers. In the present embodiment, the aluminum-containing layer may be an aluminum gallium nitride layer (Al _Y Ga _1-Y N, where Y is the molar fraction). In the composite transition layer 804, the aluminum content of the aluminum-containing layer relatively far from the ceramic substrate 800 is higher than the aluminum content of the aluminum-containing layer relatively adjacent to the ceramic substrate 800. Since the difference in aluminum content causes the difference in lattice size, the composite transition layer 804 can be regarded as a lattice gradient layer and can provide a gradient compressive stress to the ceramic substrate 800. At this time, the curvature of the ceramic substrate 800 is, for example, between 0 km ^-1 and +20 km ^-1 . In addition, in this embodiment, the composite transition layer 804 includes two aluminum-containing layers, but the present invention is not limited thereto. In other embodiments, the composite transition layer 804 may include more aluminum-containing layers sequentially stacked on the nucleation layer 802.

Specifically, in the present embodiment, the composite transition layer 804 includes two aluminum-containing layers sequentially formed on the nucleation layer 802. In the composite transition layer 804, the aluminum content of the aluminum-containing layer 804b relatively far from the ceramic substrate 800 is higher than the aluminum content of the aluminum-containing layer 804a relatively close to the ceramic substrate 800. As a result, after the aluminum-containing layer 804a is formed, the curvature of the ceramic substrate 800 is, for example, between +30 km ^-1 and +60 km ^-1 , and then after the aluminum-containing layer 804b is formed, the curvature of the ceramic substrate 800 is, for example, between 0 km ^-1 and +20 km ^-1 .

In the present embodiment, the aluminum molar fraction Y in each aluminum-containing layer is, for example, between 0.1 and 0.9. In addition, in the composite transition layer 804, the difference in aluminum molar fraction Y between two adjacent aluminum-containing layers is, for example, between 0.4/Z and 0.9/Z, where Z represents the number of aluminum-containing layers in the composite transition layer 804. In the present embodiment, the composite transition layer 804 includes an aluminum-containing layer 804a and an aluminum-containing layer 804b, and thus the difference in aluminum molar fraction Y between the aluminum-containing layer 804a and the aluminum-containing layer 804b is between 0.2 and 0.45.

Then, referring to FIG. 8C , an undoped buffer layer 806 may be formed on the composite transition layer 804. The buffer layer 806 may be formed by, for example, performing an epitaxial growth process. In the present embodiment, the buffer layer 806 is a gallium nitride layer, but the present invention is not limited thereto. The thickness of the buffer layer 806 may be, for example, between 250 nm and 500 nm. The buffer layer 806 may provide compressive stress to the ceramic substrate 800. At this time, the curvature of the ceramic substrate 800 may be, for example, between 0 km ^-1 and -20 km ^-1 . The undoped buffer layer 806 is optional. In other embodiments, the undoped buffer layer 806 may be omitted according to actual needs.

Thereafter, a buffer layer 808 doped with a first dopant is formed on the buffer layer 806. The buffer layer 808 is formed by, for example, performing an epitaxial growth process. In the present embodiment, the first dopant may be carbon, iron, or a combination thereof. The concentration of the first dopant in the buffer layer 808 is, for example, between 5×10 ¹⁷ atom/cm ³ and 1×10 ¹⁹ atom/cm ^3. In addition, in the present embodiment, the buffer layer 808 is a gallium nitride layer, but the present invention is not limited thereto. The thickness of the buffer layer 808 is, for example, between 0.5 μm and 1 μm. In this embodiment, since the size of carbon or iron as the first dopant is larger than that of nitrogen or gallium, the buffer layer 808 formed may have a larger lattice. Therefore, the buffer layer 808 may provide compressive stress to the ceramic substrate 800. At this time, the curvature of the ceramic substrate 800 is, for example, between -40 km ^-1 and -60 km ^-1 .

Next, referring to FIG. 8D , a buffer layer 810 doped with a second dopant is formed on the buffer layer 808. The method for forming the buffer layer 810 is, for example, an epitaxial growth process. In the present embodiment, the second dopant may be silicon, germanium, or a combination thereof. In addition, in the present embodiment, the buffer layer 810 is a gallium nitride layer, but the present invention is not limited thereto. The thickness of the buffer layer 810 is, for example, between 100 nm and 500 nm. In the present embodiment, since the size of silicon or germanium as the second dopant is smaller than that of nitrogen or gallium, the formed buffer layer 810 may have a smaller lattice. Therefore, the buffer layer 810 can provide tensile stress to the ceramic substrate 800. At this time, the curvature of the ceramic substrate 800 is, for example, between -20 km ^-1 and -40 km ^-1 .

Importantly, in the buffer layer 810, the concentration of the second dopant increases in the direction away from the ceramic substrate 800. In the present embodiment, the concentration of the second dopant in the buffer layer 810 increases from 1×10 ¹⁷ atom/cm ³ to 1×10 ¹⁹ atom/cm ^3. That is, in the process of forming the buffer layer 810, the concentration of the second dopant gradually increases, thereby gradually providing an increased tensile stress to the ceramic substrate 800, so as to prevent the ceramic substrate 800 and the film layer thereon from suddenly being subjected to excessive counter stress (tensile stress) and being damaged.

Afterwards, a buffer layer 812 doped with a second dopant is formed on the buffer layer 810 to form the semiconductor substrate 80 of the present embodiment. The buffer layer 812 is formed by, for example, performing an epitaxial growth process. In the present embodiment, the buffer layer 812 is a gallium nitride layer, similar to the buffer layer 810, and the second dopant in the buffer layer 812 can be silicon, germanium or a combination thereof. Therefore, the buffer layer 812 can provide tensile stress to the ceramic substrate 800. The thickness of the buffer layer 812 is, for example, greater than 500 nm.

In the buffer layer 812, the concentration of the second dopant is fixed and not lower than the maximum concentration of the second dopant in the buffer layer 810. In the present embodiment, the concentration of the second dopant in the buffer layer 812 is not lower than 8×10 ¹⁸ atom/cm ³ . Since the buffer layer 810 having a gradient second dopant concentration is formed before the buffer layer 812 having a higher second dopant concentration (increasing a larger tensile stress) is formed, the ceramic substrate 800 and the film layer thereon can be effectively prevented from being suddenly subjected to an excessively large counter stress (tensile stress) and being damaged. In other embodiments, the concentration of the second dopant in the buffer layer 812 may be higher than 1×10 ¹⁹ atom/cm ³ .

In the semiconductor substrate 80 of the present embodiment, before the buffer layer 810 and the buffer layer 812 are formed, the total stress experienced by the ceramic substrate 800 is compressive stress, so the tensile stress experienced by the ceramic substrate 800 is made close to the compressive stress by forming the buffer layer 810 and the buffer layer 812. Since the ceramic substrate 800 has balanced stress, the ceramic substrate 800 can have a lower curvature, which is beneficial to the epitaxial growth of subsequent film layers.

In this embodiment, the buffer layer 810 with a gradient second doping concentration and the buffer layer 812 with a fixed second doping concentration are sequentially disposed on the buffer layer 808, but the present invention is not limited thereto. In other embodiments, only the buffer layer with a gradient second doping concentration may be disposed on the buffer layer 808.

Fig. 9 is a cross-sectional schematic diagram of a semiconductor substrate of an embodiment of the present invention. In this embodiment, the same elements as those in Fig. 8D are represented by the same reference symbols and will not be described again.

9 , in the semiconductor substrate 90 of the present embodiment, a buffer layer 810a having a gradient second dopant concentration is disposed on the buffer layer 808. The buffer layer 810a is formed by, for example, performing an epitaxial growth process. The second dopant may be silicon, germanium, or a combination thereof. In addition, in the present embodiment, the buffer layer 810a is a gallium nitride layer, but the present invention is not limited thereto. The second dopant concentration of the buffer layer 810a increases in a direction away from the ceramic substrate 800, and the second dopant concentration increases to provide a tensile stress sufficient to make the tensile stress experienced by the ceramic substrate 800 similar to the compressive stress. For example, referring to the third embodiment, the concentration of the second dopant in the buffer layer 810a can be increased from 1×10 ¹⁷ atom/cm ³ to 1×10 ¹⁹ atom/cm ³ or more. In addition, in this case, the thickness of the buffer layer 810a can be the sum of the thicknesses of the buffer layer 810 and the buffer layer 812 in the semiconductor substrate 80.

The following will take the semiconductor substrate 80 as an example to explain the application of the present invention with balanced stress. For example, the semiconductor substrate 80 can be used in the manufacture of transistors. Depending on actual needs, the semiconductor substrate 80 can be replaced by a semiconductor substrate 90.

10A to 10B are cross-sectional schematic diagrams of the manufacturing process of a transistor according to an embodiment of the present invention. In this embodiment, the same elements as those in FIG. 8D are represented by the same reference symbols and will not be described again.

First, referring to FIG. 10A , an N-type gallium nitride layer 1000, a P-type gallium nitride layer 1002, and an N-type gallium nitride layer 1004 are sequentially formed on a semiconductor substrate 80. The N-type gallium nitride layer 1000, the P-type gallium nitride layer 1002, and the N-type gallium nitride layer 1004 are formed by, for example, performing an epitaxial growth process. The thickness of the N-type gallium nitride layer 1000 is, for example, between 3 μm and 5 μm. The thickness of the P-type gallium nitride layer 1002 is, for example, between 250 nm and 400 nm. The thickness of the N-type gallium nitride layer 1004 is, for example, between 150 nm and 300 nm. In this embodiment, the N-type gallium nitride layer 1000, the P-type gallium nitride layer 1002, and the N-type gallium nitride layer 1004 are merely exemplary and are not intended to limit the present invention.

Then, referring to FIG. 10B , the N-type gallium nitride layer 1000, the P-type gallium nitride layer 1002, and the N-type gallium nitride layer 1004 are patterned to form a stacked structure 1008. In the present embodiment, a portion of the buffer layer 812 is removed during the process of patterning the N-type gallium nitride layer 1000, the P-type gallium nitride layer 1002, and the N-type gallium nitride layer 1004. Then, a source 1010 is formed on the exposed buffer layer 812. In the present embodiment, the source 1010 is formed on the buffer layer 812 on both sides of the stacked structure 1008. Afterwards, a groove is formed in the stacked structure 1008, and a gate insulating layer 1012 is formed on the surface of the groove, a gate 1014 is formed on the gate insulating layer 1012, and a drain 1016 is formed on the N-type gallium nitride layer 1004 on both sides of the gate 1014. In this way, the manufacturing of the transistor 92 of this embodiment is completed. The formation methods of the source 1010, the gate insulating layer 1012, the gate 1014 and the drain 1016 are well known to those skilled in the art and will not be described in detail herein.

In the transistor 92, since the ceramic substrate 800 has a balanced stress and can have a lower curvature, each film layer formed on the ceramic substrate 800 can have good quality, and thus the transistor 92 can have good electrical performance.

It is particularly noted that the transistor including the semiconductor substrate of the present invention is not limited to having a structure like the transistors 70 and 92. In other embodiments, the transistor may have various well-known structures as long as the semiconductor substrate of the present invention is used as its substrate.

In addition, the semiconductor substrate of the present invention can also be used as a substrate for light-emitting diodes. When the semiconductor substrate of the present invention is used as a substrate for light-emitting diodes, various structures of light-emitting diodes can be formed on the semiconductor substrate of the present invention, and the present invention is not limited thereto.

Although the present invention has been disclosed as above by way of embodiments, they are not intended to limit the present invention. Any person having ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

10, 50, 60, 80, 90: semiconductor substrate 20, 70, 92: transistor 30: light-emitting diode 100: composite substrate 100a: substrate 100b: insulating layer 100c: semiconductor layer 102: wide bandgap diffusion buffer layer 104, 502, 802: nucleation layer 104a: diffusion layer 200, 504, 506, 506a, 508, 806, 808, 810, 810a, 812: buffer layer 202, 700: channel layer 202a: two-dimensional electron gas 204, 702: barrier layer 206, 703, 1014: Gate 208s, 704a, 1010: Source 208d, 704b, 1016: Drain 300: First conductivity type GaN layer 302: Light emitting layer 304: Second conductivity type GaN layer 306: First electrode 308: Second electrode 500, 800: Ceramic substrate 804: Composite transition layer 804a, 804b: Aluminum-containing layer 1000, 1004: N-type gallium nitride layer 1002: P-type gallium nitride layer 1008: Stacked structure 1012: Gate insulation layer

Figures 1A to 1B are schematic cross-sectional views of the manufacturing process of the semiconductor substrate of the embodiment of the present invention. Figure 2 is a graph showing the relationship between the aluminum ion concentration and the aluminum ion diffusion depth in the semiconductor substrate of the embodiment of the present invention. Figure 3 is a schematic cross-sectional view of the transistor of the embodiment of the present invention. Figure 4 is a schematic cross-sectional view of the light-emitting diode of the embodiment of the present invention. Figures 5A to 5B are schematic cross-sectional views of the manufacturing process of the semiconductor substrate of the embodiment of the present invention. Figure 6 is a schematic cross-sectional view of the semiconductor substrate of the embodiment of the present invention. Figure 7 is a schematic cross-sectional view of the transistor of the embodiment of the present invention. Figures 8A to 8D are schematic cross-sectional views of the manufacturing process of the semiconductor substrate of the embodiment of the present invention. FIG9 is a schematic cross-sectional view of a semiconductor substrate of an embodiment of the present invention. FIG10A to FIG10B are schematic cross-sectional views of a manufacturing process of a transistor of an embodiment of the present invention.

Claims (7)

A semiconductor substrate with balanced stress comprises: a ceramic substrate having a non-0 degree bevel cut angle; a nucleation layer disposed on the ceramic substrate; a first buffer layer doped with a first dopant disposed on the nucleation layer and providing compressive stress to the ceramic substrate; and a second buffer layer doped with the first dopant disposed on the first buffer layer, wherein the second buffer layer provides compressive stress to the ceramic substrate. The ceramic substrate provides compressive stress, and the concentration of the first dopant in the second buffer layer is fixed, wherein the first dopant includes carbon, iron or a combination thereof, wherein the concentration of the first dopant in the first buffer layer increases in a direction away from the ceramic substrate, wherein the first buffer layer and the second buffer layer are gallium nitride layers, and wherein the curvature of the semiconductor substrate is between +16 km ^-1 and -16 km ^-1 . A semiconductor substrate with balanced stress as described in claim 1, wherein the ceramic substrate is a silicon carbide substrate. A semiconductor substrate with balanced stress as described in claim 1, wherein the ceramic base has a 4-degree bevel cut angle. The semiconductor substrate with balanced stress as described in claim 1, wherein the concentration of the first dopant in the first buffer layer increases from 5×10 ¹⁶ atom/cm ³ to 8×10 ¹⁸ atom/cm ³ . The semiconductor substrate with balanced stress as described in claim 1, wherein the concentration of the first dopant in the second buffer layer is not less than 8×10 ¹⁸ atom/cm ³ . A semiconductor substrate with balanced stress as described in claim 1, wherein the diameter of the ceramic base is between 4 inches and 6 inches. A semiconductor substrate with balanced stress as described in claim 1, wherein the thickness of the ceramic substrate is less than 450μm.

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