TWI839671B - Debug system, microprocessing device and debug method - Google Patents

Abstract

A debug system is provided in the invention. The debug system may comprise a debugger and a target device. The debugger is configured to output an output signal. The output signal may be a first encoded signal or a reset signal, and the first encoded signal is generated by encoding a first data signal and a first clock signal. The target device comprises a serial wire debug (SWD) interface circuit and a serial wire debug (SWD) debug access port. The SWD interface circuit may be coupled to the debugger to receive the output signal. In addition, the SWD interface circuit may decode the first encoded signal to generate the first data signal and the first clock signal. The SWD debug access port is coupled to the SWD interface circuit. The SWD debug access port receives the first data signal and the first clock signal from the SWD interface circuit to perform the debug of the target device.

Description

Debugging system, microprocessing device and debugging method

The embodiments of the present invention are mainly related to a debugging technology, and more particularly to a debugging technology for transmitting a reset signal, a data signal and a clock signal through only one pin.

The serial wire debug (SWD) interface is a debugging interface. The serial wire debug interface can be applied to debugging chips or processors. The traditional serial wire debug interface requires SWDIO pins, SWDCLK pins and RESET pins to receive data signals, clock signals and reset signals respectively.

In the design of microcontroller units (MCUs), reducing the number of pins will reduce the complexity of external device routing. Therefore, how to reduce the number of pins of the serial line debugging interface configured in the microcontroller unit will be a topic worth studying.

In view of the above-mentioned problems of the prior art, the embodiments of the present invention provide a debugging system, a microprocessor device and a debugging method.

According to one embodiment of the present invention, a debugging system is provided. The debugging system includes a debugger and a target device. The debugger can be used to output an output signal. The output signal is a first coded signal or a reset signal, and the first coded signal is generated by encoding a first data signal and a first clock signal. The target device includes a serial debugging interface circuit and a debugging access port. The serial debugging interface circuit is coupled to the debugger to receive the output signal. In addition, the serial debugging interface circuit can decode the first coded signal to generate the first data signal and the first clock signal. The debugging access port is coupled to the serial debugging interface circuit. The debug access port receives the data signal and the clock signal from the serial debug interface circuit to debug the target device.

In some embodiments, the serial debug interface circuit further includes a judgment circuit. The judgment circuit judges whether a cycle time of the output signal is greater than a critical value to judge whether the output signal is the first coded signal or the reset signal. When the cycle time of the output signal is greater than a critical value, the judgment circuit judges that the output signal is the reset signal, and when the cycle time of the output signal is not greater than the critical value, the judgment circuit judges that the output signal is the first coded signal.

In some embodiments, the serial debugging interface circuit further includes a decoder. The decoder is coupled to the determination circuit and can decode the first coded signal to generate the first data signal and the first clock signal.

In some embodiments, the serial debug interface circuit further includes an analysis circuit. The analysis circuit is coupled to the decoder and the debug access port. The analysis circuit determines a first transmission direction of the first data signal and the first clock signal according to the first data signal, so as to transmit the first data signal and the first clock signal to the debug access port. The analysis circuit further receives a second data signal and a second clock signal from the debug access port, and determines a second transmission direction of the second data signal and the second clock signal according to the first data signal.

In some embodiments, the serial debugging interface circuit further includes a coding circuit. The coding circuit is coupled to the analysis circuit. The coding circuit can receive the second data signal and the second clock signal, and encode the second data signal and the second clock signal to generate a second coded data.

In some embodiments, the first coded data and the second coded data are generated via a Manchester code.

According to one embodiment of the present invention, a microprocessor device is provided. The microprocessor device includes a serial debug interface circuit and a debug access port. The serial debug interface circuit is coupled to a debugger to receive an output signal. In addition, the serial debug interface circuit decodes a first coded signal to generate a first data signal and a first clock signal. The output signal is the first coded signal or a reset signal, and the first coded signal is generated after encoding the first data signal and the first clock signal. The debug access port is coupled to the serial debug interface circuit. The debug access port can receive the data signal and the clock signal from the serial debug interface circuit to debug the microprocessor device.

According to an embodiment of the present invention, a debugging method is provided. The debugging method is applicable to a debugging system, wherein the debugging system includes a debugger and a target device. The steps of the debugging method include: outputting an output signal through a debugger, wherein the output signal is a first coded signal or a reset signal, and the first coded signal is generated by encoding a first data signal and a first clock signal; receiving the output signal through a serial debugging interface circuit of a target device; when the output signal is the first coded signal, decoding the first coded signal through the serial debugging interface circuit to generate the first data signal and the first clock signal; and receiving the data signal and the clock signal from the serial debugging interface circuit through a debugging access port of the target device to debug the target device.

As for other additional features and advantages of the present invention, those skilled in the art can obtain them by making some modifications and improvements based on the debugging system, microprocessor device and debugging method disclosed in the implementation method of this case without departing from the spirit and scope of the present invention.

This section describes the preferred method of implementing the present invention, and its purpose is to illustrate the spirit of the present invention rather than to limit the scope of protection of the present invention. The scope of protection of the present invention shall be subject to the scope of the attached patent application.

FIG. 1 is a block diagram showing a debugging system 100 according to an embodiment of the present invention. As shown in FIG. 1, the debugging system 100 may include a debugger 110 and a target device 120. It should be noted that the block diagram shown in FIG. 1 is only for the convenience of explaining the embodiment of the present invention, but the present invention is not limited to FIG. 1.

According to an embodiment of the present invention, the target device 120 may be a microcontroller unit (MCU) or a chip. As shown in FIG. 1 , according to an embodiment of the present invention, the target device 120 may include a serial debug interface circuit 210, a serial (Serial Wire Debug, SWD) debug access port (Debug Access Port, DAP) 220 and a processor core 230. According to an embodiment of the present invention, the target device 120 may be coupled to the debugger 110 via the serial debug interface circuit 210 to perform serial debugging. The serial debug interface circuit 210 may be coupled to the serial debug access port 220 and the processor core 230. In addition, the serial debug access port 220 may be coupled to the processor core 230. It should be noted that the target device 120 shown in FIG. 1 is only for the convenience of explaining the embodiment of the present invention, but the present invention is not limited to FIG. 1. The target device 120 may also include other components.

According to an embodiment of the present invention, the serial debugging interface circuit 210 can be applied to the serial debugging technology. As shown in FIG. 1 , according to an embodiment of the present invention, the serial debugging interface circuit 210 can include a determination circuit 211, a decoder 212, a encoder 213 and an analysis circuit 214.

According to an embodiment of the present invention, the judgment circuit 211 can use a timer. According to an embodiment of the present invention, when the debugger 110 is to debug the target device 120, the debugger 110 will send an output signal S _out to the serial debug interface circuit 210 of the target device 120. After the judgment circuit 211 of the serial debug interface circuit 210 receives the output signal S _out , the judgment circuit 211 will judge whether the cycle time of the currently received output signal is greater than a critical value (for example, 100 microseconds (μs)). ), but the present invention is not limited thereto). Specifically, the cycle time described in the present invention refers to the time taken for the output signal S _out to switch from a high level to a low level or from a low level to a high level.

When the determination circuit 211 determines that the cycle time of the currently received output signal is greater than a critical value, the determination circuit 211 determines that the output signal S _out is a reset signal S _reset and transmits the reset signal S _reset to the processor core 230. According to an embodiment of the present invention, the determination circuit 211 may first transmit the reset signal S _reset to the processor core 230. According to an embodiment of the present invention, when the reset signal S _reset is a high level, the target device 120 will not enter a reset state, and when the reset signal S _reset is a low level, the target device 120 enters a reset state.

When the judging circuit 211 judges that the cycle time of the currently received output signal S _out is not greater than a critical value, the judging circuit 211 judges that the output signal S _out is a coded signal S _encode . Then, the judging circuit 211 transmits the coded signal S _encode to the decoder 212. According to an embodiment of the present invention, the coded signal S _encode output by the debugger 110 is generated by encoding a data signal S _data and a clock signal S _clock in advance through a coding technique. According to an embodiment of the present invention, the coding technique adopted by the present invention can be Manchester Coding. The decoder 212 decodes the coded signal S _encode according to the adopted coding technique to generate the data signal S _data and the clock signal S _clock to be transmitted by the debugger 110 . Then, the decoder 212 transmits the data signal S _data and the clock signal S _clock to the analysis circuit 214 .

According to an embodiment of the present invention, the analysis circuit 214 determines the transmission direction of the subsequent data signal S _data and the clock signal S _clock according to the command bit (e.g., RnW bit) in _{the data signal S data from} the decoder 212. In other words, the analysis circuit 214 determines whether the operation required by the debugger 110 is a write operation (i.e., writing data from the debugger 110 to the target device 120) or a read operation (i.e., reading data from the target device 120 to the debugger 110) according to the command bit (e.g., RnW bit) in the data signal S data from the decoder 212. According to an embodiment of the present invention, when the command bit is a first value (e.g., 0), the analysis circuit 214 determines that the data signal S _data and the clock signal S _clock are to be written from the debugger 110 to the target device 120; and when the command bit is a second value (e.g., 1), the analysis circuit 214 determines that the data signal S _data and the clock signal S _clock are to be read from the target device 120 to the debugger 110. In addition, according to an embodiment of the present invention, the analysis circuit 214 determines whether the data signal S _data is successfully received according to the confirmation bit (e.g., ACK bit) in the data signal S _data . When the analysis circuit 214 successfully receives the data signal S _data , the analysis circuit 214 can transmit the data signal S _data according to the transmission direction of the data signal S _data .

According to an embodiment of the present invention, when the analysis circuit 214 determines that the transmission direction of the data signal S _data and the clock signal S _clock is to be written from the debugger 110 to the target device 120 according to the data signal S _data from the decoder 212, the analysis circuit 214 transmits the data signal S _data and the clock signal S _clock decoded by the decoder 212 to the serial debug access port 220. According to an embodiment of the present invention, the analysis circuit 214 can transmit the data signal S _data to the serial debug access port 220 via a data path, and transmit the clock signal S _clock to the serial debug access port 220 via a clock path. After receiving the data signal S _data and the clock signal S _clock , the serial debug access port 220 transmits the data signal S _data and the clock signal S _clock to the processor core 230 to perform a debugging procedure.

According to an embodiment of the present invention, when the analysis circuit 214 determines that the transmission direction of the data signal S _data and _the clock signal S _clock is to be read from the target device 120 to the debugger 110 according to the data signal S data from the decoder 212, the analysis circuit 214 transmits the data signal S _data and the clock signal S _clock received from the serial debug access port 220 to the encoder 213. According to an embodiment of the present invention, the analysis circuit 214 can receive the data signal S _data and the clock signal S _clock from the serial debug access port 220 via the data path. The encoder 213 _encodes the data signal S _data and the clock signal S _clock into a coded signal ^S'encode by a coding technique (e.g., Manchester Coding). Then, the encoder 213 transmits the _encoded signal ^S'encode to the determination circuit 211. The determination circuit 211 transmits the _encoded signal ^S'encode to the debugger 110.

According to an embodiment of the present invention, the debugger 110 may also include a decoder and an encoder to _decode the coded signal ^S'encode and generate the coded signal _Sencode .

According to the debugging system 100 proposed by the present invention, the target device 120 can transmit the reset signal S _reset , the data signal S _data and the clock signal S _clock to be transmitted by the serial debugging interface by connecting to the debugger 110 through only one pin. In other words, the debugging system 100 proposed by the present invention can integrate the SWDIO pin, the SWDCLC pin and the RESET pin of the serial debugging interface into one pin. Therefore, the debugging system 100 proposed by the present invention can reduce the number of pins required to be configured by the target device 120 for serial debugging.

FIG. 2 is a flow chart of a debugging method according to an embodiment of the present invention. The debugging method can be applied to the debugging system 100. As shown in FIG. 2, in step S210, the debugger of the debugging system 100 outputs an output signal, wherein the output signal is a first coded signal or a reset signal, and the first coded signal is generated by encoding a first data signal and a first clock signal.

In step S220, the output signal is received by a serial debug interface circuit of the target device of the debugging system 100.

In step S230, when the output signal is a first coded signal, the first coded signal is decoded by the serial debug interface circuit to generate a first data signal and a first clock signal.

In step S240, a data signal and a clock signal are received from a serial debug interface circuit via a serial debug access port of the target device to debug the target device.

According to an embodiment of the present invention, the debugging method further includes, by a judgment circuit of the serial debugging interface circuit, judging whether a cycle time of the output signal is greater than a critical value, so as to judge whether the output signal is the first coded signal or the reset signal. When the cycle time of the output signal is greater than the critical value, the judgment circuit judges that the output signal is the reset signal, and when the cycle time of the output signal is not greater than the critical value, the judgment circuit judges that the output signal is the first coded signal.

According to an embodiment of the present invention, step S230 of the debugging method further includes decoding the first coded signal by a decoder of the serial debugging interface circuit to generate the first data signal and the first clock signal.

According to an embodiment of the present invention, the debugging method further includes, by means of an analysis circuit of the serial debugging interface circuit, judging a first transmission direction of the first data signal and the first clock signal according to the first data signal, so as to transmit the first data signal and the first clock signal to the serial debugging access port. In addition, the debugging method further includes, by means of an analysis circuit of the serial debugging interface circuit, judging, by means of the first data signal, that a second data signal and a second clock signal are received from the serial debugging access port in a second transmission direction.

According to an embodiment of the present invention, the steps of the debugging method further include receiving a second data signal and a second clock signal through an encoding circuit of the serial debugging interface circuit, and encoding the second data signal and the second clock signal to generate a second encoded data.

According to an embodiment of the present invention, in the debugging method, the first coded data and the second coded data are generated via a Manchester coding.

According to the debugging method proposed by the present invention, the target device of the debugging system 100 can be connected to the debugger of the debugging system 100 by only one pin, and the reset signal S _reset , the data signal S _data and the clock signal S _clock can be transmitted. Therefore, the debugging method proposed by the present invention can reduce the number of pins required for serial debugging.

The serial numbers in this specification and the scope of the patent application, such as "first", "second", etc., are only for the convenience of explanation and there is no sequential relationship between them.

The methods and algorithm steps disclosed in the specification of the present invention can be directly applied to hardware and software modules or a combination of the two by executing a processor. A software module (including execution instructions and related data) and other data can be stored in a data memory, such as random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), register, hard disk, portable disk, compact disk read-only memory (CD-ROM), DVD or any other computer-readable storage medium format in the art. A storage medium can be coupled to a machine device, for example, such as a computer/processor (for ease of explanation, the processor is represented in this specification), through which the processor can read information (such as program code) and write information to the storage medium. A storage medium can integrate a processor. A special application integrated circuit (ASIC) includes a processor and a storage medium. A user device includes a special application integrated circuit. In other words, the processor and the storage medium are included in the user device in a manner that is not directly connected to the user device. In addition, in some embodiments, any product suitable for a computer program includes a readable storage medium, wherein the readable storage medium includes program code related to one or more disclosed embodiments. In some embodiments, a product of a computer program may include packaging materials.

The above paragraphs use multiple layers for description. Obviously, the teachings of this article can be implemented in multiple ways, and any specific architecture or function disclosed in the examples is only a representative situation. According to the teachings of this article, anyone familiar with this technology should understand that each layer disclosed in this article can be implemented independently or two or more layers can be implemented in combination.

Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Anyone skilled in the art may make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the invention shall be subject to the definition of the attached patent application scope.

100: debugging system 110: debugger 120: target device 210: serial debugging interface circuit 211: judgment circuit 212: decoder 213: encoder 214: analysis circuit 220: serial debugging access port 230: processor core S _out : output signal S _encode , S ^' _encode : encoding signal S _reset : reset signal S _data : data signal S _clock : clock signal S210~S240: steps

FIG. 1 is a block diagram showing a debugging system 100 according to an embodiment of the present invention. FIG. 2 is a flow chart of a debugging method according to an embodiment of the present invention.

100: Debug system

110: Debugger

120: Target device

210: Serial debug interface circuit

211: Judgment circuit

212:Decoder

213: Encoder

214: Analyzing Circuits

220: Debug access port

230: Processor core

S _out : output signal

S _encode , S _encode : coded signal

S _reset : reset signal

S _data : data signal

S _clock : clock signal

Claims (10)

A debugging system includes: a debugger outputting an output signal, wherein the output signal is a first coded signal or a reset signal, and the first coded signal is generated by encoding a first data signal and a first clock signal; and a target device, including: a serial debugging interface circuit coupled to the debugger via a pin to receive the first coded signal or the reset signal via the pin; and decoding the first coded signal to generate the first data signal and the first clock signal; and a serial debugging access port coupled to the serial debugging interface circuit to receive the first data signal and the first clock signal from the serial debugging interface circuit to debug the target device. The debugging system of claim 1, wherein the serial debugging interface circuit further includes: a judgment circuit, judging whether a cycle time of the output signal is greater than a critical value, so as to judge whether the output signal is the first coded signal or the reset signal; wherein when the cycle time of the output signal is greater than the critical value, the judgment circuit judges that the output signal is the reset signal, and when the cycle time of the output signal is not greater than the critical value, the judgment circuit judges that the output signal is the first coded signal. As in claim 2, the debugging system, wherein the serial debugging interface circuit further comprises: a decoder, coupled to the judgment circuit, and decoding the first coded signal to generate the first data signal and the first clock signal. The debugging system of claim 3, wherein the serial debugging interface circuit further comprises: an analysis circuit coupled to the decoder and the serial debugging access port, and judging a first transmission direction of the first data signal and the first clock signal according to the first data signal, so as to transmit the first data signal and the first clock signal to the serial debugging access port; wherein the analysis circuit further judges, according to the first data signal, to receive a second data signal and a second clock signal from the serial debugging access port from a second transmission direction. As in claim 4, the above-mentioned serial debugging interface circuit further comprises: an encoding circuit coupled to the above-mentioned analysis circuit, receiving the above-mentioned second data signal and the above-mentioned second clock signal, and encoding the above-mentioned second data signal and the above-mentioned second clock signal to generate a second encoded data. A microprocessor device includes: a serial debug interface circuit coupled to a debugger via a pin to receive an output signal via the pin, and decode a first coded signal to generate a first data signal and a first clock signal, wherein the output signal is the first coded signal or a reset signal; and the first coded signal is generated by encoding the first data signal and the first clock signal; and a serial debug access port coupled to the serial debug interface circuit to receive the first data signal and the first clock signal from the serial debug interface circuit to debug the microprocessor device. The microprocessor device of claim 6 further includes: a judgment circuit, judging whether a cycle time of the output signal is greater than a critical value, so as to judge whether the output signal is the first coded signal or the reset signal; wherein when the cycle time of the output signal is greater than the critical value, the judgment circuit judges that the output signal is the reset signal, and when the cycle time of the output signal is not greater than the critical value, the judgment circuit judges that the output signal is the first coded signal. The microprocessor device of claim 7 further includes: a decoder coupled to the judgment circuit and decoding the first coded signal to generate the first data signal and the first clock signal. A debugging method is applicable to a debugging system, wherein the debugging system includes a debugger and a target device, wherein the debugger is coupled to the debugger via a pin, and the debugging method includes: outputting an output signal through the debugger, wherein the output signal is a first coded signal or a reset signal, and the first coded signal is generated by encoding a first data signal and a first clock signal; A serial debugging of the target device The interface circuit receives the above-mentioned coding signal or the above-mentioned reset signal through the above-mentioned pin; when the above-mentioned output signal is the above-mentioned first coding signal, the above-mentioned first coding signal is decoded by the above-mentioned serial debugging interface circuit to generate the above-mentioned first data signal and the above-mentioned first clock signal; and the above-mentioned first data signal and the above-mentioned first clock signal are received from the above-mentioned serial debugging interface circuit through a serial debugging access port of the above-mentioned target device to debug the above-mentioned target device. The debugging method of claim 9 further includes: determining a first transmission direction of the first data signal and the first clock signal by an analysis circuit of the serial debugging interface circuit according to the first data signal, so as to transmit the first data signal and the first clock signal to the serial debugging access port; or determining receiving a second data signal and a second clock signal from the serial debugging access port from a second transmission direction by the analysis circuit of the serial debugging interface circuit according to the first data signal.