TWI837033B - Pixel circuit - Google Patents

Abstract

A pixel circuit is provided. The pixel circuit includes a light emitting element, a reference capacitor, a reset circuit, an input circuit and a driving circuit. The reference capacitor is coupled between a first node and a second node. The reset circuit is coupled to the first node. The reset circuit provides a first reference bias voltage to the first node during a reset period. The input circuit is coupled to the second node. The input circuit provides a second reference bias voltage to the second node during the reset period, and provides a data voltage during a data input period. A control terminal of a driving transistor of the driving circuit is coupled to the first node. The driving circuit uses the driving transistor and a driving voltage to compensate a voltage value on the first node during a compensation period. The driving circuit drives the light-emitting element according to the data voltage and the driving voltage during the light-emitting period.

Description

Pixel circuit

The present invention relates to a pixel circuit, and in particular, to a pixel circuit with a compensation function.

Each of the plurality of pixel circuits in current display devices includes a driving circuit and a light-emitting element. The light-emitting element can be any form of light-emitting diode element. The driving circuit can drive the light-emitting element based on the light-emitting enable signal. However, the driving transistor in the driving circuit has a threshold voltage (Vth) value. Based on differences in manufacturing processes, the threshold voltage values of the driving transistors in the plurality of pixel circuits of the display device may be different. Therefore, in order to improve the luminescence uniformity of the display device, the driving circuit must compensate the voltage value at the control terminal of the driving transistor according to the critical voltage value of the driving transistor.

Please refer to Figure 1 and Figure 2 at the same time. Figure 1 is a circuit diagram of a current pixel circuit. FIG. 2 is a signal timing diagram based on FIG. 1 . The pixel circuit 10 includes a light emitting element LE, transistors T1 to T9, and capacitors C1 and C2. The first terminal of the transistor T1 is coupled to the driving voltage VDD. The second terminal of the transistor T1 is coupled to the node P. The control terminal of the transistor T1 receives the luminescence enable signal EM(n). Transistor T2 is the pixel circuit 10 drive transistor in the. The first terminal of the transistor T2 is coupled to the node P. The first terminal of the transistor T3 is coupled to the second terminal of the transistor T2. The second terminal of the transistor T3 is coupled to the control terminal of the transistor T2. The control terminal of the transistor T3 receives the scan signal SN(n). The first terminal of the transistor T4 is coupled to the second terminal of the transistor T2. The second terminal of the transistor T4 is coupled to the anode of the light emitting element LE. The control terminal of the transistor T4 receives the luminescence enable signal EM(n). The first terminal of the transistor T5 is coupled to the control terminal of the transistor T2. The second terminal of the transistor T5 is coupled to the reference voltage VREF1. The control terminal of the transistor T5 receives the scan signal SN(n-1). Capacitor C1 is coupled between the control terminal of transistor T2 and node Q. Capacitor C2 is coupled between node P and node Q. The first terminal of transistor T6 is coupled to node Q. The second terminal of the transistor T6 is coupled to the reference voltage VREF1. The control terminal of the transistor T6 receives the scan signal SN(n-1). The first terminal of transistor T7 is coupled to node Q. The second terminal of the transistor T7 is coupled to the reference voltage VREF1. The control terminal of the transistor T7 receives the scan signal SN(n). The first terminal of transistor T8 receives data voltage VDATA. The second terminal of transistor T8 is coupled to node Q. The control terminal of the transistor T8 receives the scan signal SN(n+1). The first terminal of the transistor T9 is coupled to the reference voltage VREF2. The second terminal of transistor T8 is coupled to node P. The control terminal of the transistor T8 receives the auxiliary scanning signal VC(n).

Based on the timing as shown in Figure 2, during the reset period PR, the voltage value at the node P, the voltage value at the node Q, and the voltage value Vg at the control end of the transistor T2 are reset. During the compensation period PC, the voltage value Vg at the control end of the transistor T2 is equal to the voltage value of the reference voltage VREF2 minus the voltage difference of the critical voltage value of the transistor T2. That is, Vg=Vr2-|Vth|. "Vr2" is the voltage value of the reference voltage VREF2. "Vth" is the critical voltage value of the transistor T2. During the data input period PD, the voltage value Vg at the control end of the transistor T2 is as shown in formula (1).

Vg=Vr2-｜Vth｜+(Vd-Vr1)×Cc1/(Cc1+Ct1)...Formula (1)

"Vd" is the voltage value of the data voltage VDATA. "Vr1" is the voltage value of the reference voltage VREF1. "Cc1" is the capacitance value of capacitor C1. "Ct1" is the equalizing capacitance value located at the control end of transistor T2.

During the light-emitting period TE, the voltage value Vg located at the control terminal of the transistor T2 is shown in formula (2).

Vg=Vr2-|Vth|+(Vd-Vr1)×Cc1/(Cc1+Ct1)+(vVDD-Vrr2)×Cc2/(Cc1+Cc2+Ct2)×Cc1/(Cc1+Ct1)...Formula ( 2)

"vVDD" is the voltage value of the driving voltage VDD. "Vr1" is the voltage value of the reference voltage VREF1. "Cc2" is the capacitance value of capacitor C2. "Ct2" is the equal-correction capacitance value at node Q.

The pixel circuit 10 may exclude the critical voltage value of the transistor T2 based on the compensation of equation (2). It should be noted that an equal-correction capacitance value at the control terminal of the transistor T2 (ie, an equal-correction capacitance value Ct1) and an equal-correction capacitance value at the node Q (ie, an equal-correction capacitance value Ct2) are generated. Therefore, in order to eliminate the equal-correction capacitance value at the control terminal of the transistor T2 and the equal-correction capacitance value at the node Q, the areas of the capacitors C1 and C2 must be increased. In fact, Cc2/(Cc1+Cc2+Ct2) in formula (2) cannot be equal to 1 or 0. Therefore, the equal-correction capacitance value located at the control terminal of the transistor T2 and the equal-correction capacitance value located at the node Q cannot be significantly eliminated (or ignored). Therefore, the pixel circuit 10 cannot provide accurate compensation. It can be seen from this that the equalizer located at the control end of transistor T2 The capacitance value and the equal capacitance value at node Q will still affect the operation of transistor T2. Pixel circuits cannot provide precise compensation.

Therefore, how to provide a pixel circuit with accurate compensation function is one of the research focuses of technicians in this field.

The invention provides a pixel circuit with precise compensation function.

The pixel circuit of the present invention includes a light-emitting element, a reference capacitor, a reset circuit, an input circuit and a driving circuit. The reference capacitor is coupled between the first node and the second node. The reset circuit is coupled to the first node. The reset circuit provides a first reference bias voltage to the first node during reset. The input circuit is coupled to the second node. The input circuit provides a second reference bias voltage to the second node during the reset period and provides a data voltage during the data input period. The driving circuit is coupled to the driving voltage, the first node and the light-emitting element. The drive circuit includes drive transistors. The control terminal of the driving transistor is coupled to the first node. The driving circuit uses the driving transistor and the driving voltage to compensate the voltage value at the first node during the compensation period after the reset period. The input circuit provides the data voltage to the second node during the data input period after the compensation period. During the light-emitting period, the driving circuit drives the light-emitting element according to the material voltage and the driving voltage.

Based on the above, the pixel circuit includes a single capacitor (ie, a reference capacitor). This enables the influence of the equalization capacitance value at the first node to be significantly reduced. The equalization capacitance value at the first node is ignored. In this way, the pixel circuit can provide a precise compensation function.

10, 100, 200, 300: pixel circuit

110, 210: Reset circuit

120, 220, 320: Input circuit

130, 230: driving circuit

A(n), B(n), P, Q: nodes

C1, C2, CB, CC1, CC2: capacitors

CA: Reference capacitor

CK1, CK3: clock signal

EM(n): Luminous Enablement Signal

LE: Light-emitting element

PC: Compensation period

PD: Data input period

PE: Luminescence period

PR: during reset

SN(n-1), SN(n), SN(n+1): scanning signal

SR(n): shift register unit

T1~T9, TS1~TS8: transistors

TB1, TB2: bias transistor

TC1, TC2: Compensation transistors

TD: drive transistor

TE1, TE2: enabling transistor

TI: Input transistors

tp1~tp6: time point

TR: Reset transistor

V1: voltage difference

V2: operating voltage value

VC(n-1), VC(n): auxiliary scanning signal

VDATA: data voltage

VDD, VSS: driving voltage

VGH, VGL: Gate voltage

VREF1: First reference bias voltage

VREF2: Second reference bias voltage

Figure 1 is a circuit diagram of a current pixel circuit.

Figure 2 is a signal timing diagram based on Figure 1.

FIG. 3 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

FIG4 is a circuit diagram of a pixel circuit according to the first embodiment of the present invention.

FIG. 5 is a signal timing diagram based on the pixel circuit shown in FIG. 4 .

FIG6 is a circuit diagram of a pixel circuit according to the second embodiment of the present invention.

FIG7 is a signal timing diagram of the pixel circuit shown in FIG6.

FIG8 is a circuit diagram of the shift register unit shown in FIG4.

FIG. 9 is a circuit diagram of the shift register unit shown in FIG. 6 .

Some embodiments of the present invention will be described in detail with reference to the accompanying drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementation methods of the present invention. More precisely, these embodiments are only examples within the scope of the patent application of the present invention.

Please refer to FIG. 3, which is a schematic diagram of a pixel circuit according to the first embodiment of the present invention. In this embodiment, the pixel circuit 100 includes a light-emitting element LE, a reference capacitor CA, a reset circuit 110, an input circuit 120, and a driving circuit 130. The light-emitting element LE can be a light-emitting diode element in any form. The light-emitting element LE can include, for example, an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, or a quantum dot light-emitting diode (quantum dot LED). The anode of the light-emitting element LE is coupled to the driving circuit 130. The cathode of the light-emitting element LE is coupled to the driving voltage VSS.

In this embodiment, the reference capacitor CA is coupled between node P and node Q. Reset circuit 110 is coupled to node P. The reset circuit 110 provides the first reference bias voltage VREF1 to the node P during the reset period. Input circuit 120 is coupled to node Q. The input circuit 120 provides the second reference bias voltage VREF2 to the node Q during the reset period. Input circuit 120 provides data voltage VDATA during data input.

In this embodiment, the driving circuit 130 is coupled to the driving voltage VDD, the node P and the light-emitting element LE. The driving circuit 130 includes a driving transistor TD. The control end of the driving transistor TD is coupled to the node P. The driving circuit 130 uses the driving transistor TD and the driving voltage VDD to compensate for the voltage value at the node P during the compensation period. The compensation period of this embodiment is after the reset period. The input circuit 120 provides the data voltage VDATA to the node Q during the data input period. The data input period of this embodiment is after the compensation period. In addition, the driving circuit 130 drives the light-emitting element LE according to the data voltage VDATA and the driving voltage VDD during the light-emitting period.

It is worth mentioning here that the pixel circuit 100 includes a single capacitor (ie, reference capacitor CA). Using the reference capacitor CA, the influence of the equalizing capacitance value at node P can be significantly reduced. The equal-correction capacitance value at node P (ie, the equal-correction capacitance value at the control terminal of the driving transistor TD) is ignored. In this way, the pixel battery Road 100 can provide precise compensation function based on.

In this embodiment, the driving transistor TD is implemented by a P-type field effect transistor (FET). The present invention is not limited to the form of the FET in this embodiment. The driving transistor TD of the present invention can be implemented by any form of FET.

In this embodiment, during the compensation period, the voltage value at node P is the voltage difference V1 between the voltage value of the driving voltage VDD and the absolute value of the critical voltage value of the driving transistor TD. Specifically, during the compensation period, the voltage value at node P is shown in formula (3).

Vg=vVDD-|Vth|=V1...Formula (3)

"Vg" is the voltage value located at node P and also the voltage value located at the control terminal of the driving transistor TD. "vVDD" is the voltage value of the driving voltage VDD. "Vth" is the critical voltage value of the drive transistor TD.

During data input, the voltage value at node P is the sum of the voltage difference value V1 and the operating voltage value V2. The operating voltage value V2 is generated based on the voltage value of the data voltage VDATA, the voltage value of the second reference bias voltage VREF2, the capacitance value of the reference capacitor CA and the equal calibration capacitance value at the node P.

Specifically, during the data input period, the operating voltage value V2 is as shown in formula (4).

V2=(Vd-Vr2)×Cc1/(Cc1+Ct1)...Formula (4)

"Vd" is the voltage value of the data voltage VDATA. "Vr2" is the voltage value of the reference voltage VREF2. "Cc1" is the capacitance value of capacitor C1. "Ct1" is located at node The equal calibration capacitance value of P. "Ct1" is also the equalizing capacitance value located at the control end of the drive transistor TD.

Therefore, the voltage value at node P is as shown in formula (5).

Vg=V1+V2=(vVDD-｜Vth｜)+( Vd - Vr 2)×Cc1/(Cc1+Ct1)...Formula (5)

In addition, during the light emitting period, the driving circuit 130 drives the light emitting element LE using the voltage value generated by equation (6).

Vdr=V1+V2-vVDD-Vth=V2...Formula (6)

"Vdr" is the voltage value of the driving circuit 130 to drive the light-emitting element LE. It should be noted that in this embodiment, the critical voltage value of the driving transistor TD is a negative value. Therefore, the driving circuit 130 drives the light-emitting element LE according to the operating voltage value V2. The influence caused by the voltage value of the driving voltage VDD and the critical voltage value of the driving transistor TD is reduced. In other words, the pixel circuit 100 will not be affected by the change of the driving voltage VDD and the change of the critical voltage value of the driving transistor TD to affect the light emission of the light-emitting element LE.

It should also be noted that, as shown in formula (4), the operating voltage value V2 is related to the voltage value of the data voltage VDATA, the voltage value of the second reference bias voltage VREF2, the capacitance value of the reference capacitor CA and the equal calibration value at the node P. capacitance value. In addition, the capacitance value of the reference capacitor CA is designed to be significantly larger than the equal calibration capacitance value at the node P. Therefore, the equal-correction capacitance value at node P can be ignored.

Please refer to FIG. 4, which is a circuit diagram of a pixel circuit according to the first embodiment of the present invention. In this embodiment, the pixel circuit 200 includes a light-emitting element LE, a reference capacitor CA, a reset circuit 210, an input circuit 220, and a drive circuit 230. The reference capacitor CA is coupled between the node P and the node Q. The reset circuit 210 includes a reset transistor TR. The first end of the reset transistor TR is coupled to the node P. The second end of the reset transistor TR is coupled to the first reference bias voltage VREF1. The control end of the reset transistor TR receives the scanning signal SN(n-1) (or the first scanning signal). In this embodiment, the reset transistor TR is turned on in response to the pulse of the scanning signal SN(n-1) during the reset period.

Input circuit 220 includes input transistor TI. The first terminal of the input transistor TI receives the data voltage VDATA. The second terminal of the input transistor TI is coupled to the node Q. The control end of the input transistor TI receives the scan signal SN(n+1) (or the second scan signal). In this embodiment, the input transistor TI is turned on in response to the pulse wave of the scan signal SN(n+1) during the data input period to provide the data voltage VDATA to the node Q.

Input circuit 220 also includes bias transistor TB1. The first terminal of the bias transistor TB1 is coupled to the second reference bias voltage VREF2. The second terminal of the bias transistor TB1 is coupled to the node Q. The control terminal of the bias transistor TB1 receives the auxiliary scanning signal VC(n-1). The bias transistor TB1 is turned on in response to the auxiliary scan signal VC(n-1) during the reset period and the compensation period to provide the second reference bias voltage VREF2 to the node Q.

Input circuit 220 also includes capacitor CB. The capacitor CB is coupled between the second reference bias voltage VREF2 and the node Q. The capacitor CB is used to maintain the voltage difference between the second reference bias voltage VREF2 and the node Q. However, the present invention does not use the method of this embodiment Capacitor CB coupling mode is limited. One end of the capacitor CB of the present invention is coupled to the node Q. The other end of the capacitor CB can be coupled to any voltage source. The voltage source may be one of the driving voltages VDD, VSS, the first reference bias VREF1 and the second reference bias VREF2. In some embodiments, capacitor CB may be omitted.

In the present embodiment, the driving circuit 230 includes a driving transistor TD, compensation transistors TC1, TC2, and enabling transistors TE1, TE2. The control end of the driving transistor TD is coupled to the node P. The first end of the compensation transistor TC1 is coupled to the driving voltage VDD. The second end of the compensation transistor TC is coupled to the first end of the driving transistor TD. The control end of the compensation transistor TC receives the scanning signal SN(n) (or the third scanning signal). The first end of the compensation transistor TC2 is coupled to the second end of the driving transistor TD. The second end of the compensation transistor TC2 is coupled to the control end of the driving transistor TD. The control end of the compensation transistor TC2 receives the scanning signal SN(n). The compensation transistors TC1 and TC2 are turned on in response to the pulse of the scanning signal SN(n) during the compensation period.

Taking this embodiment as an example, the scan signal SN(n-1) is the previous stage scan signal of the scan signal SN(n). The scanning signal SN(n+1) is the subsequent scanning signal of the scanning signal SN(n).

In this embodiment, the first terminal of the enabling transistor TE1 is coupled to the driving voltage VDD. The second terminal of the enabling transistor TE1 is coupled to the first terminal of the driving transistor TD. The control terminal of the enabling transistor TE1 receives the luminescence enabling signal EM(n). The first terminal of the enabling transistor TE2 is coupled to the second terminal of the driving transistor TD. The second terminal of the enabling transistor TE2 is coupled to the light emitting element LE. The control terminal of the enabling transistor TE2 receives the luminescence enabling signal EM(n). The second terminal of the enabling transistor TE2 in this embodiment is coupled to on the anode of the light-emitting element LE. The cathode of the light-emitting element LE is coupled to the driving voltage VSS. The enabling transistors TE1 and TE2 are respectively turned on in response to the pulse wave of the luminescence enabling signal EM(n) during the light-emitting period.

In this embodiment, the driving voltage VDD can be a system high voltage. The driving voltage VSS can be a system low voltage.

In this embodiment, the reset transistor TR, the input transistor TI, the bias transistor TB1, the driving transistor TD, the compensation transistors TC1 and TC2 and the enabling transistors TE1 and TE2 are respectively implemented as P-type FETs. . The present invention is not limited to the form of the FET in this embodiment.

Please refer to FIG. 4 and FIG. 5 at the same time. FIG. 5 is a signal timing diagram based on the pixel circuit shown in FIG. 4 . In this embodiment, at time point tp1, the auxiliary scanning signal VC(n-1) begins to have a negative pulse wave. Therefore, the reset period PR begins. Between time point tp1 and time point tp3, the bias transistor TB1 is turned on in response to the negative pulse wave of the auxiliary scanning signal VC(n-1). Therefore, the voltage value at node Q is substantially equal to the voltage value of the second reference bias voltage VREF2. During the reset period PR, between time point tp2 and time point tp3, the reset transistor TR is turned on in response to the negative pulse wave of the scan signal SN(n-1). Therefore, the voltage value at the node P is substantially equal to the voltage value of the first reference bias voltage VREF1. Based on the above, during the reset period PR, the voltage value at the node P is reset to the voltage value of the first reference bias VREF1. The first reference bias voltage VREF1 is, for example, a low voltage value or a negative voltage value. The voltage value at node Q is reset to the voltage value of the second reference bias voltage VREF2.

At time point tp3, the reset period PR ends. The reset transistor TR is disconnected open. During the compensation period PC between time point tp3 and time point tp4, the scanning signal SN(n) has a negative pulse wave. Both compensation transistors TC1 and TC2 are turned on. Therefore, the driving circuit 230 uses the charging path formed by the compensation transistors TC1 and TC2 and the driving transistor TD to perform a charging operation on the node P (ie, the control terminal of the driving transistor TD). When the voltage value at node P satisfies formula (3), the driving transistor TD will be turned off. Therefore, when the charging operation ends, the voltage value at the node P is the voltage difference V1 between the voltage value of the driving voltage VDD and the critical voltage value of the driving transistor TD.

At time point tp4, the compensation period PC ends. Bias transistor TB1 and compensation transistors TC1 and TC2 are disconnected. During the data input period PD between time point tp4 and time point tp5, the scanning signal SN(n+1) has a negative pulse wave. Therefore, the input transistor TI is turned on. The turned-on input transistor TI provides the data voltage VDATA to node Q.

At time point tp5, the data input period PD ends. The input transistor TI is disconnected. During the luminescence period PE between time point tp5 and time point tp6, the luminescence enable signal EM(n) has a negative pulse. The enable transistors TE1 and TE2 are turned on. Therefore, the voltage value at the node P satisfies formula (5). Therefore, the driving circuit 230 drives the light-emitting element LE according to the operating voltage value (i.e., the operating voltage value V2 in formula (5)). The operating voltage value is shown in formula (4). When the capacitance value of the reference capacitor CA is designed to be significantly larger than the calibrated capacitance value at the node P, the calibrated capacitance value at the node P can be ignored.

It should be noted that the number of transistors coupled to node Q in this embodiment is less than the number of transistors coupled to node Q shown in FIG. 1 . Therefore, in this implementation In this example, the equal capacitor at node Q has a lower value. In addition, the known capacitance value of the capacitor CB in this embodiment is designed to be significantly larger than the parasitic capacitance value of the input transistor TI coupled to the node Q and the parasitic capacitance value of the bias transistor TB1. For example, the capacitance value of capacitor CB can be designed to be greater than 100 times the parasitic capacitance value. Therefore, the parasitic capacitance value of the input transistor TI and the parasitic capacitance value of the bias transistor TB1 can be ignored.

Please refer to FIG. 6 , which is a circuit diagram of a pixel circuit according to a second embodiment of the present invention. In this embodiment, the pixel circuit 300 includes a light emitting element LE, a reference capacitor CA, a reset circuit 210, an input circuit 320 and a driving circuit 230. In this embodiment, the implementation of the light emitting element LE, the reference capacitor CA, the reset circuit 210 and the driving circuit 230 has been clearly explained in the embodiment of FIG. 4 and will not be repeated here.

In this embodiment, the input circuit 320 includes an input transistor TI, bias transistors TB1 and TB2 and a capacitor CB. The first terminal of the input transistor TI receives the data voltage VDATA. The second terminal of the input transistor TI is coupled to the node Q. The control terminal of the input transistor TI receives the scan signal SN(n+1). The first terminal of the bias transistor TB1 is coupled to the second reference bias voltage VREF2. The second terminal of the bias transistor TB1 is coupled to the node Q. The control terminal of the bias transistor TB1 receives the scan signal SN(n-1). The first terminal of the bias transistor TB2 is coupled to the second reference bias voltage VREF2. The second terminal of the bias transistor TB2 is coupled to the node Q. The control terminal of the bias transistor TB2 receives the scan signal SN(n). The bias transistor TB1 is turned on in response to the scan signal SN(n-1). The bias transistor TB2 is turned on in response to the scan signal SN(n). Capacitor CB coupling Between the second reference bias voltage VREF2 and node Q.

Please refer to FIG. 6 and FIG. 7 at the same time. FIG. 7 is a signal timing diagram of the pixel circuit shown in FIG. 6. In this embodiment, during the reset period PR between time point tp1 and time point tp2, the scanning signal SN(n-1) has a negative pulse. The bias transistor TB1 and the reset transistor TR are turned on in response to the negative pulse of the scanning signal SN(n-1). Therefore, the voltage value at the node Q is substantially equal to the voltage value of the second reference bias voltage VREF2. The voltage value at the node P is substantially equal to the voltage value of the first reference bias voltage VREF1.

At time point tp2, the reset period PR ends. The bias transistor TB1 and the reset transistor TR are disconnected. During the compensation period between time point tp2 and time point tp3, the scanning signal SN(n) has a negative pulse. The bias transistor TB2 and the compensation transistors TC1 and TC2 are all turned on. The drive circuit 230 uses the charging path formed by the compensation transistors TC1, TC2 and the drive transistor TD to charge the node P (i.e., the control end of the drive transistor TD). Therefore, when the charging operation ends, the voltage value at the node P is the voltage difference V1 between the voltage value of the drive voltage VDD and the critical voltage value of the drive transistor TD.

At time point tp3, the compensation period PC ends. The bias transistor TB2 and the compensation transistors TC1 and TC2 are disconnected. During the data input period PD between time point tp3 and time point tp4, the scanning signal SN(n+1) has a negative pulse. Therefore, the input transistor TI is turned on. The turned-on input transistor TI provides the data voltage VDATA to the node Q.

At time point tp4, the data input period PD ends. The input transistor TI is disconnected. During the luminescence period PE between time point tp4 and time point tp5, the luminescence enable signal EM(n) has a negative pulse. The enable transistors TE1 and TE2 are turned on. Therefore, the voltage value at the node P satisfies formula (5). Therefore, the driving circuit 230 drives the light-emitting element LE according to the operating voltage value (i.e., the operating voltage value V2 in formula (5)). The operating voltage value is shown in formula (4). When the capacitance value of the reference capacitor CA is designed to be significantly larger than the equal calibration capacitance value at the node P, the equal calibration capacitance value at the node P can be ignored.

Please refer to Figures 4 and 8 at the same time. Figure 8 is a circuit diagram of the shift register unit shown in Figure 4. In the present embodiment, the shift register unit SR(n) is applicable to the pixel circuit 200. In the present embodiment, the shift register unit SR(n) includes transistors TS1~TS8 and capacitors CC1 and CC2. The first end of transistor TS1 and the control end of transistor TS1 receive the scanning signal SN(n-1). The second end of transistor TS1 is coupled to node A(n). The first end of transistor TS2 receives the clock signal CK1. The second end of transistor TS2 is used to output the scanning signal SN(n). The control end of transistor TS2 is coupled to node A(n). Capacitor CC1 is coupled between the second end of transistor TS2 and the control end of transistor TS2. The first end of transistor TS3 is coupled to node B(n). The second end of transistor TS3 and the control end of transistor TS3 receive the clock signal CK3. The first end of transistor TS4 is coupled to node B(n). The second end of transistor TS4 receives the gate voltage VGH. The control end of transistor TS4 is coupled to node A(n). The first end of transistor TS5 is coupled to node A(n). The second end of transistor TS5 receives the gate voltage VGH. The control end of transistor TS5 is coupled to node B(n). The first end of transistor TS6 is coupled to the second end of transistor TS2. The second end of transistor TS6 receives the gate voltage VGH. The control end of transistor TS6 is coupled to node B(n).

The first end of transistor TS7 receives the gate voltage VGL. The second end of transistor TS7 is used to output the auxiliary scanning signal VC(n). The control end of transistor TS7 is coupled to node A(n). Capacitor CC2 is coupled between the second end of transistor TS7 and the control end of transistor TS7. The first end of transistor TS8 is coupled to the second end of transistor TS7. The second end of transistor TS8 receives the gate voltage VGH. The control end of transistor TS8 is coupled to node B(n).

In this embodiment, transistors TS1~TS8 are implemented as P-type FETs respectively. The present invention is not limited to the form of FETs in this embodiment. Gate voltage VGH is a gate high voltage. Gate voltage VGL is a gate low voltage. In this embodiment, the negative pulse width of the auxiliary scanning signal VC(n) is equal to the time length of the low voltage value at node A(n). The negative pulse width of the scanning signal SN(n) is equal to the negative pulse width of the clock signal CK1. Therefore, the negative pulse width of the auxiliary scanning signal VC(n) is greater than the negative pulse width of the scanning signal SN(n).

In this embodiment, the shift register unit SR(n) can use the negative pulse of the clock signal CK3 to reset the voltage value at the node A(n) to a high voltage value. At the same time, the voltage value at the node B(n) is set to a low voltage value. Therefore, transistors TS5, TS6, and TS8 respond to the low voltage value at the node B(n) to suppress the noise at the node A(n), the noise at the second end of the transistor TS2, and the noise at the second end of the transistor TS7.

It should be understood that the shift register unit SR(n-1) (not shown) of the previous stage of the shift register unit SR(n) provides the auxiliary scanning signal VC(n-1) and the scanning signal SN(n-1). The shift register unit SR(n+1) (not shown) of the next stage of the shift register unit SR(n) provides at least the scanning signal SN(n+1).

Please refer to FIG. 6 and FIG. 9 at the same time. FIG. 9 is a circuit diagram of the shift register unit shown in FIG. 6. In this embodiment, the shift register unit SR(n) is applicable to the pixel circuit 300. In this embodiment, the shift register unit SR(n) includes transistors TS1-TS6 and capacitor CC1. The coupling method of the transistors TS1-TS6 and the capacitor CC1 of this embodiment is the same as the coupling method of the transistors TS1-TS6 and the capacitor CC1 shown in FIG. 8, so it will not be repeated here.

In this embodiment, the shift register unit SR(n) can use the negative pulse of the clock signal CK3 to reset the voltage value at the node A(n) to a high voltage value. At the same time, the voltage value at node B(n) is set to a low voltage value. Therefore, the transistors TS5 and TS6 respond to the low voltage value at the node B(n) to suppress the noise at the node A(n) and the noise at the second terminal of the transistor TS2.

It should be understood that the shift register unit SR(n-1) (not shown) of the previous stage of the shift register unit SR(n) provides the scanning signal SN(n-1). The shift register unit SR(n+1) (not shown) of the next stage of the shift register unit SR(n) provides the scanning signal SN(n+1).

In summary, the pixel circuit includes a single capacitor (ie, a reference capacitor). By using the reference capacitor, the influence of the calibrated capacitance value at the first node can be greatly reduced. The calibrated capacitance value at the first node is ignored. In this way, the pixel circuit can provide a precise compensation function.

Although the present invention has been disclosed above through embodiments, it is not intended to limit the scope of the present invention. Any person with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the invention shall be deemed to be defined by the appended patent application scope. Accurate.

100:Pixel circuit

110:Reset circuit

120:Input circuit

130:Drive circuit

CA: Reference capacitor

LE: light emitting element

P, Q: Node

TD: drive transistor

V1: voltage difference

V2: Operating voltage value

VDATA: data voltage

VDD, VSS: driving voltage

VREF1: First reference bias voltage

VREF2: second reference bias voltage

Claims (15)

A pixel circuit includes: a light-emitting element; a reference capacitor coupled between a first node and a second node; a reset circuit coupled to the first node and configured to provide a first reference bias voltage to the first node during a reset period; an input circuit coupled to the second node and configured to provide a second reference bias voltage to the second node during the reset period and to provide a data voltage during a data input period; and a drive circuit coupled to a drive voltage, the first node, and the light-emitting element. The device comprises a driving circuit including a driving transistor, wherein the control end of the driving transistor is coupled to the first node, wherein the driving circuit uses the driving transistor and the driving voltage to compensate the voltage value at the first node during a compensation period after the reset period, wherein the input circuit provides a data voltage to the second node during the data input period after the compensation period, and wherein the driving circuit drives the light-emitting element according to the data voltage and the driving voltage during a light-emitting period. A pixel circuit as described in claim 1, wherein during the compensation period, the voltage value at the first node is a voltage difference between the voltage value of the driving voltage and the absolute value of the critical voltage value of the driving transistor. A pixel circuit as described in claim 2, wherein: During the data input period, the voltage value at the first node is the sum of the voltage difference and an operating voltage value, and the operating voltage value is generated according to the voltage value of the data voltage, the voltage value of the second reference bias voltage, the capacitance value of the reference capacitor, and a calibration capacitance value at the first node. A pixel circuit as described in claim 3, wherein during the light-emitting period, the driving circuit drives the light-emitting element according to the operating voltage value. The pixel circuit of claim 1, wherein the reset circuit includes: a reset transistor, a first terminal of the reset transistor is coupled to the first node, and a second terminal of the reset transistor is coupled to the first node. Connected to the first reference bias, the control terminal of the reset transistor receives a first scan signal, wherein the reset transistor is turned on in response to the pulse wave of the first scan signal during the reset period. The pixel circuit of claim 5, wherein the input circuit includes: an input transistor, a first terminal of the input transistor receives the data voltage, and a second terminal of the input transistor is coupled to the second node, The control terminal of the input transistor receives a second scan signal. The pixel circuit as described in claim 6, wherein the input circuit further comprises: a bias transistor, the first end of the bias transistor is coupled to the second reference bias, the second end of the bias transistor is coupled to the second node, and the control end of the bias transistor receives an auxiliary scanning signal. The pixel circuit of claim 7, wherein the input circuit further includes: a capacitor coupled between a voltage source and the second node, wherein the voltage source is the driving voltage, the first reference bias voltage and one of the second reference bias voltages. A pixel circuit as described in claim 7, wherein the bias transistor is turned on in response to the auxiliary scanning signal during the reset period and the compensation period to provide the second reference bias to the second node. The pixel circuit of claim 6, wherein the input circuit further includes: a first bias transistor, a first terminal of the first bias transistor is coupled to the second reference bias, and the first bias transistor The second end of the piezoelectric crystal is coupled to the second node, the control end of the first bias transistor receives the first scan signal; and a second bias transistor, the second bias transistor has a One end is coupled to the second reference bias, a second end of the second bias transistor is coupled to the second node, and a control end of the second bias transistor receives a third scan signal. The pixel circuit of claim 10, wherein: the first bias transistor is turned on in response to the first scan signal during the reset period, and the second bias transistor is turned on in response to the compensation period. The third scan signal is turned on. The pixel circuit of claim 1, wherein the driving circuit further includes: a first compensation transistor, a first terminal of the first compensation transistor coupled to the driving voltage, and a second terminal of the first compensation transistor. The terminal is coupled to the first terminal of the driving transistor, the control terminal of the first compensation transistor receives a third scan signal; and a second compensation transistor, the first terminal of the second compensation transistor is coupled to The second terminal of the driving transistor and the second terminal of the second compensation transistor are coupled to the control terminal of the driving transistor, and the control terminal of the second compensation transistor receives the third scan signal. The pixel circuit of claim 12, wherein the first compensation transistor and the second compensation transistor are respectively turned on in response to the pulse wave of the third scanning signal during the compensation period. The pixel circuit as described in claim 12, wherein the driving circuit further comprises: a first enabling transistor, the first end of the first enabling transistor is coupled to the driving voltage, the second end of the first enabling transistor is coupled to the first end of the driving transistor, and the control end of the first enabling transistor receives a light-emitting enabling signal; a second enabling transistor, the first end of the second enabling transistor is coupled to the second end of the driving transistor, the second end of the second enabling transistor is coupled to the light-emitting element, and the control end of the second enabling transistor receives the light-emitting enabling signal. A pixel circuit as described in claim 14, wherein the first enabling transistor and the second enabling transistor are respectively turned on in response to the pulse of the light-emitting enabling signal during the light-emitting period.

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