TWI799054B - Driving circuit for driving light emitting diode - Google Patents

Abstract

The disclosure provides a driving circuit which is used to drive a light emitting diode (LED). The driving circuit includes a driving transistor, a switching transistor and a capacitor. The driving transistor has a first source and a first drain, the first source receives a first direct-current (DC) voltage, the first drain has a first voltage value, furthermore, the driving transistor is used to generate a driving current to drive the LED according to the first voltage value of the first drain. The switching transistor is coupled to the first drain of the driving transistor and receives a first control signal. The capacitor is coupled to the switching transistor and receives a second control signal. Wherein, the switching transistor and the capacitor are used to adjust the first voltage value of the first drain according to the first control signal and the second control signal, to cause the driving current reach a saturated current value.

Description

Driving circuit for driving light-emitting diodes

The present disclosure relates to an electronic circuit, in particular to a driving circuit for driving light-emitting diodes of display pixels.

Display pixels use light-emitting diodes (for example, organic light-emitting diodes (OLEDs)) to provide light sources, and the brightness of the light source of the light-emitting diodes is closely related to the current size of the driving current used to drive the light-emitting diodes . Moreover, the magnitude of the driving current depends on the device characteristics of the driving transistor providing the driving current, and also depends on the circuit structure including the overall driving circuit. Therefore, in order to achieve the shortest optical response time of the light-emitting diode, the driving transistor must have a faster response speed.

For the conventional drive circuit, limited by its circuit structure design, the upper limit of the source-drain cross voltage of the drive transistor is roughly equal to the critical voltage of the drive transistor, so the source-drain The cross voltage cannot be further increased, so that the driving transistor cannot quickly enter the saturation region so that the driving current reaches the saturation current value; therefore, the conventional driving transistor cannot further increase its response speed.

Aiming at the above-mentioned technical problems existing in the known driving circuit, technicians in related industries in this technical field are devoting themselves to research and development of an improved driving circuit, hoping to improve the driving performance. The response speed of the electrokinetic crystal can obtain better optical performance of the display, and can have a better user experience visually.

In the technical solution of this disclosure, a switching transistor and a capacitor are added to the driving circuit, and the voltage value of the drain of the driving transistor can be adjusted through the switching transistor and the capacitor according to the corresponding control signal or DC voltage, and can stabilize Maintain the above-mentioned drain voltage value, so that the source-drain cross voltage of the driving transistor is greatly increased.

According to an aspect of the present disclosure, a driving circuit is provided for driving a light emitting diode. The driving circuit includes a driving transistor, a switching transistor and a capacitor. The driving transistor has a first source and a first drain, the first source receives a first direct current voltage, the first drain has a first voltage value, and the driving transistor is used for receiving the first voltage according to the first drain of the first drain. value to generate a drive current to drive the light emitting diode. The switching transistor is coupled to the first drain of the driving transistor and receives the first control signal. The capacitor is coupled to the switch transistor and receives the second control signal. Wherein, the switching transistor and the capacitor are used to adjust the first voltage value of the first drain according to the first control signal and the second control signal, so that the driving current reaches a saturation current value.

According to another aspect of the present disclosure, a driving circuit for driving light emitting diodes is provided. The driving circuit includes driving transistors, switching transistors, capacitors and post-stage transistors. The driving transistor has a first source and a first drain, the first source receives a first direct current voltage, the first drain has a first voltage value, and the driving transistor is used for receiving the first voltage according to the first drain of the first drain. value to generate a drive current to drive the LED. The switching transistor is coupled to the first drain of the driving transistor and receives the first control signal. The capacitor is coupled to the switching transistor and receives one of the first DC voltage, the second DC voltage and the first control signal. The latter transistor is coupled between the first drain of the driving transistor and the light-emitting diode, and receives the second control signal. The switching transistor and the capacitor are used to adjust the first voltage value of the first drain according to the first control signal and the second control signal, so that the driving current reaches a saturation current value.

According to the above technical solution of the present disclosure, the driving transistor of the driving circuit has a larger source-drain cross voltage. Accordingly, the driving current of the driving transistor can reach the saturation current value relatively quickly, and thus, the response speed of the radiation source of the light-emitting diode driven by the driving current can be greatly improved.

Other aspects and advantages of this disclosure can be seen by reading the following drawings, detailed description and claims.

100,300,400,500: drive circuit

150: Pre-stage circuit

M1: drive transistor

M2: switching transistor

M3: post-stage transistor

M4~M9: Transistor

M1_s, M2_s, M3_s: source

M1_d, M2_d, M3_d: drain

M1_g, M2_g, M3_g: gate

D1: light emitting diode

D1_a: Positive pole

D1_b: negative pole

C1, Cst: capacitance

C1_a: first end

C1_b: second terminal

D,P,A,T: nodes

V_ref1, Vref2, O_VDD: DC voltage

V_DATA, O_VSS: DC voltage

S1[N], S2[N], EM[N]: control signal

S1[N-1], S2[N-1], EM[N-1]: control signal

t1~t9: time point

R1: During the first reset

R2: Second reset period

W: data writing period

E: during driving radiation

Vsd: cross-voltage (source-drain cross-voltage)

V _H : high potential

V _L : low potential

Id: drive current

FIG. 1A is a circuit diagram of a driving circuit according to an embodiment of the present disclosure.

FIG. 1B is a schematic diagram of the operation of the driving circuit in FIG. 1A during the first reset period.

FIG. 1C is a schematic diagram of the operation of the driving circuit in FIG. 1A during the second reset period.

FIG. 1D is a schematic diagram of the operation of the driving circuit in FIG. 1A during data writing.

FIG. 1E is a schematic diagram of the operation of the driving circuit in FIG. 1A during the driving emission period.

Figure 2 is a timing diagram of each control signal of the drive circuit operating in different periods.

FIG. 3A is a circuit diagram of a driving circuit according to another embodiment of the present disclosure.

FIG. 3B is a schematic diagram of the operation of the driving circuit in FIG. 3A during the driving emission period.

FIG. 4 is a circuit diagram of a driving circuit according to another embodiment of the present disclosure.

FIG. 5 is a circuit diagram of a driving circuit according to yet another embodiment of the present disclosure.

The technical terms in this specification refer to the customary terms in this technical field. If some terms are explained or defined in this specification, the explanations or definitions of these terms shall prevail. Each embodiment of the disclosure has one or more technical features. On the premise of possible implementation, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

FIG. 1A is a circuit diagram of a driving circuit 100 according to an embodiment of the disclosure. Please refer to FIG. 1A. The driving circuit 100 includes a driving transistor M1, a switching transistor M2, a rear-stage transistor M3, a capacitor C1, a transistor M4 and a front transistor. stage circuit 150. The driving circuit 100 is used for driving the light emitting diode D1 to make the light emitting diode D1 emit light.

Wherein, the driving transistor M1 has a source (source) M1_s, a drain (drain) M1_d and a gate (gate) M1_g. The source M1_s is coupled to a DC voltage source (not shown in FIG. 1A ) to receive the DC voltage O_VDD. The drain M1_d is at the same potential as the node A, and the voltage value of the drain M1_d is equal to the voltage _VA of the node A; that is, the drain M1_d has a voltage value _VA . Moreover, the driving transistor M1 can generate a driving current Id to drive the light-emitting diode D1, and the magnitude of the driving current Id corresponds to the voltage value V _A of the drain M1_d; _A generates a driving current Id. The switching transistor M2 is coupled to the drain M1_d of the driving transistor M1, and the switching transistor M2 receives the control signal S2[N]. The capacitor C1 is coupled to the switch transistor M2, and the capacitor C1 receives the control signal EM[N]. Among them, the switching transistor M2 and the capacitor C1 can be used to adjust the voltage value V _A of the drain M1_d according to the control signal S2[N] and the control signal EM[N], so that the driving current Id provided by the driving transistor M1 reaches the saturation current value.

More specifically, the driving transistor M1 is a thin film transistor with a driving function, so the driving transistor M1 may be called "driving-TFT (DTFT)", which is, for example, a P-type metal oxide semiconductor (PMOS) transistor. The gate M1_g of the driving transistor M1 is coupled to the node P of the front-end circuit 150 .

The switching transistor M2 is a thin film transistor with switching function, so the switching transistor M2 may be called "switching-TFT (SWTFT)", which is, for example, an N-type metal oxide semiconductor (NMOS) transistor. The switching transistor M2 has a source M2_s, a drain M2_d and a gate M2_g. The drain M2_d of the switching transistor M2 is coupled to the drain M1_d of the driving transistor M1; The gate M2_g receives the control signal S2 , and the source M2_s is coupled to the first terminal C1_a of the capacitor C1 ; the node T is a coupling point between the source M2_s and the first terminal C1_a of the capacitor C1 .

The subsequent transistor M3 is, for example, a PMOS transistor, and the latter transistor M3 has a source M3_s, a drain M3_d, and a gate M3_g. The source M3_s of the subsequent transistor M3 is coupled to the drain M1_d of the driving transistor M1 and the node A. The gate M3_g is coupled to the second terminal C1_b of the capacitor C1, and the gate M3_g receives the control signal EM. The drain M3_d is coupled to the anode D1_a of the LED D1, and the cathode D1_b of the LED D1 receives the DC voltage O_VSS.

Transistor M4 is, for example, a PMOS transistor (for simplicity of the drawing, the symbols of the source, drain and gate of transistor M4 are not shown in FIG. 1A ). The gate of the transistor M4 receives the control signal S1, and the drain of the transistor M4 is coupled to the anode D1_a of the light emitting diode D1. The control signal S1, the control signal S2 and the control signal EM mentioned above are all signals of a gate driver on array (GOA).

On the other hand, the pre-stage circuit 150 includes transistors M5, M6, M7, M8, M9 and capacitors Cst (for the sake of simplicity in the drawing, the sources of transistors M5, M6, M7, M8, M9 are not shown in Figure 1A , the symbols of the drain and the gate, and the symbols of the first terminal and the second terminal of the capacitor Cst are not marked). The transistors M5 , M6 , M7 , M8 , and M9 are all PMOS transistors, for example. The gate of the transistor M8 receives the control signal EM, the source of the transistor M8 receives the DC voltage V_ref2, and the drain of the transistor M8 is connected to the source of the transistor M9. The junction of the transistor M8 and the transistor M9 is the node D. The drain of the transistor M9 receives the DC voltage V_DATA. The first end of the capacitor Cst is coupled to the drain of the transistor M8, the source of the transistor M9 and the node D, and the second end of the capacitor Cst is coupled to the source of the transistor M6 and the gate M1_g of the drive transistor M1 . The node P is where the second end of the capacitor Cst is coupled to the source of the transistor M6.

The drain of the transistor M6 is coupled to the source of the transistor M5, and the drain of the transistor M5 is coupled to the drain M1_d of the driving transistor M1. The gates of the transistors M5, M6 are coupled to the gate of the transistor M9, and the gates of the transistors M5, M6, M9 all receive the control signal S2. The source of the transistor M7 is coupled to the drain of the transistor M6 and the source of the transistor M5, the gate of the transistor M7 receives the control signal S1, and the drain of the transistor M7 receives the DC voltage V_ref1.

In addition, the gate M1_g of the driving transistor M1 is coupled to the node P of the previous stage circuit 150, and the drain M1_d of the driving transistor M1 and the drain M2_d of the switching transistor M2 are also coupled to the previous stage circuit 150; Node A is where the drain M1_d of the transistor M1 and the drain M2_d of the switching transistor M2 are coupled to the front-stage circuit 150 .

The above describes the circuit structure of the driving circuit 100 , and the following describes the operation of the driving circuit 100 in conjunction with FIGS. 1B-1E and FIG. 2 . Among them, FIG. 1B is a schematic diagram of the driving circuit 100 in FIG. 1A operating in the first reset period R1, and FIG. 2 shows the control signals S1[N], S2[N], EM of the driving circuit 100 operating in different periods. Timing diagrams of [N], S1[N-1], S2[N-1], EM[N-1] (hereinafter, Figure 2 can also be used to illustrate the driving circuits of Figures 3A, 4, and 5 operation). Please refer to FIG. 1B and FIG. 2 at the same time. When the driving circuit 100 operates in the first reset period R1, the driving circuit 100 resets the anode D1_a of the light-emitting diode D1 to reset and clear the previous The current remaining in the operation cycle (the previous operation cycle is denoted as “[N-1]”).

For each control signal S1[N-1], S2[N-1], EM[N-1] of the previous operation cycle [N-1], the control signal S1[N-1] is reset at the first The time point t1 at the beginning of the period R1 is reduced from a high potential to a low potential, and the control signal S1[N-1] is maintained at a low potential during the first reset period R1 until the time point t3 at the end of the first reset period R1 The control signal S1[N-1] is raised again from a low potential to a high potential; accordingly, the transistor M4 whose gate receives the control signal S1[N-1] is turned on (turned-on) during the first reset period R1 or conduction state. Moreover, the control signal S2[N−1] is lowered from a high potential to a low potential at a time point t2 within the first reset period R1. Furthermore, the control signal EM[N−1] maintains a high potential during the first reset period R1.

On the other hand, for each control signal S1[N], S2[N], EM[N] of the current operation cycle (the current operation cycle is expressed as “[N]”), the control signal S1[N] is at the first The high potential is maintained during the reset period R1; accordingly, the transistor M7 whose gate receives the control signal S1[N] is in a turned-off state during the first reset period R1. Moreover, the control signal S2[N] also maintains a high potential during the first reset period R1; accordingly, the transistors M5, M6, and M9 (which are PMOS transistors) whose gates receive the control signal S2[N] are During the first reset period R1 is in the off state, and the switching transistor M2 (which is an NMOS transistor) whose gate receives the control signal S2 [N] is in the open state during the first reset period R1 . Moreover, the control signal EM[N] is raised to a high potential at the time point t0 before the first reset period R1 and remains at a high potential during the first reset period R1, accordingly, the gate receives the control signal EM[ The transistor M8 of N] and the subsequent transistor M3 are turned off during the first reset period R1. Moreover, the voltage V _P of the node P is maintained at a low potential by the capacitor Cst, so the driving transistor M1 whose gate receives the voltage V _P is turned on.

From the above, during the first reset period R1, the voltage V _A of the node A of the driving circuit 100 is approximately equal to the sum of the DC voltage O_VSS and the forward bias voltage V_D1 of the light-emitting diode D1, and the voltage of the node T V _T is approximately equal to the voltage V _A of node A . The voltage V _A and V _T are shown in formula (1): V _A =V _T =O_VSS+V_D1 (1)

After the first reset period R1, the driving circuit 100 operates in a second reset period R2. FIG. 1C is a schematic diagram of the driving circuit 100 in FIG. 1A operating in the second reset period R2. Please refer to FIG. 1C and FIG. 2 at the same time. The drive circuit 100 controls the driving transistor M1 in the second reset period R2. The gate M1_g is reset and compensated. At time point t5 when the second reset period R2 starts, the control signal EM[N-1] of the previous operation period [N-1] is lowered from a high potential to a low potential, and the control signal EM[N-1] is at R2 maintains a low potential during the second reset period. Moreover, the control signal S1[N] of the current operation period [N] is lowered from a high potential to a low potential at time point t5, and the control signal S1[N] is maintained at a low potential in the second reset period R2 until the second At time point t7 when the reset period R2 ends, the control signal S1 [N] is raised to a high level again. Accordingly, the gate of the transistor M7 receiving the control signal S1 [N] is turned on during the second reset period R2 .

In addition, the control signal S2 [N] of the current operation period [N] is lowered from a high potential to a low potential at the time point t6 within the second reset period R2 . Accordingly, the gate The transistors M5, M6, M9 (which are PMOS transistors) receiving the control signal S2[N] are turned on at time t6, and the switching transistor M2 (which is an NMOS transistor) whose gate receives the control signal S2[N] Transistor) is switched to the off state at the time point t6.

Furthermore, the control signal EM[N] of the current operation period [N] maintains a high potential during the second reset period R2. Accordingly, the transistor M8 whose gate receives the control signal EM[N] and the downstream transistor M3 are turned off during the second reset period R2. Moreover, the control signal S1[N-1] of the previous operation period [N-1] is maintained at a high potential in the second reset period R2, therefore, the transistor M4 whose gate receives the control signal S1[N-1] During the second reset period R2 is in the OFF state. Moreover, the voltage V _P of the node P is maintained at a low potential by the capacitor Cst, so the driving transistor M1 whose gate receives the voltage V _P is turned on.

From above, during the second reset period R2, the voltage VA of the node A generally ranges from the DC voltage V_ref1 to the DC voltage O_VDD minus the threshold voltage Vth_1 of the driving transistor M1. The voltage VP at the node P is roughly equal to the voltage VA at the node A. Moreover, the voltage VT of the node T is equal to: the sum of the DC voltage O_VSS and the forward bias voltage V_D1 of the LED D1 . The respective voltages V _P , V _A , and V _T of nodes P, A, and T are shown in equations (2) and (3): V _P =V _A =(~V_ref1)to(O_VDD-Vth_1) (2)

V _T =O_VSS+V_D1 (3)

After the second reset period R2, the driving circuit 100 operates in the data writing period W. FIG. 1D shows that the driving circuit 100 of FIG. 1A operates in a resource For the schematic diagram of the data writing period W, please refer to Figure 1D and Figure 2 at the same time. At the time point t7 when the data writing period W starts, the control signal S1[N] is raised from low potential to high potential, and the control signal S1 The high potential of [N] is maintained throughout the data writing period W, and accordingly, the transistor M7 whose gate receives the control signal S1 [N] is turned off during the data writing period W.

Moreover, the control signal S2[N] is maintained at a low potential during the data writing period W, and accordingly, the transistors M5, M6, and M9 (which are PMOS transistors) whose gates receive the control signal S2[N] are turned on. , and the switching transistor M2 (NMOS transistor) whose gate receives the control signal S2[N] is turned off. At this time, the voltage V _P at the node P is roughly equal to the voltage V _A at the node A. The voltage V _P of the node P is approximately equal to: the DC voltage O_VDD minus the threshold voltage Vth_1 of the driving transistor M1 . . Moreover, the voltage V _T of the node T is approximately equal to the sum of the DC voltage O_VSS and the forward bias voltage V_D1 of the LED D1 . Furthermore, the voltage V _D of the node D is approximately equal to the DC voltage V_DATA. From the above, the respective voltages V _P , VA , V T , and V _D of the nodes P, _A , _T , and D are shown in equations (4) to (6): V _P =V _A =O_VDD-Vth_1 (4)

V _T =O_VSS+V_D1 (5)

V _D = V_DATA (6)

After the data writing period W, the driving circuit 100 is ready to operate in the driving emission period E. Referring to FIG. FIG. 1E is a schematic diagram of the driving circuit 100 in FIG. 1A operating in the driving emission period E. Please refer to FIG. 1E and FIG. 2 at the same time. As shown in the figure, the drive circuit 100 has not yet entered the driving radiation period E at the time point t8 when the data writing period W ends, and the control signal S2 [N] is raised from a low potential to a high potential at the time point t8. Accordingly, the gate receives the control signal S2 [N] transistors M5, M6, M9 (PMOS transistors) are turned off at time t8, and the switching transistor M2 (NMOS transistors) whose gate receives the control signal S2[N] is At the time point t8, it is switched to the on state. Moreover, at the time point t8, the control signal EM[N] is still at a high potential, so the gate of the transistor M8 receiving the control signal EM[N] and the downstream transistor M3 are still in the off state at the time point t8.

At time point t9, the driving circuit 100 enters the driving emission period E, and the driving circuit 100 drives the light emitting diode D1 so that the light emitting diode D1 emits light. At the time point t9, the control signal EM[N] is lowered from a high potential to a low potential. Accordingly, the gate of the transistor M8 receiving the control signal EM[N] and the downstream transistor M3 are turned on at the time point t9. Since the subsequent transistor M3 is turned on, the driving current Id generated by the driving transistor M1 can be supplied to the light-emitting diode D1 through the latter transistor M3.

Moreover, after the time point t9, since the transistor M8 is turned on, the voltage V _D of the node D is approximately equal to the DC voltage V_ref2 . In addition, since the driving transistor M1 is still on, the voltage V _P of the node P is approximately equal to the DC voltage O_VDD minus the threshold voltage Vth_1 of the driving transistor M1; and through the function of the capacitor Cst, the DC voltage V_ref2 and the DC voltage V_DATA The difference of adjusts the voltage V _P of the input node P.

Furthermore, the control signal EM[N] is applied to the second terminal C1_b of the capacitor C1. When the control signal EM[N] is lowered from a high potential to a low potential, a capacitive coupling effect occurs on the capacitor C1, so that the second terminal of the capacitor C1 A coupling voltage difference is generated between the terminal C1_b and the first terminal C1_a. For example, when the control signal EM[N] decreases from the high potential V _H to the low potential V _L (the high potential V _H is the voltage value of the high potential of the second terminal C1_b of the capacitor C1, and the low potential V _L is the voltage value of the capacitor C1 The voltage value of the low potential of the second terminal C1_b), the capacitive coupling effect of the capacitor C1 can cause a coupling voltage difference of "V _L -V _H " between the second terminal C1_b of the capacitor C1 and the first terminal C1_a. Accordingly, after the time point t9, the control signal EM[N] lowered to a low level can adjust the coupling voltage difference "V _L -V _H " to the voltage V _A of the node A through the capacitive coupling effect of the capacitor C1, The voltage V _A of the node A is reduced to the sum of the DC voltage O_VSS, the forward bias voltage V_D1 of the light-emitting diode D1 , and the coupling voltage difference "V _L -V _H ".

From the above, during the drive emission period E, the respective voltages V _D , VP , and VA of the nodes D, _P , and _A of the drive circuit 100, and the voltage between the source M1_s and the drain M1_d of the drive transistor M1 The cross voltage Vsd is shown in formula (7) ~ formula (10): V _D =V_ref2 (7)

V _P =O_VDD-Vth_1+(V_ref2-V_DATA) (8)

V _A =V _T =O_VSS+V_D1+(V _L -V _H) (9)

Vsd=O_VDD-V _A =O_VDD-O_VSS-V_D1-(V _L -V _H ) (10)

From the above, when the driving circuit 100 drives the light-emitting diode D1 during the driving emission period E, the voltage V _A of the node A can be lowered by the control signal EM[N] with a lower potential through the capacitor C1 and the switching transistor M2. To a lower voltage level (that is, reducing the voltage of the drain M1_d of the driving transistor M1 to a lower voltage level), the source-drain cross voltage Vsd of the driving transistor M1 is greatly increased, so The driving transistor M1 can quickly enter the saturation region, and the driving current Id can quickly reach the saturation current value. Accordingly, the response speed of the driving transistor M1 can be greatly improved, thereby increasing the response speed of the light source emitted by the light-emitting diode D1.

FIG. 3A is a circuit diagram of a driving circuit 300 according to another embodiment of the disclosure. The driving circuit 300 in FIG. 3A is similar to the driving circuit 100 in FIG. 1, the difference lies in that the capacitor C1 of the driving circuit 300 has a different coupling method . Please refer to FIG. 3A, the second terminal C1_b of the capacitor C1 of the drive circuit 300 is coupled to the source M2_s of the switching transistor M2, and the coupling point between the second terminal C1_b of the capacitor C1 and the source M2_s of the switching transistor M2 is Node T.

On the other hand, the first terminal C1_a of the capacitor C1 is coupled to the source M1_s of the driving transistor M1, and the first terminal C1_a of the capacitor C1 can receive the DC voltage O_VDD. The voltage V _T of the node T can be stably maintained at a substantially constant voltage value by the DC voltage O_VDD and the voltage stabilization effect of the capacitor C1; and, when the switching transistor M2 is turned on, the voltage V _A of the node A is substantially equal to The voltage V _T , thus the DC voltage O_VDD and the capacitor C1 can also indirectly stabilize the voltage _VA of the node A.

FIG. 3B is a schematic diagram of the driving circuit 300 in FIG. 3A operating during the driving emission period E. Please refer to FIG. 2 and FIG. 3B at the same time. After the time point t9, the control signal S2[N] and the control signal S1[N- 1], S1[N] maintains a high potential and the control signal EM[N] decreases to a low potential. Accordingly, the transistors M5, M6, and M9 (PMOS transistors) whose gate receives the control signal S2[N] are in the off state and the switching transistor M2 (NMOS transistor) is in the on state, and the gate receives the control signal The transistor M4 of the signal S1[N-1] is in the off state, and the transistor M7 whose gate receives the control signal S1[N] is in the off state. Moreover, the transistors M8 and M3 whose gates receive the control signal EM[N] are turned on.

Since the subsequent transistor M3 is in the on state, the voltage V _A of the E node A is approximately equal to the sum of the DC voltage O_VSS, the forward bias voltage V_D1 of the light-emitting diode D1 and the above two during the driving emission period. Moreover, when the switching transistor M2 is in the on state, the voltage _VA of the node A can be stably maintained at the above-mentioned voltage value through the voltage stabilizing effect of the capacitor C1. During the drive emission period E, the voltage V _A of node A is shown in formula (11): V _A =O_VSS+V_D1 (11)

Moreover, during the driving radiation period E, the source-drain cross voltage Vsd of the driving transistor M1 of the driving circuit 300 is shown in formula (12): Vsd=O_VDD-O_VSS-V_D1 (12)

Compared with the driving circuit 100 in FIG. 1A, the capacitor C1 of the driving circuit 300 does not receive the control signal EM[N] and the node T is not coupled to the control signal EM[N]. Therefore, the control signal EM[ When N] is lowered to a low potential, the coupling voltage difference "V _L -V _H " is not adjusted into the voltage V _A of the node A. Therefore, the source-drain voltage Vsd of the driving transistor M1 of the driving circuit 300 is slightly smaller than the source-drain voltage Vsd of the driving transistor M1 of the driving circuit 100 . However, the source-drain cross voltage Vsd of the driving transistor M1 of the driving circuit 300 is still greater than the source-drain cross voltage of the conventional driving transistor (ie, the critical voltage of the driving transistor), so the driving The speed at which the driving current Id of the driving transistor M1 of the circuit 300 reaches the saturation current value is still faster than that of conventional driving transistors.

FIG. 4 is a circuit diagram of a driving circuit 400 according to yet another embodiment of the present disclosure. The driving circuit 400 in FIG. 4 is similar to the driving circuit 300 in FIG. connected to another DC voltage V_ref3. Accordingly, the DC voltage V_ref3 and the capacitor C1 can be used to stabilize the voltage V _T of the node T; and when the switching transistor M2 is turned on, the DC voltage V_ref3 and the capacitor C1 can also indirectly affect the voltage V of the node A _A plays a stabilizing role.

In operation, during the emission period E of the drive circuit 400, the control signals S1[N-1], S1[N], and S2[N] are maintained at high potentials and the control signal EM[N] is reduced to low potentials, so the electric potential The crystal M4 is turned off and the downstream transistor M3 is turned on; accordingly, the voltage _VA of the node A is approximately equal to the sum of the DC voltage O_VSS, the forward bias voltage V_D1 of the light-emitting diode D1, and the above two. During the driving emission period E, the voltage V _A of the node A of the driving circuit 400 and the source-drain cross voltage Vsd of the driving transistor M1 are shown in formula (13) and formula (14): V _A =O_VSS+V_D1 (13)

Vsd=O_VDD-O_VSS-V_D1 (14)

FIG. 5 is a circuit diagram of a driving circuit 500 according to yet another embodiment of the present disclosure. The driving circuit 500 in FIG. 5 is similar to the driving circuit 400 in FIG. Not coupled to any DC voltage. In this embodiment, the first terminal C1_a of the capacitor C1 is coupled to the gate M2_g of the switching transistor M2, and the first terminal C1_a of the capacitor C1 can receive the control signal S2[N]. During the driving emission period E, the control signal S2 [N] is high to turn on the switching transistor M2 . The voltage V _T of the node T can be stably maintained by controlling the voltage value of the high potential of the signal S2[N] and the voltage stabilization function of the capacitor C1, and the voltage V _A of the node A is approximately equal to the voltage V _T of the node T ( Because the switching transistor M2 is in the on state); accordingly, the voltage V _A of the node A can be indirectly stabilized by the high potential control signal S2 [N] and the capacitor C1 .

During drive emission period E, the operation of the drive circuit 500 is similar to that of the drive circuit 400 of FIG. 4 . During the driving emission period E, the transistor M4 of the driving circuit 500 is in the off state and the subsequent transistor M3 is in the on state, so the voltage V _A of the node A is roughly equal to: the DC voltage O_VSS, the forward bias of the light emitting diode D1 Press V_D1, the sum of the above two. During the drive emission period E, the voltage V _A of the node A of the drive circuit 500 and the source-drain cross voltage Vsd of the drive transistor M1 are shown in formula (15) and formula (16): V _A =O_VSS+V_D1 (15)

Vsd=O_VDD-O_VSS-V_D1 (16)

As above, in the embodiment shown in Figures 3A, 4, and 5, the first terminal C1_a of the capacitor C1 of the driving circuit 300 receives the DC voltage O_VDD, and the first terminal C1_a of the capacitor C1 of the driving circuit 400 receives the DC voltage V_ref3, and drives The first terminal C1_a of the capacitor C1 of the circuit 500 receives the control signal S2 [N]. That is, for the driving circuits 300 , 400 , 500 , the first terminal C1_a of the capacitor C1 receives one of the DC voltage O_VDD, the DC voltage V_ref3 and the control signal S2 [N].

According to the circuit structures of the driving circuits 100, 300, 400, and 500 in the above different embodiments, an additional switching transistor M2 and a capacitor C1 are added to respond to the control signal S2[N], the control signal EM[N] and the DC voltage 0_VDD and adjust the voltage value V _A of the drain M1_d of the driving transistor M1 through the switching transistor M2 and the capacitor C1, so that the voltage value V _A of the drain M1_d of the driving transistor M1 has a lower voltage level to increase the driving voltage The source-drain voltage Vsd of the crystal M1. Moreover, the voltage value V _A of the drain M1_d of the driving transistor M1 can be stably maintained through the voltage stabilizing effect of the capacitor C1 . Accordingly, corresponding to the greatly increased source-drain voltage Vsd, the driving transistor M1 can quickly enter the saturation region, so that the driving current Id of the driving transistor M1 can reach the saturation current value quickly; thus, the driving The response time of the transistor M1 is greatly shortened, so that the response speed of the light source emitted by the light-emitting diode D1 is greatly improved.

Although the present invention has been disclosed above in detail with preferred embodiments and examples, it should be understood that these examples are meant to be illustrative rather than limiting. It is expected that those skilled in the art can think of various modifications and combinations, and the various modifications and combinations fall within the spirit of the present invention and the scope of the appended patent application.

100: drive circuit

150: Pre-stage circuit

M1: drive transistor

M2: switching transistor

M3: post-stage transistor

M4~M9: Transistor

M1_s, M2_s, M3_s: source

M1_d, M2_d, M3_d: drain

M1_g, M2_g, M3_g: gate

D1: light emitting diode

D1_a: Positive pole

D1_b: negative pole

C1, Cst: capacitance

C1_a: first end

C1_b: second terminal

D,P,A,T: nodes

V_ref1, Vref2, O_VDD: DC voltage

V_DATA, O_VSS: DC voltage

Id: drive current

Vsd: cross-voltage (source-drain cross-voltage)

S1[N], S2[N], EM[N], S1[N-1]: control signal

Claims (16)

A driving circuit for driving a light-emitting diode, the driving circuit includes: a driving transistor with a first source and a first drain, the first source receives a first DC voltage, the first A drain has a first voltage value, and the driving transistor is used to generate a driving current to drive the light-emitting diode according to the first voltage value of the first drain; a switching transistor is coupled to the driving the first drain of the transistor and receiving a first control signal; and a capacitor coupled to the switching transistor and receiving a second control signal, wherein the switching transistor and the capacitor are used according to The first control signal and the second control signal adjust the first voltage value of the first drain, so that the driving current reaches a saturation current value. The drive circuit as described in claim 1, wherein a first end of the capacitor is coupled to a second source of the switching transistor, a second end of the capacitor receives the second control signal, and when the second When the control signal is switched from high potential to low potential, the capacitor has a capacitive coupling effect to generate a coupling voltage difference between the second terminal and the first terminal of the capacitor. The drive circuit as described in claim 2 further includes: a subsequent stage transistor, the latter stage transistor is coupled to the first drain of the drive transistor between the electrode and one positive electrode of the light-emitting diode; wherein, the subsequent transistor receives the second control signal, and the latter transistor is turned on when the second control signal is at a low potential. The drive circuit as described in claim 3, wherein one negative pole of the light emitting diode is coupled to a second DC voltage, and when the second control signal is at a low potential, the positive pole of the light emitting diode and the negative pole are connected There is a forward bias between them. The driving circuit as described in claim 4, wherein a second drain of the switching transistor is coupled to the first drain of the driving transistor, and a second gate of the switching transistor receives the first control signal, when the first control signal is at a high potential, the switch transistor is turned on, and the first voltage value of the first drain of the driving transistor is approximately equal to the voltage of the first terminal of the capacitor. The driving circuit as described in claim 5, wherein when the first control signal is at a high potential and the second control signal is at a low potential, the first voltage value of the first drain of the driving transistor is approximately equal to : the sum of the second DC voltage, the forward bias voltage of the light-emitting diode and the coupling voltage difference caused by the coupling effect of the capacitor. The driving circuit as described in claim 6, wherein when the driving circuit operates in a driving emission period, the first control signal is at a high potential and the second control signal The control signal is a low potential, and the driving current of the driving transistor passes through the subsequent transistor to drive the light-emitting diode. The driving circuit according to claim 1, wherein the driving transistor further has a first gate, and the first gate and the first drain are coupled to a previous stage circuit. A driving circuit for driving a light-emitting diode, the driving circuit includes: a driving transistor with a first source and a first drain, the first source receives a first DC voltage, the first A drain has a first voltage value, and the driving transistor is used to generate a driving current to drive the light-emitting diode according to the first voltage value of the first drain; a switching transistor is coupled to the the first drain of the driving transistor and receive a first control signal; and a capacitor coupled to the switching transistor and receive the first DC voltage, a second DC voltage and the first control signal One of them, wherein, the switching transistor and the capacitor are used to adjust the first voltage value of the first drain according to the first control signal and/or the second DC voltage, so that the driving current reaches a saturation current value. The drive circuit as described in claim 9, wherein one of the capacitors The first terminal receives one of the first DC voltage, the second DC voltage and the first control signal, and a second terminal of the capacitor is coupled to a second source of the switching transistor. The driving circuit as described in claim 10, further comprising: a subsequent transistor coupled between the first drain of the driving transistor and an anode of the light-emitting diode; wherein , the subsequent transistor receives a second control signal, and when the second control signal is at a low potential, the latter transistor is turned on. The driving circuit as described in claim 11, wherein one negative pole of the light emitting diode is coupled to a third DC voltage, and when the second control signal is at a low potential, the positive pole of the light emitting diode and the negative pole are connected There is a forward bias between them. The driving circuit as described in claim 12, wherein a second drain of the switching transistor is coupled to the first drain of the driving transistor, and a second gate of the switching transistor receives the first control signal, when the first control signal is at a high potential, the switch transistor is turned on, and the first voltage value of the first drain of the driving transistor is approximately equal to the voltage of the second terminal of the capacitor. The drive circuit according to claim 13, wherein when the first control signal is at a high potential and the second control signal is at a low potential, the drive transistor The first voltage value of the first drain is approximately equal to: the sum of the third DC voltage and the forward bias voltage of the light emitting diode. The driving circuit as described in claim 14, wherein when the driving circuit operates in a driving emission period, the first control signal is at a high potential and the second control signal is at a low potential, and the driving current of the driving transistor The light-emitting diode is driven by the subsequent transistor. The driving circuit according to claim 9, wherein the driving transistor further has a first gate, and the first gate and the first drain are coupled to a previous stage circuit.

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