TWI832369B - Semiconductor device - Google Patents

Abstract

The present disclosure provides a semiconductor device including a substrate having a first conductive type, first and second isolation structures, an emitter semiconductor layer, a base semiconductor layer, an emitter spacer, and a dielectric layer. The substrate includes a deep well, a collector well, and first and second doped regions, which have a second conductive type. The collector well and the second doped region are disposed in the deep well. The first doped region is disposed in the collector well. The first isolation structure is disposed in the substrate to define the deep well. The second isolation structure is disposed in the deep well to define the first and second doped regions with the first isolation structure. The emitter semiconductor layer is disposed on the first doped region. The base semiconductor layer is disposed on the first doped region and surrounds the emitter semiconductor layer. The emitter spacer is disposed on the substrate and between the emitter semiconductor layer and the base semiconductor layer. The dielectric layer is disposed on the emitter semiconductor layer, the base semiconductor layer, and the emitter spacer and includes an extension portion extending between the emitter semiconductor layer and the base semiconductor layer.

Description

Semiconductor device

The present invention relates to a semiconductor device, and in particular to a semiconductor device for a heterojunction bipolar transistor (HBT).

The heterojunction bipolar transistor uses different semiconductor materials to form the emitter layer and the base layer, and forms a heterojunction at the interface between the emitter layer and the base layer. In heterojunction bipolar transistors, because SiGe has a lower energy gap, the collector current of SiGe heterojunction bipolar transistors will be higher than that of homojunction bipolar transistors under the same emitter base bias. The crystal has a high collector current and a high carrier mobility rate, and therefore has a higher cutoff frequency than traditional bipolar transistors. However, as the performance requirements of electronic components continue to increase, researchers in the field continue to improve the performance of heterojunction bipolar transistors.

The present invention provides a semiconductor device, which uses a retracted emitter spacer design to allow a dielectric layer to extend between the emitter semiconductor layer and the base semiconductor layer. The extended portion can improve the reliability and performance of the semiconductor device.

An embodiment of the present invention provides a semiconductor device, which includes a substrate with a first conductivity type, a first isolation structure, a second isolation structure, an emitter semiconductor layer, a base semiconductor layer, an emitter spacer, and a dielectric layer. The substrate includes a deep well region with a second conductivity type, a collector well region, a first doped region and a second doped region. The collector well region and the second doped region are disposed in the deep well region. The first doped region is disposed in the collector well region. A first isolation structure is disposed in the substrate to define a deep well region. The second isolation structure is disposed in the deep well region of the substrate to define the collector well region and the second doping region with the first isolation structure. The emitter semiconductor layer is disposed on the collector well region. The base semiconductor layer is disposed on the collector well region and surrounds the emitter semiconductor layer. The emitter spacer is disposed on the substrate and between the base semiconductor layer and the emitter semiconductor layer. The dielectric layer is disposed on the emitter semiconductor layer, the base semiconductor layer and the emitter spacer and includes an extension portion extending between the emitter semiconductor layer and the base semiconductor layer.

In some embodiments, the extended portion of the dielectric layer is in direct contact with the emitter semiconductor layer.

In some embodiments, the emitter semiconductor layer includes a first portion surrounded by the emitter spacer and a second portion on the first portion. The second portion extends in a direction horizontal to the substrate to be disposed over the emitter spacer and the base semiconductor layer. The second portion of the emitter semiconductor layer is in direct contact with the extended portion of the dielectric layer.

In some embodiments, the interface where the emitter spacer and the dielectric layer contact each other is positioned beneath the second portion of the emitter semiconductor layer.

In some embodiments, the interface is formed from a side of the second portion of the emitter semiconductor layer The wall is offset horizontally by a non-zero distance.

In some embodiments, the semiconductor device further includes a first metal silicide layer and a second metal silicide layer. The first metal silicide layer is disposed on the second portion of the emitter semiconductor layer and between the dielectric layer and the second portion of the emitter semiconductor layer. The second metal silicide layer is disposed between the base semiconductor layer and the dielectric layer. The second metal silicide layer extends under the second portion of the emitter semiconductor layer.

In some embodiments, the extended portion of the dielectric layer is disposed between a portion of the second metal silicide layer that extends below the second portion of the emitter semiconductor layer and the second portion of the emitter semiconductor layer.

In some embodiments, the first metal silicide layer is separated from the second metal silicide layer by an extension of the dielectric layer.

In some embodiments, the interface where the emitter spacer and the dielectric layer contact each other does not cut sidewalls of the second portion of the emitter semiconductor layer.

In some embodiments, the semiconductor device further includes a base layer disposed on the collector well region, the first isolation structure, and the second isolation structure. The base layer is located between the substrate and the emitter semiconductor layer and the base semiconductor layer.

Based on the above, in the above semiconductor device, the dielectric layer includes an extension portion extending between the emitter semiconductor layer and the base semiconductor layer through the design of the retracted emitter spacer, which can improve the reliability of the semiconductor device. performance and improve its performance.

10:Semiconductor device

100:Base

102:Sham Tseng District

104:Jijijing area

106: First doped region

108: Second doping region

110: First isolation structure

110a:Shallow trench isolation structure

110b: Deep Trench Isolation Structure

112: Second isolation structure

120: Base layer

130: Base semiconductor layer

140: Emitter semiconductor layer

150: Emitter spacer

152: First insulation layer

154: Second insulation layer

160: Silicone layer

162, 164, 166: Metal silicide layer

170, 180: Dielectric layer

190: Conductive contacts

192:Base contact

194:Emitter contact

196: Collector contact

A:Region

d: distance

Rb_ext1, Rb_ext2, Rb_ext3, Rb_intrinsic: resistance

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an enlarged schematic diagram of area A in FIG. 1 .

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention may also be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers indicate the same or similar components, and will not be repeated one by one in the following paragraphs.

It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. When an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connection" may refer to a physical and/or electrical connection, and "electrical connection" or "coupling" may refer to the presence of other components between two components. "Electrical connection" as used herein may include physical connections (such as wired connections) and physical disconnections (such as wireless connections).

As used herein, "about," "approximately" or "substantially" includes the recited value and the average within an acceptable range of deviations from the specific value that a person with ordinary skill in the art can determine, taking into account the Discuss the specific quantities of measurements and errors associated with the measurements (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the terms “approximately”, “approximately” or “substantially” used in this article may be based on optical properties, etching properties or other properties to select a more acceptable deviation range or standard deviation, rather than having one standard deviation apply to all properties.

The terminology used herein is used only to describe illustrative embodiments and does not limit the disclosure. In such cases, the singular form includes the plural form unless the context dictates otherwise.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is an enlarged schematic diagram of area A in FIG. 1 .

Referring to FIG. 1 , the semiconductor device 10 includes a substrate 100 , a first isolation structure 110 , a second isolation structure 112 , a base semiconductor layer 130 , an emitter semiconductor layer 140 , an emitter spacer 150 and a dielectric layer 170 .

Referring to FIG. 1 , the substrate 100 has a first conductivity type and includes a deep well region 102 of a second conductivity type, a collector well region 104 , a first doped region 106 and a second doped region 108 . The collector well region 104 and the second doped region 108 are disposed in the deep well region 102 . The first doped region 106 is disposed in the collector well region 104 . The first conductive type may be P-type, and the second conductive type may be N-type, but is not limited thereto. In other embodiments, the first conductivity type may be N-type, and the second conductivity type may be P-type. The substrate 100 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include element semiconductors (eg, Si, Ge), alloy semiconductors (eg, SiGe), or compound semiconductors (eg, III-V semiconductors, etc.). The semiconductor material may be doped with a dopant of the first conductivity type so that the substrate 100 has the first conductivity type.

In some embodiments, the first doped region 106 and the second doped region 108 may be heavily doped regions, and their doping concentration may be higher than that of the deep well region 102 and the collector well region 104 . doping concentration. When the semiconductor device 10 is an HBT, the first doping region 106 can adjust the profile of the depletion region between the collector and the base of the HBT. In some embodiments, the first doped region 106 may be a selective implanted collector (SIC). When the semiconductor device 10 is an HBT, the second doped region 108 and the deep well region 102 may jointly serve as a contact region for a collector contact (eg, the collector contact 196 ) of the HBT.

The first isolation structure 110 is disposed in the substrate 100 to define the deep well region 102 . In some embodiments, the first isolation structure 110 may include a shallow trench isolation structure 110a and a deep trench isolation structure 110b. The shallow trench isolation structure 110a may extend from the surface of the substrate 100 into the substrate 100. That is to say, the top surface of the shallow trench isolation structure 110a may be coplanar with the surface of the substrate 100, but is not limited thereto. The deep trench isolation structure 110b may extend from the bottom surface (eg, the surface opposite to the top surface) of the shallow trench isolation structure 110a into the substrate 100 . The shallow trench isolation structure 110a and the deep trench isolation structure 110b may each include one or more dielectric materials. The dielectric material may include oxides (such as silicon oxide), tetraethyl orthosilicate (TEOS), nitrides (such as silicon nitride, silicon oxynitride, etc.), carbides (such as silicon carbide, carbon silicon oxide, etc.) or similar.

The second isolation structure 112 is disposed in the deep well region 102 of the substrate 100 to define the collector well region 104 and the second doping region 108 with the first isolation structure 110 . In some embodiments, the shallow trench isolation structure 110a and the second isolation structure 112 in the first isolation structure 110 define the collector well region 104 and the second doped region 108. In some embodiments, the second isolation structure 112 may be a shallow trench isolation structure extending from the surface of the substrate 100 into the substrate 100 . The second isolation structure 112 may include one or more dielectric materials. The dielectric material may include oxides (such as silicon oxide), tetraethyl orthosilicate (tetraethyl orthosilicate; TEOS), nitrides (such as silicon nitride, silicon oxynitride, etc.), carbides (such as silicon carbide, silicon oxycarbide, etc.) or the like.

In some embodiments, the semiconductor device 10 may further include a base layer 120 disposed on the collector well region 104 , the first isolation structure 110 and the second isolation structure 112 . In some embodiments, the base layer 120 may have a first conductivity type, and when the semiconductor device 10 is an HBT, the base layer 120 may serve as the base of the HBT. In some embodiments, the material of base layer 120 includes SiGe. In some embodiments, the base layer 120 is located between the substrate 100 and the base semiconductor layer 130 and the emitter semiconductor layer 140 that will be described later.

The base semiconductor layer 130 and the emitter semiconductor layer 140 are disposed on the base layer 120 , and the base semiconductor layer 130 surrounds the emitter semiconductor layer 140 .

In some embodiments, the base semiconductor layer 130 may be disposed over the first isolation structure 110 and the second isolation structure 112 and overlap with the first portion of the collector well region 104 in a direction perpendicular to the substrate 100 . In some embodiments, the base semiconductor layer 130 may have a first conductivity type. For example, the base semiconductor layer 130 may include polycrystalline silicon doped with P-type dopants. In some embodiments, the base semiconductor layer 130 may have a doping concentration higher than that of the base of the HBT (ie, the base layer 120 ) and may serve as a contact to the base (ie, the base layer 120 ). layer.

In some embodiments, the emitter semiconductor layer 140 may be disposed on the base layer 120 on the collector well region 104 and overlap with the second portion of the collector well region 104 in a direction perpendicular to the substrate 100 . The second portion of the collector well region 104 is further away from the first isolation structure 110 and the second isolation structure 112 than the first portion of the collector well region 104 . In some practical In an embodiment, the first doped region 106 is located in the second portion of the collector well region 104 . In some embodiments, the emitter semiconductor layer 140 may have a second conductivity type. For example, the emitter semiconductor layer 140 may include polycrystalline silicon doped with N-type dopants. In some embodiments, when the semiconductor device 10 is an HBT, the emitter semiconductor layer 140 may serve as the emitter of the HBT. The material of the emitter semiconductor layer 140 may be different from the material of the base layer 120, so that a heterojunction is formed between the emitter and the base of the HBT. For example, the material of the emitter semiconductor layer 140 may include polycrystalline silicon, and the material of the base layer 120 may include SiGe.

In some embodiments, the emitter semiconductor layer 140 may include a first portion and a second portion. The first portion of the emitter semiconductor layer 140 may be surrounded by an emitter spacer 150 to be described later. The second portion of the emitter semiconductor layer 140 may be disposed on the first portion, and the second portion of the emitter semiconductor layer 140 extends in a direction horizontal to the substrate 100 to be disposed on the emitter spacer 150 and the base semiconductor layer 130 .

The emitter spacer 150 is provided on the substrate 100 and between the base semiconductor layer 130 and the emitter semiconductor layer 140 . The emitter spacer 150 can electrically isolate the base semiconductor layer 130 and the emitter semiconductor layer 140 from each other. The emitter spacer 150 may include an insulating material such as silicon nitride. In some embodiments, emitter spacer 150 may include first insulating layer 152 and second insulating layer 154. The first insulating layer 152 may be located under the second portion of the emitter semiconductor layer 140 and surround the first portion of the emitter semiconductor layer 140 . The second insulating layer 154 may be disposed on the base semiconductor layer 130 and extends from the first insulating layer 152 in a direction horizontal to the substrate 100 . In some embodiments, the first insulating layer 152 and the second insulating layer 154 can be formed simultaneously in the same process, so the first insulating layer 152 There is no interface where different materials contact each other and the second insulating layer 154 .

From a top view, the sidewall of the second insulating layer 154 that contacts the dielectric layer 170 to be described later is below the second portion of the emitter semiconductor layer 140 but does not exceed the sidewall thereof. For example, the interface where the second insulating layer 154 and the dielectric layer 170 contact each other may be positioned under the second portion of the emitter semiconductor layer 140 , or the interface where the second insulating layer 154 and the dielectric layer 170 contact each other is not cut. The sidewalls of the second portion of the emitter semiconductor layer 140 . As such, the dielectric layer 170 that will be described later may include an extension portion that extends below the second portion of the emitter semiconductor layer 140 and is between the emitter semiconductor layer 140 and the base semiconductor layer 130 to avoid that will be described later. The metal silicide layer 164 and the metal silicide layer 166 are electrically connected together, causing the emitter semiconductor layer 140 and the base semiconductor layer 130 to be electrically connected to each other, resulting in a short circuit problem. In addition, the metal silicide layer 164 to be described later may further extend below the second portion of the emitter semiconductor layer 140 to reduce the base resistance of the HBT. For example, please refer to Figure 2. The base resistance of HBT can be divided into external resistance (such as the sum of resistance Rb_ext1, resistance Rb_ext2 and resistance Rb_ext3) and intrinsic resistance (such as resistance Rb_intrinsic). In the case where the metal silicide layer 164 further extends under the second portion of the emitter semiconductor layer 140 , the external resistance in the base resistor (eg, the reduced resistance Rb_ext2) can be further reduced, so that the HBT has good performance.

Silicide layer 160 may include metal silicide layers 162, 164, 166. The metal silicide layer 162 may be disposed on the second doped region 108 . The metal silicide layer 164 may be disposed on the base semiconductor layer 130 and extend to the second portion of the emitter semiconductor layer 140 points below. In some embodiments, the metal silicide layer 164 may include a portion overlapping the emitter semiconductor layer 140 in a direction perpendicular to the substrate 100 . In some embodiments, the metal silicide layer 164 is not formed under the second insulating layer 154 . The metal silicide layer 166 may be disposed on the second portion of the emitter semiconductor layer 140 and spaced apart from the metal silicide layer 164 . In some embodiments, metal silicide layer 164 may be separated from metal silicide layer 166 by an extension of dielectric layer 170 . In some embodiments, metal silicide layer 164 and metal silicide layer 166 are electrically isolated from each other. Materials of the metal silicide layer 164 and the metal silicide layer 166 may include CoSi, TiSi, NiSi, the like, or combinations thereof.

The dielectric layer 170 is provided on the base semiconductor layer 130 , the emitter semiconductor layer 140 and the emitter spacer 150 and includes an extension portion extending between the emitter semiconductor layer 140 and the base semiconductor layer 130 . In some embodiments, the second insulating layer 154 of the emitter spacer 150 can be designed to be retracted inwardly from the sidewall of the second portion of the emitter semiconductor layer 140 by a non-zero distance (for example, as shown in FIG. 2 distance d), for example, the interface where the second insulating layer 154 and the dielectric layer 170 contact each other is horizontally offset from the sidewall of the second portion of the emitter semiconductor layer 140 by a non-zero distance (for example, the distance d shown in FIG. 2 ), This allows the dielectric layer 170 to include an extension extending between the emitter semiconductor layer 140 and the base semiconductor layer 130 and the metal silicide layer 164 to include an extension below the second portion of the emitter semiconductor layer 140 part. On the one hand, the above design can avoid the short circuit problem caused by the electrical connection between the metal silicide layer 164 and the metal silicide layer 166 and the electrical connection between the base semiconductor layer 130 and the emitter semiconductor layer 140 to improve the semiconductor device. 10 reliability. on the other hand, The above design can extend the length of the metal silicide layer 164 to further reduce the external resistance in the base resistor (for example, reduce the resistance Rb_ext2), so that the HBT has good performance. In some embodiments, the material of dielectric layer 170 may include silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof.

In some embodiments, the extended portion of dielectric layer 170 may be in direct contact with emitter semiconductor layer 140 . For example, the extended portion of dielectric layer 170 may be in direct contact with the second portion of emitter semiconductor layer 140 but not with the first portion of emitter semiconductor layer 140 . In some embodiments, the metal silicide layer 164 may be disposed between the base semiconductor layer 130 and the dielectric layer 170 . In some embodiments, the metal silicide layer 166 may be disposed between the second portion of the emitter semiconductor layer 140 and the dielectric layer 170 . In some embodiments, the extended portion of the dielectric layer 170 may be disposed between the extended portion of the metal silicide layer 164 that extends below the second portion of the emitter semiconductor layer 140 and the second portion of the emitter semiconductor layer 140 .

Dielectric layer 180 may be disposed on dielectric layer 170. Dielectric layer 180 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarb, silicon boron nitride, silicon boron nitride, silicon oxynitride, or a low-k material (having Materials with a dielectric constant that is the same as or lower than that of silicon oxide). Low-k materials may include, for example, flowable oxide (FOX), tonen silazene (TOSZ), undoped silicate glass (USG), borosilicate glass ;BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetra ethyl ortho silicate; PETEOS), fluoride silicate glass (FSG), carbon-doped silicon oxide (CDO), xerogel, aerogel, fluorinated amorphous carbon, organosilicon At least one of, but not limited to, glass (organo silicate glass; OSG), parylene, bis-benzocyclobutene (BCB), SiLK, polyimide, porous polymeric materials or combinations thereof this. In some embodiments, the material of dielectric layer 180 may be different from the material of dielectric layer 170 .

Conductive contacts 190 may be disposed in dielectric layer 180 and include base contact 192 , emitter contact 194 , and collector contact 196 . The base contact 192 , the emitter contact 194 and the collector contact 196 are electrically connected to the base semiconductor layer 130 , the emitter semiconductor layer 140 and the second doped region 108 respectively. In some embodiments, base contact 192, emitter contact 194, and collector contact 196 may be formed simultaneously in the same process. Base contact 192 , emitter contact 194 , and collector contact 196 may include conductive materials such as copper, tungsten, ruthenium, aluminum, and/or the like.

To sum up, in the semiconductor device in the above embodiments, the dielectric layer includes an extending portion extending between the emitter semiconductor layer and the base semiconductor layer through the design of the retracted emitter spacer, so that It can improve the reliability and performance of semiconductor devices.

10:Semiconductor device

100:Base

102:Sham Tseng District

104:Jijijing area

106: First doped region

108: Second doping region

110: First isolation structure

110a:Shallow trench isolation structure

110b: Deep Trench Isolation Structure

112: Second isolation structure

120: Base layer

130: Base semiconductor layer

140: Emitter semiconductor layer

150: Emitter spacer

152: First insulation layer

154: Second insulation layer

160: Silicone layer

162, 164, 166: Metal silicide layer

170, 180: Dielectric layer

190: Conductive contacts

192:Base contact

194:Emitter contact

196: Collector contact

A:Region

Claims (10)

A semiconductor device including: A substrate having a first conductivity type and including a deep well region, a collector well region, a first doping region and a second doping region having a second conductivity type, wherein the collector well region and the second doping region Disposed in the deep well region, the first doping region is disposed in the collector well region, and the first conductivity type is different from the second conductivity type; a first isolation structure disposed in the substrate to define the deep well region; a second isolation structure disposed in the deep well region of the substrate to define the collector well region and the second doping region with the first isolation structure; An emitter semiconductor layer is provided on the collector well region; a base semiconductor layer disposed on the collector well region and surrounding the emitter semiconductor layer; an emitter spacer disposed on the substrate and between the base semiconductor layer and the emitter semiconductor layer; and A dielectric layer is provided on the emitter semiconductor layer, the base semiconductor layer and the emitter spacer and includes an extension portion extending between the emitter semiconductor layer and the base semiconductor layer. The semiconductor device of claim 1, wherein the extended portion of the dielectric layer is in direct contact with the emitter semiconductor layer. The semiconductor device according to claim 1, wherein the emitter semiconductor layer includes: a first portion surrounded by said emitter spacer; and a second portion, on the first portion, extending in a direction horizontal to the substrate to be disposed above the emitter spacer and the base semiconductor layer, wherein the second portion of the emitter semiconductor layer is in direct contact with the extended portion of the dielectric layer. The semiconductor device of claim 3, wherein an interface where the emitter spacer and the dielectric layer contact each other is positioned below the second portion of the emitter semiconductor layer. The semiconductor device of claim 4, wherein the interface is horizontally offset from a sidewall of the second portion of the emitter semiconductor layer by a non-zero distance. The semiconductor device as claimed in claim 3 further includes: A first metal silicide layer disposed on the second portion of the emitter semiconductor layer and between the dielectric layer and the second portion of the emitter semiconductor layer; and A second metal silicide layer is provided between the base semiconductor layer and the dielectric layer, The second metal silicide layer extends below the second portion of the emitter semiconductor layer. The semiconductor device of claim 6, wherein the extended portion of the dielectric layer is disposed between a portion of the second metal silicide layer extending below the second portion of the emitter semiconductor layer and between the second portion of the emitter semiconductor layer. The semiconductor device of claim 6, wherein the first metal silicide layer is spaced apart from the second metal silicide layer by the extended portion of the dielectric layer. The semiconductor device of claim 3, wherein an interface where the emitter spacer and the dielectric layer contact each other is not flush with the sidewall of the second portion of the emitter semiconductor layer. The semiconductor device as claimed in claim 1 further includes: A base layer is provided on the collector well region, the first isolation structure and the second isolation structure, and the base layer is located between the base, the emitter semiconductor layer and the base between semiconductor layers.

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