TWI828600B - Manufacturing method of semiconductor device structure - Google Patents

Abstract

A manufacturing method of a semiconductor device structure including the following steps is provided. A first dielectric layer is formed on a substrate. A P-type semiconductor layer and an N-type semiconductor layer connected to each other are formed on the first dielectric layer. A second dielectric layer is formed on the P-type semiconductor layer and the N-type semiconductor layer. A first opening and a second opening are formed in the second dielectric layer. A first metal layer is formed in the first opening, and a second metal layer is formed in the second opening. The first metal layer is electrically connected to the P-type semiconductor layer. The second metal layer is electrically connected to the N-type semiconductor layer. The substrate is placed in an electrolyte, wherein the electrolyte covers the second dielectric layer, the first metal layer, and the second metal layer. A light treatment is performed on the P-type semiconductor layer and the N-type semiconductor layer to perform a oxidation reaction and a reduction reaction in the electrolyte.

Description

Manufacturing method of semiconductor element structure

The present invention relates to a method for manufacturing a semiconductor structure, and in particular, to a method for manufacturing a semiconductor element structure that can be integrated with other processes.

In the current manufacturing process of semiconductor structures, different semiconductor elements and/or semiconductor components often need to be manufactured using different processes. However, in this case, the required process time is longer and the process complexity is higher. Therefore, how to integrate different processes has become the goal of continuous efforts.

The present invention provides a semiconductor device structure that can integrate the manufacturing process of the semiconductor device with other manufacturing processes.

The invention provides a method for manufacturing a semiconductor element structure, which includes the following steps. A first dielectric layer is formed on the substrate. A P-type semiconductor layer and an N-type semiconductor layer connected to each other are formed on the first dielectric layer. A second dielectric layer is formed on the P-type semiconductor layer and the N-type semiconductor layer. A first opening and a second opening are formed in the second dielectric layer. The first opening exposes the P-type semiconductor layer. The second opening exposes the N-type semiconductor layer. A first metal layer is formed in the first opening, and a second metal layer is formed in the second opening. The first metal layer is electrically connected to the P-type semiconductor layer. The second metal layer is electrically connected to the N-type semiconductor layer. The substrate is placed in the electrolyte, where the electrolyte covers the second dielectric layer, the first metal layer and the second metal layer. The P-type semiconductor layer and the N-type semiconductor layer are illuminated to perform an oxidation reaction and a reduction reaction in the electrolyte, wherein part of the first metal layer in the first opening is removed through the oxidation reaction to form a void. , and increase the amount of the second metal layer through the reduction reaction. Remove the substrate from the electrolyte. A first barrier layer and a conductive layer are formed in the gap. The first barrier layer is between the conductive layer and the first metal layer.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the semiconductor device structure, the P-type semiconductor layer and the N-type semiconductor layer may be integrally formed.

According to an embodiment of the present invention, the method for manufacturing the semiconductor device structure may further include the following steps. A second barrier layer is formed between the first metal layer and the second dielectric layer and between the first metal layer and the P-type semiconductor layer, and between the second metal layer and the second dielectric layer and the second metal layer A third barrier layer is formed between the N-type semiconductor layer and the N-type semiconductor layer.

According to an embodiment of the present invention, the method for manufacturing the semiconductor device structure may further include the following steps. Before forming the first barrier layer and the conductive layer, the second metal layer located outside the second opening is removed. A third dielectric layer is formed on the second metal layer, the conductive layer and the first barrier layer. A first interconnect structure and a second interconnect structure are formed in the third dielectric layer. The first interconnect structure is electrically connected to the conductive layer, and the second interconnect structure is electrically connected to the second metal layer.

The present invention proposes another method for manufacturing a semiconductor element structure, which includes the following steps. A first dielectric layer is formed on the substrate. A P-type semiconductor layer and an N-type semiconductor layer connected to each other are formed on the first dielectric layer. A second dielectric layer is formed on the P-type semiconductor layer and the N-type semiconductor layer. A first opening and a second opening are formed in the second dielectric layer. The first opening exposes the P-type semiconductor layer. The second opening exposes the N-type semiconductor layer. A first metal layer is formed in the first opening, and a second metal layer is formed in the second opening. The first metal layer is electrically connected to the P-type semiconductor layer. The second metal layer is electrically connected to the N-type semiconductor layer. The substrate is placed in the electrolyte, where the electrolyte covers the second dielectric layer, the first metal layer and the second metal layer. The P-type semiconductor layer and the N-type semiconductor layer are illuminated to perform an oxidation reaction and a reduction reaction in the electrolyte, wherein at least part of the first metal layer in the first opening is removed by the oxidation reaction to form a void, and The amount of the second metal layer is increased through a reduction reaction. Remove the substrate from the electrolyte. A capacitor is formed in the gap.

According to another embodiment of the present invention, in the above method for manufacturing a semiconductor device structure, the P-type semiconductor layer and the N-type semiconductor layer may be integrally formed.

According to another embodiment of the present invention, the method for manufacturing the semiconductor device structure may further include the following steps. A first barrier layer is formed between the first metal layer and the second dielectric layer and between the first metal layer and the P-type semiconductor layer, and between the second metal layer and the second dielectric layer and the second metal layer A second barrier layer is formed between the N-type semiconductor layer and the N-type semiconductor layer.

According to another embodiment of the present invention, in the above method for manufacturing a semiconductor device structure, the oxidation reaction can completely remove the first metal layer.

According to another embodiment of the present invention, in the above method of manufacturing a semiconductor device structure, the capacitor may include a first electrode layer, a second electrode layer and a third dielectric layer. The first electrode layer can be electrically connected to the P-type semiconductor layer. The second electrode layer is located on the first electrode layer. The third dielectric layer is located between the first electrode layer and the second electrode layer.

According to another embodiment of the present invention, the method for manufacturing the semiconductor device structure may further include the following steps. Before forming the capacitor, the second metal layer located outside the second opening is removed. A fourth dielectric layer is formed on the capacitor and the second metal layer. A first interconnect structure and a second interconnect structure are formed in the fourth dielectric layer. The first interconnect structure is electrically connected to the second electrode layer, and the second interconnect structure is electrically connected to the second metal layer.

Based on the above, in the manufacturing method of the semiconductor element structure proposed by the present invention, a first metal layer is formed in the first opening, a second metal layer is formed in the second opening, and the first metal layer is electrically connected to the P-type semiconductor layer, and the second metal layer is electrically connected to the N-type semiconductor layer. Next, the substrate is placed in an electrolyte solution, where the electrolyte solution covers the first metal layer and the second metal layer. Then, the P-type semiconductor layer and the N-type semiconductor layer are exposed to light to perform an oxidation reaction and a reduction reaction in the electrolyte. At least part of the first metal layer in the first opening is removed by an oxidation reaction to form a void, and an amount of the second metal layer is increased by a reduction reaction. Next, a semiconductor element (eg, a capacitor or a fuse element) can be formed in the void. Thereby, the above-mentioned semiconductor device manufacturing process can be integrated with other manufacturing processes (eg, interconnection manufacturing process). In addition, since at least part of the first metal layer in the first opening is removed through the oxidation reaction, the process capability and process flexibility can be increased.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Examples are listed below and described in detail with reference to the drawings. However, the provided examples are not intended to limit the scope of the present invention. To facilitate understanding, the same components will be identified with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to original size. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

1A to 1L are cross-sectional views of a manufacturing process of a semiconductor device structure according to some embodiments of the present invention.

Referring to FIG. 1A , a dielectric layer 102 is formed on the substrate 100 . In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the material of the dielectric layer 102 is, for example, silicon oxide. In some embodiments, the dielectric layer 102 may be a shallow trench isolation structure formed by a shallow trench isolation (STI) process or a dielectric layer formed by a thermal oxidation method. However, the present invention does not This is the limit. As long as the dielectric layer 102 has an insulating function, it falls within the scope of the present invention.

Next, an N-type semiconductor material layer 104 may be formed on the dielectric layer 102 . In some embodiments, the material of the N-type semiconductor material layer 104 is, for example, N-type doped polycrystalline silicon. In some embodiments, the N-type semiconductor material layer 104 is formed by a chemical vapor deposition method such as in-situ doping. In other embodiments, a semiconductor material layer may be formed first by a chemical vapor deposition method, and then an N-type dopant may be doped into the semiconductor material layer by an ion implantation method to form the N-type semiconductor material layer 104 .

Referring to FIG. 1B , the N-type semiconductor material layer 104 can be patterned to form the N-type semiconductor layer 106 . In some embodiments, the N-type semiconductor material layer 104 can be patterned through a photolithography process and an etching process.

Referring to FIG. 1C , a patterned photoresist layer 108 can be formed on the dielectric layer 102 and the N-type semiconductor layer 106 . The patterned photoresist layer 108 may expose a portion of the N-type semiconductor layer 106 . In some embodiments, the patterned photoresist layer 108 may be formed by a photolithography process.

Next, the patterned photoresist layer 108 can be used as a mask to perform an ion implantation process IP1 on the N-type semiconductor layer 106 to form the P-type semiconductor layer 110 . Thereby, the P-type semiconductor layer 110 and the N-type semiconductor layer 106 connected to each other can be formed on the dielectric layer 102 . In some embodiments, the P-type semiconductor layer 110 and the N-type semiconductor layer 106 may be integrally formed. In this embodiment, the N-type semiconductor layer 106 is formed first, and then an ion implantation process is performed on the N-type semiconductor layer 106 to form the P-type semiconductor layer 110, but the invention is not limited thereto. In other embodiments, the P-type semiconductor layer 110 may be formed first, and then an ion implantation process is performed on the P-type semiconductor layer 110 to form the N-type semiconductor layer 106 .

Referring to FIG. 1D , the patterned photoresist layer 108 can be removed. In some embodiments, the patterned photoresist layer 108 is removed by, for example, dry stripping or wet stripping.

Next, a dielectric layer 112 is formed on the P-type semiconductor layer 110 and the N-type semiconductor layer 106 . In some embodiments, the material of the dielectric layer 112 is, for example, a low dielectric constant material or silicon oxide. In some embodiments, the dielectric layer 112 is formed by a chemical vapor deposition method, for example.

Referring to FIG. 1E , openings OP1 and openings OP2 are formed in the dielectric layer 112 . The opening OP1 exposes the P-type semiconductor layer 110 . The opening OP2 exposes the N-type semiconductor layer 106 . In some embodiments, a portion of the dielectric layer 112 may be removed through a patterning process to form the openings OP1 and OP2. In this embodiment, the opening OP1 and the opening OP2 are dual damascene openings as an example, but the invention is not limited thereto. In other embodiments, the opening OP1 and the opening OP2 may be single damascene openings.

Referring to FIG. 1F , a barrier material layer 114 may be conformally formed on the dielectric layer 112 and in the openings OP1 and OP2. In some embodiments, the material of the barrier material layer 114 is, for example, tantalum, tantalum nitride, or a combination thereof. In some embodiments, the barrier material layer 114 is formed by, for example, physical vapor deposition or chemical vapor deposition.

Next, a metal material layer 116 may be formed on the barrier material layer 114 . In some embodiments, the material of the metal material layer 116 is, for example, copper. In some embodiments, the metal material layer 116 is formed by, for example, physical vapor deposition, electrochemical plating (ECP), or a combination thereof.

Referring to FIG. 1G, the metal material layer 116 and the barrier material layer 114 located outside the opening OP1 and the opening OP2 can be removed to form a metal layer 116a, a metal layer 116b, a barrier layer 114a and a barrier layer 114b. . Thereby, the metal layer 116a can be formed in the opening OP1, the metal layer 116b can be formed in the opening OP2, and barriers can be formed between the metal layer 116a and the dielectric layer 112 and between the metal layer 116a and the P-type semiconductor layer 110. layer 114a, and a barrier layer 114b may be formed between the metal layer 116b and the dielectric layer 112 and between the metal layer 116b and the N-type semiconductor layer 106. The metal layer 116a is electrically connected to the P-type semiconductor layer 110. In some embodiments, the metal layer 116a may be electrically connected to the P-type semiconductor layer 110 via the barrier layer 114a. The metal layer 116b is electrically connected to the N-type semiconductor layer 106 . In some embodiments, the metal layer 116b may be electrically connected to the N-type semiconductor layer 106 via the barrier layer 114b. In some embodiments, the removal method of the metal material layer 116 and the barrier material layer 114 located outside the opening OP1 and the opening OP2 is, for example, chemical mechanical polishing.

Referring to FIG. 1H, the substrate 100 is placed in the electrolyte 200, where the electrolyte 200 covers the dielectric layer 112, the metal layer 116a and the metal layer 116b. In some embodiments, the electrolyte 200 can further cover the barrier layer 114a and the barrier layer 114b. In some embodiments, when the material of the metal layer 116a and the metal layer 116b is copper, the electrolyte 200 may be a copper sulfate solution or a copper nitrate solution.

Referring to FIG. 1I, the P-type semiconductor layer 110 and the N-type semiconductor layer 106 are subjected to a light treatment LT1 to perform an oxidation reaction and a reduction reaction in the electrolyte 200, wherein part of the metal layer in the opening OP1 is removed through the oxidation reaction. 116a to form the void V1, and increase the amount of the metal layer 116b through the reduction reaction. Since the P-type semiconductor layer 110 and the N-type semiconductor layer 106 have a PN junction, and the P-type semiconductor layer 110 and the N-type semiconductor layer 106 are subjected to the irradiation treatment LT1, electron-hole pairs are generated and are affected by the interface electric field. Function and separation. The electric holes flow to the P-type semiconductor layer 110, the metal layer 116a undergoes an oxidation reaction, the electric holes absorb the released electrons, and the metal layer 116a gradually disappears. The electrons flow to the N-type semiconductor layer 106, the metal layer 116b undergoes a reduction reaction, and the metal is deposited on the metal layer 116b, thereby increasing the amount of the metal layer 116b. In this embodiment, the top view area of the metal layer 116a is similar to the top view area of the metal layer 116b, but the invention is not limited thereto. In other embodiments, the top view area of the metal layer 116b may be larger than the top view area of the metal layer 116a, thereby preventing the height of the metal layer 116b located outside the opening OP2 from being too high to facilitate subsequent processes. In addition, the removal amount of the metal layer 116a and the addition amount of the metal layer 116b can be controlled by controlling the time of the irradiation process LT1.

Referring to FIG. 1J , the substrate 100 is taken out of the electrolyte 200 . Next, the metal layer 116b located outside the opening OP2 can be removed. In some embodiments, the metal layer 116b located outside the opening OP2 is removed by, for example, chemical mechanical polishing.

Then, the barrier material layer 118 and the conductive material layer 120 can be sequentially formed on the metal layer 116a, the barrier layer 114a, the metal layer 116b, the barrier layer 114b and the dielectric layer 112. In some embodiments, the material of the barrier material layer 118 is, for example, titanium, titanium nitride, or a combination thereof. In some embodiments, the barrier material layer 118 is formed by, for example, physical vapor deposition or chemical vapor deposition. In some embodiments, the conductive material layer 120 is made of, for example, tungsten. In some embodiments, the conductive material layer 120 is formed by a chemical vapor deposition method or a physical vapor deposition method, for example.

Referring to FIG. 1K , the conductive material layer 120 and the barrier material layer 118 located outside the void V1 can be removed, and the barrier layer 118a and the conductive layer 120a are formed in the void V1. The barrier layer 118a is located between the conductive layer 120a and the metal layer 116a. Thereby, the fuse element 122 can be formed. The fuse element 122 may include a metal layer 116a, a barrier layer 118a, and a conductive layer 120a. Since the resistance value of the conductive layer 120a may be higher than the resistance value of the metal layer 116a, when the current is too high, the barrier layer 118a will melt to achieve the effect of a fuse. In some embodiments, the barrier layer 118a may be further located between the conductive layer 120a and the barrier layer 114a. In some embodiments, the conductive material layer 120 and the barrier material layer 118 located outside the gap V1 are removed by, for example, chemical mechanical polishing.

1L, a dielectric layer 124 may be formed on the metal layer 116b, the barrier layer 114b, the conductive layer 120a, the barrier layer 118a, the barrier layer 114a and the dielectric layer 112. In some embodiments, the material of the dielectric layer 124 is, for example, a low dielectric constant material or silicon oxide. In some embodiments, the dielectric layer 124 is formed by a chemical vapor deposition method, for example.

Next, interconnect structures 126 and 128 may be formed in the dielectric layer 124 . The interconnect structure 126 is electrically connected to the conductive layer 120a, and the interconnect structure 128 is electrically connected to the metal layer 116b. In some embodiments, interconnect structures 126 and 128 may be formed by an interconnect process.

In some embodiments, the interconnect structure 126 may include a conductive layer 130 and a barrier layer 132 . The barrier layer 132 is located between the conductive layer 130 and the dielectric layer 124 and between the conductive layer 130 and the conductive layer 120a. Thereby, the fuse element 134 can be formed. The fuse element 134 may include a conductive layer 120a, a barrier layer 132, and a conductive layer 130. Since the resistance value of the conductive layer 120a can be higher than the resistance value of the conductive layer 130, when the current is too high, the barrier layer 132 will melt to achieve the effect of a fuse. In some embodiments, the material of the conductive layer 130 is, for example, copper. In some embodiments, the material of the barrier layer 132 is, for example, tantalum, tantalum nitride, or a combination thereof.

In some embodiments, the interconnect structure 128 may include a conductive layer 136 and a barrier layer 138 . The barrier layer 138 is located between the conductive layer 136 and the dielectric layer 124 and between the conductive layer 136 and the metal layer 116b. In some embodiments, the material of the conductive layer 136 is, for example, copper. In some embodiments, the material of the barrier layer 138 is, for example, tantalum, tantalum nitride, or a combination thereof.

Based on the above embodiments, it can be known that in the above manufacturing method of the semiconductor device structure 10, the metal layer 116a is formed in the opening OP1, and the metal layer 116b is formed in the opening OP2. The metal layer 116a is electrically connected to the P-type semiconductor layer 110, and the metal layer 116a is electrically connected to the P-type semiconductor layer 110. Layer 116b is electrically connected to the N-type semiconductor layer 106 . Next, the substrate 100 is placed in the electrolyte 200, where the electrolyte 200 covers the metal layer 116a and the metal layer 116b. Then, the P-type semiconductor layer 110 and the N-type semiconductor layer 106 are subjected to light treatment LT1 to perform an oxidation reaction and a reduction reaction in the electrolyte 200 . Part of the metal layer 116a in the opening OP1 is removed through the oxidation reaction to form the void V1, and the amount of the metal layer 116b is increased through the reduction reaction. Next, fuse element 122 may be formed in void V1. Thereby, the process of the fuse element 122 can be integrated with other processes (eg, interconnection process). In addition, since part of the metal layer 116a in the opening OP1 is removed through the oxidation reaction, the process capability and process flexibility can be increased.

2A to 2D are cross-sectional views of the manufacturing process of a semiconductor device structure according to other embodiments of the present invention.

Referring to Figure 2A, a structure as shown in Figure 1H can be provided. In addition, for details of the structure of FIG. 1H , reference can be made to the descriptions of FIGS. 1A to 1H , and the description will not be repeated here.

Referring to FIG. 2B , the P-type semiconductor layer 110 and the N-type semiconductor layer 106 are subjected to a light treatment LT2 to perform an oxidation reaction and a reduction reaction in the electrolyte 200 , wherein at least part of the metal in the opening OP1 is removed through the oxidation reaction. The layer 116a is formed to form the void V2, and the amount of the metal layer 116b is increased through the reduction reaction. In this embodiment, the oxidation reaction can completely remove the metal layer 116a, but the invention is not limited thereto. In this embodiment, the time of the illumination process LT2 in FIG. 2B may be longer than the time of the illumination process LT1 in FIG. 1I. In other embodiments, the oxidation reaction may remove only a portion of the metal layer 116a. In addition, for the rest of the steps of FIG. 2B , reference can be made to the description of FIG. 1I , and the description will not be repeated here.

Referring to FIG. 2C , the substrate 100 is taken out of the electrolyte 200 . Next, the metal layer 116b located outside the opening OP2 can be removed. In some embodiments, the metal layer 116b located outside the opening OP2 is removed by, for example, chemical mechanical polishing.

Then, capacitor 140 is formed in gap V2. In some embodiments, capacitor 140 may include electrode layer 142, electrode layer 144, and dielectric layer 146. The electrode layer 142 can be electrically connected to the P-type semiconductor layer 110 . In some embodiments, the electrode layer 142 may be electrically connected to the P-type semiconductor layer 110 via the barrier layer 114a. In some embodiments, the material of the electrode layer 142 is, for example, titanium nitride. The electrode layer 144 is located on the electrode layer 142 . In some embodiments, the material of the electrode layer 142 is, for example, tungsten. The dielectric layer 146 is located between the electrode layer 142 and the electrode layer 144 . In some embodiments, the material of the dielectric layer 146 is, for example, hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), or titanium dioxide (TiO ₂ ). In addition, the capacitor 140 can be manufactured by conventional methods, which will not be described again.

Referring to FIG. 2D, a dielectric layer 148 may be formed on the capacitor 140, the barrier layer 114a, the barrier layer 114b, the metal layer 116b and the dielectric layer 112. In some embodiments, the material of the dielectric layer 148 is, for example, a low dielectric constant material or silicon oxide. In some embodiments, the dielectric layer 148 is formed by a chemical vapor deposition method, for example.

Next, interconnect structures 150 and 152 may be formed in dielectric layer 148 . The interconnect structure 150 is electrically connected to the electrode layer 144, and the interconnect structure 152 is electrically connected to the metal layer 116b. In some embodiments, the interconnect structure 150 and the interconnect structure 152 may be formed by an interconnect process.

In some embodiments, the interconnect structure 150 may include a conductive layer 154 and a barrier layer 156 . The barrier layer 156 is located between the conductive layer 154 and the dielectric layer 148 and between the conductive layer 154 and the electrode layer 144 . In some embodiments, the material of the conductive layer 154 is, for example, tungsten or copper. In some embodiments, the material of the barrier layer 132 is, for example, titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof.

In some embodiments, interconnect structure 152 may include conductive layer 158 and barrier layer 160 . The barrier layer 160 is located between the conductive layer 158 and the dielectric layer 148 and between the conductive layer 158 and the metal layer 116b. In some embodiments, the material of conductive layer 158 is, for example, tungsten or copper. In some embodiments, the material of the barrier layer 160 is, for example, titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof.

Based on the above embodiments, it can be known that in the above manufacturing method of the semiconductor device structure 20, the metal layer 116a is formed in the opening OP1, and the metal layer 116b is formed in the opening OP2. The metal layer 116a is electrically connected to the P-type semiconductor layer 110, and the metal layer 116a is electrically connected to the P-type semiconductor layer 110. Layer 116b is electrically connected to the N-type semiconductor layer 106 . Next, the substrate 100 is placed in the electrolyte 200, where the electrolyte 200 covers the metal layer 116a and the metal layer 116b. Then, the P-type semiconductor layer 110 and the N-type semiconductor layer 106 are subjected to light treatment LT2 to perform an oxidation reaction and a reduction reaction in the electrolyte 200 . At least part of the metal layer 116a in the opening OP1 is removed through an oxidation reaction to form a void V2, and the amount of the metal layer 116b is increased through a reduction reaction. Next, capacitor 140 may be formed in void V2. Thereby, the process of the capacitor 140 can be integrated with other processes (eg, interconnection process), and the capacitor 140 can have a larger capacitance value. In addition, since at least part of the metal layer 116a in the opening OP1 is removed through the oxidation reaction, the process capability and process flexibility can be increased.

In summary, in the manufacturing method of the semiconductor device structure of the above embodiments, the manufacturing process of the semiconductor device (eg, capacitor or fuse element) can be integrated with other processes (eg, interconnection process). In addition, in the manufacturing method of the semiconductor device structure of the above embodiments, at least part of the metal layer can be removed through an oxidation reaction, thereby increasing the process capability and process flexibility.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

10,20:Semiconductor element structure 100:Base 102,112,124,146,148: Dielectric layer 104:N-type semiconductor material layer 106:N-type semiconductor layer 108:Patterned photoresist layer 110:P-type semiconductor layer 114,118: Barrier material layer 114a,114b,118a,132,138,156,160: barrier layer 116: Metal material layer 116a,116b: metal layer 120: Conductive material layer 120a,130,136,154,158: Conductive layer 122,134: Fuse element 126,128,150,152: Internal wiring structure 140:Capacitor 142,144:Electrode layer 200:Electrolyte IP1: Ion implantation process LT1, LT2: Lighting treatment OP1, OP2: Open V1, V2: gap

1A to 1L are cross-sectional views of a manufacturing process of a semiconductor device structure according to some embodiments of the present invention. 2A to 2D are cross-sectional views of the manufacturing process of a semiconductor device structure according to other embodiments of the present invention.

100:Base

102,112: Dielectric layer

106:N-type semiconductor layer

110:P-type semiconductor layer

114a, 114b: barrier layer

116a,116b: metal layer

200:Electrolyte

LT1: Lighting treatment

OP1, OP2: Open

V1: Gap

Claims (10)

A method for manufacturing a semiconductor element structure, including: forming a first dielectric layer on the substrate; forming a P-type semiconductor layer and an N-type semiconductor layer connected to each other on the first dielectric layer; forming a second dielectric layer on the P-type semiconductor layer and the N-type semiconductor layer; forming a first opening and a second opening in the second dielectric layer, wherein the first opening exposes the P-type semiconductor layer, and the second opening exposes the N-type semiconductor layer; A first metal layer is formed in the first opening, and a second metal layer is formed in the second opening, wherein the first metal layer is electrically connected to the P-type semiconductor layer, and the second The metal layer is electrically connected to the N-type semiconductor layer; placing the substrate in an electrolyte, wherein the electrolyte covers the second dielectric layer, the first metal layer and the second metal layer; The P-type semiconductor layer and the N-type semiconductor layer are illuminated to perform an oxidation reaction and a reduction reaction in the electrolyte, wherein a portion of the first opening is removed through the oxidation reaction. The first metal layer forms voids, and the amount of the second metal layer is increased through the reduction reaction; removing the substrate from the electrolyte; and A first barrier layer and a conductive layer are formed in the gap, wherein the first barrier layer is located between the conductive layer and the first metal layer. The manufacturing method of a semiconductor element structure as claimed in claim 1, wherein the P-type semiconductor layer and the N-type semiconductor layer are integrally formed. The method for manufacturing a semiconductor device structure as described in claim 1 further includes: A second barrier layer is formed between the first metal layer and the second dielectric layer and between the first metal layer and the P-type semiconductor layer, and between the second metal layer and the P-type semiconductor layer A third barrier layer is formed between the second dielectric layers and between the second metal layer and the N-type semiconductor layer. The method for manufacturing a semiconductor device structure as described in claim 1 further includes: Before forming the first barrier layer and the conductive layer, removing the second metal layer located outside the second opening; forming a third dielectric layer on the second metal layer, the conductive layer and the first barrier layer; and A first interconnect structure and a second interconnect structure are formed in the third dielectric layer, wherein the first interconnect structure is electrically connected to the conductive layer, and the second interconnect structure The structure is electrically connected to the second metal layer. A method for manufacturing a semiconductor element structure, including: forming a first dielectric layer on the substrate; forming a P-type semiconductor layer and an N-type semiconductor layer connected to each other on the first dielectric layer; forming a second dielectric layer on the P-type semiconductor layer and the N-type semiconductor layer; forming a first opening and a second opening in the second dielectric layer, wherein the first opening exposes the P-type semiconductor layer, and the second opening exposes the N-type semiconductor layer; A first metal layer is formed in the first opening, and a second metal layer is formed in the second opening, wherein the first metal layer is electrically connected to the P-type semiconductor layer, and the second The metal layer is electrically connected to the N-type semiconductor layer; placing the substrate in an electrolyte, wherein the electrolyte covers the second dielectric layer, the first metal layer and the second metal layer; The P-type semiconductor layer and the N-type semiconductor layer are illuminated to perform an oxidation reaction and a reduction reaction in the electrolyte, wherein at least one of the first openings is removed by the oxidation reaction. Part of the first metal layer forms voids, and the amount of the second metal layer is increased through the reduction reaction; removing the substrate from the electrolyte; and A capacitor is formed in the gap. The manufacturing method of a semiconductor element structure as claimed in claim 5, wherein the P-type semiconductor layer and the N-type semiconductor layer are integrally formed. The manufacturing method of the semiconductor element structure as described in claim 5 further includes: A first barrier layer is formed between the first metal layer and the second dielectric layer and between the first metal layer and the P-type semiconductor layer, and between the second metal layer and the A second barrier layer is formed between the second dielectric layers and between the second metal layer and the N-type semiconductor layer. The method of manufacturing a semiconductor device structure as claimed in claim 5, wherein the oxidation reaction completely removes the first metal layer. The manufacturing method of a semiconductor element structure as claimed in claim 5, wherein the capacitor includes: A first electrode layer, wherein the first electrode layer is electrically connected to the P-type semiconductor layer; a second electrode layer located on the first electrode layer; and A third dielectric layer is located between the first electrode layer and the second electrode layer. The method for manufacturing a semiconductor device structure as claimed in claim 9 further includes: Before forming the capacitor, removing the second metal layer located outside the second opening; forming a fourth dielectric layer on the capacitor and the second metal layer; and A first interconnect structure and a second interconnect structure are formed in the fourth dielectric layer, wherein the first interconnect structure is electrically connected to the second electrode layer, and the second interconnect structure The connection structure is electrically connected to the second metal layer.

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