TWI620333B - Schottky diode and method for manufacturing the same - Google Patents

Abstract

The Schottky diode of the embodiment of the present invention includes: a well region of a first conductivity type; a lightly doped region of a second conductivity type, located on the well region, and the first conductivity type and the second conductivity The opposite type; the heavily doped region of the second conductivity type is located on the well region; the gate structure is located on a portion of the lightly doped region, and the gate structure has a gate and a gate dielectric layer, wherein the gate The lightly doped region and the heavily doped region not covered by the structure are respectively located on opposite sides of the gate structure; the first contact is electrically connected to the heavily doped region and the first electrode; the second contact is electrically connected to the gate And the second electrode; and the third contact, electrically connecting the lightly doped region and the second electrode.

Description

Schottky diode and its formation method

The present invention relates to Schottky diodes, and more particularly to the structure and method of forming the same.

Contact of the metal with the lightly doped semiconductor material produces a contact structure (Schottky contact) similar to the PN junction and can be used to fabricate Schottky diodes. When a forward voltage is applied, the Schottky diode is in a conducting state, and current flows through the Schottky diode. When a reverse voltage is applied, the Schottky diode is turned off. In the ideal case, the reverse current is zero. In fact, the Schottky diode is not an ideal device and will have a small amount of reverse leakage current. Reverse leakage current can affect the performance of the circuit and reduce the efficiency of the circuit. In order to reduce the reverse leakage current, it is necessary to reduce the doping concentration of the lightly doped semiconductor material, but this will lower the startup speed of the Schottky diode.

In summary, a new Schottky diode is needed now, and its startup speed can be balanced while reducing its reverse leakage current.

A Schottky diode according to an embodiment of the present invention includes: a well region of a first conductivity type; a lightly doped region of a second conductivity type, located on the well region, and the first conductivity type and the second conductivity type The conductivity type is opposite; the second conductivity type is heavily doped The region is located on the well region; the gate structure is located on a portion of the lightly doped region, and the gate structure has a gate and a gate dielectric layer, wherein the lightly doped region and the heavily doped region are not covered by the gate structure Respectively located on opposite sides of the gate structure; the first contact electrically connecting the heavily doped region with the first electrode; the second contact electrically connecting the gate and the second electrode; and the third contact, electrical The lightly doped region and the second electrode are connected.

A method for forming a Schottky diode according to an embodiment of the present invention includes: forming a well region of a first conductivity type; forming a lightly doped region of a second conductivity type on the well region, and the first conductivity type The state is opposite to the second conductivity type; the gate structure is formed on a portion of the lightly doped region, and the gate structure has a gate and a gate dielectric layer; and the heavily doped region of the second conductivity type is formed in the portion In the lightly doped region and the well region below, the lightly doped region and the heavily doped region which are not covered by the gate structure are respectively located on opposite sides of the gate structure; the first contact is formed to be electrically doped heavily doped And a first electrode is formed to electrically connect the gate and the second electrode; and a third contact is formed to electrically connect the lightly doped region and the second electrode.

100‧‧‧Substrate

101‧‧‧Isolation structure

103‧‧‧ Well Area

105‧‧‧Lightly doped area

107‧‧‧ gate structure

107A‧‧‧gate dielectric layer

107B‧‧‧ gate

109‧‧‧Doped area

111, 116‧‧‧ photoresist layer

113‧‧‧ spacers

115‧‧‧ heavily doped area

117‧‧‧Interlayer dielectric layer

119A, 119B, 119C‧‧‧ contacts

1A to 1H are cross-sectional views showing a process of a Schottky diode in an embodiment of the present invention.

1A to 1H are cross-sectional views showing a process of a Schottky diode in an embodiment of the present invention. As shown in FIG. 1A, a substrate 100 of a first conductivity type is provided. In an embodiment of the invention, the substrate 100 may be a germanium wafer or a germanium-on-insulator (SOI) wafer, and the first conductivity type is p-type.

Next, as shown in section in FIG. 1B, a spacer structure 101 to define the Schottky diode (Schottky diode) in the region between the isolation structure 101. The isolation structure 101 shown in FIG. 1B is a partial ruthenium oxide (LOCOS), and the formation method thereof includes, but is not limited to, depositing a mask layer such as a tantalum nitride layer on the substrate 100, and patterning the mask layer by a lithography and etching process. A portion of the substrate 100 is exposed to thermally oxidize the exposed portion of the substrate 100 to form a hafnium oxide layer, and the patterned mask layer is removed. The yttrium oxide layer formed above is LOCOS. In other embodiments, the isolation structure 101 is shallow trench isolation (STI) or medium trench isolation (MTI), and the formation method thereof includes, but is not limited to, forming a mask layer on the substrate 100, and patterning by lithography and etching process. The mask layer exposes a portion of the substrate, etches the exposed portion of the substrate 100 to form trenches, fills the spacer material, such as yttrium oxide, into the trench, and removes the patterned mask layer.

Next, as shown in FIG. 1C, the well region 103 of the first conductivity type is formed in the Schottky diode region. In one embodiment, the well region 103 is p-type and can be formed by implanting a p-type dopant such as boron.

Next, as shown in FIG. 1D, a lightly doped region 105 of a second conductivity type is formed on the surface of the Schottky diode region. The second conductivity type is opposite to the first conductivity type. In one embodiment, the lightly doped region 105 is n-type and can be formed by implanting an n-type dopant such as phosphorus or arsenic. In one embodiment, the doped concentration of the lightly doped region 105 is between 5.0E11 and 1.0E13.

Next, as shown in FIG. 1E, a gate structure 107 is formed on a portion of the lightly doped region 105. In Fig. 1E, the gate structure 107 is located at the center of the Schottky diode region, but may be biased to either side without being limited to the central position shown. The method for forming the gate structure 107 includes, but is not limited to, sequentially depositing a gate dielectric layer and a gate layer, and patterning the gate dielectric layer and the gate layer by a lithography and etching process to define the gate structure 107. The gate dielectric layer 107A and the gate 107B. The above gate Electrical layer 107A can be yttrium oxide and gate 107B can be n-type doped or undoped polysilicon. When the gate 107B is an n-type doped polysilicon, the n-type dopant can be implanted on site when the gate layer is deposited.

Next, as shown in FIG. 1F, a doped region 109 in the second conductivity type is formed on one side of the gate structure 107. In one embodiment, the intermediate doping region 109 is n-type, and the forming method thereof includes, but is not limited to, forming the photoresist layer 111 on the gate structure 107 and the lightly doped region 105, and patterning the photoresist layer 111 with Exposing the lightly doped region 105 on one side of the gate structure 107 (without exposing the lightly doped region 105 on the other side of the gate structure 107), and implanting an n-type dopant such as phosphorus or arsenic to the exposed lightly doped region 105 is in the well area 103 below it. As shown in FIG. 1F, the boundary between the medium doped region 109 and the lightly doped region 105 is aligned with the sidewall edge of the gate structure 107. In an embodiment of the invention, the doping concentration of the medium doped region 109 is greater than the doping concentration of the lightly doped region 105. For example, the doping concentration of the medium doped region 109 is between 1.0E13 and 1.0E15.

Next, as shown in FIG. 1G, after the photoresist layer 111 is removed, a spacer 113 is formed on the sidewall of the gate structure 107 to cover the partially doped region 109. The method of removing the photoresist layer 111 may be dry ashing, wet stripping, or a combination thereof. In an embodiment of the invention, the method for forming the spacers 113 includes, but is not limited to, forming a spacer layer on the middle doped region 109, the gate structure 107, and the lightly doped region 105, and then performing anisotropic etching. A portion of the spacer layer is removed to retain spacers 113 on the sidewalls of the gate structure 107. In an embodiment of the invention, the spacer 113 may be tantalum oxide, tantalum nitride, hafnium oxynitride, or a multilayer structure as described above. A photoresist layer 116 is then formed to protect the lightly doped region 105, and a heavily doped region 115 of the second conductivity type is formed in the exposed portion of the doped region 109. In an embodiment, the heavily doped region 115 is n-type, and the formation method thereof includes, but is not limited to, implanting an n-type dopant such as phosphorus or arsenic. To the exposed medium doped region 109. As shown in FIG. 1G, the boundary between the heavily doped region 115 and the medium doped region 109 is aligned with the edge of the spacer 113. In an embodiment of the invention, the doping concentration of the heavily doped region 115 is greater than the doping concentration of the medium doped region 109. For example, the heavily doped region 115 has a doping concentration between 5.0E14 and 7.0E15.

Then, as shown in FIG. 1H, after the photoresist layer 116 is removed, the interlayer dielectric layer 117 is formed on the heavily doped region 115, and the contacts 119A, 119B, and 119C are formed to contact the heavily doped region 115 and the gate respectively. The pole 107B and the lightly doped region 105. The method of removing the photoresist layer 116 may be dry ashing, wet stripping, or a combination thereof. Contact 119A is connected to a first electrode (such as a cathode), and contacts 119B and 119C are connected to a second electrode (such as an anode). This completes the Schottky diode. In an embodiment of the invention, the forming methods of the contacts 119A, 119B, and 119C include, but are not limited to, forming a mask layer on the interlayer dielectric layer 117, and patterning the mask layer by the lithography and etching process and exposing the mask layer. The interlayer dielectric layer 117 is etched to remove the exposed interlayer dielectric layer 117 to form the heavily doped region 115 of the via exposed portion, the gate 107B, and the lightly doped region 105, and finally the conductive material is filled into the via hole. Contacts 119A, 119B, and 119C are formed. The above conductive material may be a metal such as tungsten, copper, silver, gold, the like, or an alloy thereof, which may be formed by sputtering, electroplating, or any suitable method.

Since the second electrode is electrically connected to the gate 107B and the lightly doped region 105 at the same time, the voltage applied to the gate 107B via the contact 119B can turn on the lightly doped region 105 (eg, the channel) under the gate structure 107, via The voltage applied to the lightly doped region 105 by the contact 119C can pass faster through the lightly doped region 105 under the gate structure, i.e., the actuation time required to shorten the Schottky diode. On the other hand, the above structure can adopt a lightly doped region 105 of a lower doping concentration to avoid the problem of reverse leakage current, and the gate The pole structure 107 avoids problems caused by reducing the concentration of the lightly doped region 105 (e.g., the actuation time of the Schottky diode is elongated). In short, the above Schottky diodes have the advantages of both fast start and low leakage current.

As shown in FIG. 1H, the lightly doped region 105 and the heavily doped region 115 which are not covered by the gate structure 107 are respectively located on opposite sides of the gate structure 107 to achieve the above advantages. On the other hand, the overlap length of the gate structure 107 and the lightly doped region 105 is between 0.3 μm and 1.0 μm. If the overlap length is too long, it may increase the start-up time of the Schottky diode. If the above overlap length is too short, a problem of leakage current may occur.

In the above embodiment, the substrate 100 and the well region 103 are p-type, the lightly doped region 105, the medium doped region 109, and the heavily doped region 115 are n-type, the first electrode is a cathode, and the second electrode is an anode. . In another embodiment, the substrate 100 and the well region 103 are n-type, and the lightly doped region 105, the middle doped region 109, and the heavily doped region 115 are p-type. The first electrode is a cathode and the second electrode is an anode.

While the invention has been described above in terms of several embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make any changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (14)

A Schottky diode comprising: a well region of a first conductivity type; a lightly doped region of a second conductivity type, located on the well region, and the first conductivity type and the first The second conductivity type is opposite; the heavily doped region of the second conductivity type is located on the well region; a gate structure is located on a portion of the lightly doped region, and the gate structure has a gate and a gate a gate dielectric layer, wherein the lightly doped region and the heavily doped region not covered by the gate structure are respectively located on opposite sides of the gate structure; a first contact electrically connecting the heavily doped region And a first electrode; a second contact electrically connected to the gate and a second electrode; and a third contact electrically connected to the lightly doped region and the second electrode. The Schottky diode of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type. The Schottky diode according to claim 1, wherein the first conductivity type is an n-type and the second conductivity type is a p-type. The Schottky diode according to claim 1, wherein the heavily doped region has a doping concentration greater than a doping concentration of the lightly doped region. The Schottky diode according to claim 1, wherein an overlap length of the gate structure and the lightly doped region is between 0.3 μm and 1.0 μm. The Schottky diode of claim 1, further comprising a spacer on a sidewall of the gate structure and a doped region in one of the second conductivity types, wherein the heavily doped a region is located in the middle doped region, and a portion of the doped region is located between the heavily doped region and the lightly doped region, the heavily doped region and the The junction of the mid-doped regions is aligned with the edge of the spacer, and the interface between the mid-doped region and the lightly doped region is aligned with the edge of the gate structure. The Schottky diode according to claim 6 , wherein a doping concentration of the heavily doped region is greater than a doping concentration of the doped region, and a doping concentration of the doped region is greater than the doping concentration Doping concentration of lightly doped regions. A method for forming a Schottky diode includes: forming a well region of a first conductivity type; forming a lightly doped region of a second conductivity type on the well region, and the first conductivity type The state is opposite to the second conductivity type; forming a gate structure on a portion of the lightly doped region, and the gate structure has a gate and a gate dielectric layer; forming the second conductivity type a heavily doped region is disposed in a portion of the lightly doped region and the well region underneath, wherein the lightly doped region and the heavily doped region not covered by the gate structure are respectively located on opposite sides of the gate structure; Forming a first contact electrically connected to the heavily doped region and a first electrode; forming a second contact electrically connecting the gate and a second electrode; and forming a third contact The lightly doped region and the second electrode are electrically connected. The method for forming a Schottky diode according to claim 8, wherein the first conductivity type is p-type and the second conductivity type is n-type. The method for forming a Schottky diode according to claim 8, wherein the first conductivity type is an n-type and the second conductivity type is a p-type. The method for forming a Schottky diode according to claim 8 , wherein a doping concentration of the heavily doped region is greater than a doping concentration of the lightly doped region. a method for forming a Schottky diode according to claim 8 of the patent application, The overlap length of the gate structure and the lightly doped region is between 0.3 μm and 1.0 μm. The method for forming a Schottky diode according to claim 8 , further comprising: forming a spacer on a sidewall of the gate structure; and forming a doped region in the second conductivity type Wherein the heavily doped region is located in the middle doped region, and a portion of the doped region is located between the heavily doped region and the lightly doped region, and a boundary between the heavily doped region and the middle doped region An edge of the spacer is aligned, and a boundary of the middle doped region and the lightly doped region is aligned with an edge of the gate structure. The method for forming a Schottky diode according to claim 13 , wherein a doping concentration of the heavily doped region is greater than a doping concentration of the doped region, and the doping region is doped The concentration is greater than the doping concentration of the lightly doped region.