TWI828551B - Thin film transistor - Google Patents

Abstract

A thin film transistor includes a first metal pattern, an insulating structure, a polysilicon layer, a source and a drain. The first metal pattern is located above a substrate. An angle between at least one side surface of the first metal pattern and a bottom surface of the first metal pattern is from 10 degrees to 35 degrees. The insulating structure is conformally formed on the first metal pattern. The polysilicon layer is conformally formed on the insulating structure and overlaps the first metal pattern. The polysilicon layer includes grains with a grain length greater than 400 Angstroms. The source and the drain are electrically connected to the polysilicon layer.

Description

thin film transistor

The present invention relates to a thin film transistor.

With the advancement of technology, electronic products have become inseparable from our lives, and displays play a very important role. Whether it is a mobile phone, a tablet computer, or a smart watch, the display serves as the interface for human-machine communication. In traditional display devices, amorphous silicon thin film transistors are usually included. However, due to the low carrier mobility of amorphous silicon thin film transistors, it is difficult for amorphous silicon thin film transistor display devices to achieve the advantages of thinness, power saving, and high image quality.

In order to improve the carrier mobility of thin film transistors, a low temperature polysilicon (LTPS) thin film transistor has been proposed. Generally speaking, low-temperature polycrystalline silicon processes are mostly carried out using Excimer Laser Annealing (ELA) technology, which uses excimer lasers to provide heat energy to convert the amorphous silicon structure into a polycrystalline silicon structure. The excimer laser is irradiated on the substrate on which amorphous silicon is deposited, so that the amorphous silicon absorbs energy and transforms into polycrystalline silicon.

The present invention provides a thin film transistor that can solve the problem of insufficient carrier mobility of a polycrystalline silicon layer.

At least one embodiment of the present invention provides a thin film transistor. The thin film transistor includes a first metal pattern, an insulation structure, a polycrystalline silicon layer, a source electrode and a drain electrode. The first metal pattern is located on the substrate. The angle between at least one side surface of the first metal pattern and the bottom surface of the first metal pattern is 10 degrees to 35 degrees. The insulation structure is conformally formed on the first metal pattern. The polycrystalline silicon layer is conformally formed on the insulating structure and overlaps the first metal pattern. The polycrystalline silicon layer contains grains with grain lengths greater than 400 Angstroms. The source electrode and the drain electrode are electrically connected to the polycrystalline silicon layer.

At least one embodiment of the present invention provides a thin film transistor. The thin film transistor includes a first metal pattern, an insulation structure, a polycrystalline silicon layer, a source electrode and a drain electrode. The first metal pattern is located on the substrate. The cross-sectional shape of the first metal pattern includes at least one triangle. An insulation structure is formed on the first metal pattern. A polycrystalline silicon layer is formed on the insulating structure and overlaps the first metal pattern. The polycrystalline silicon layer contains grains with grain lengths greater than 400 Angstroms. The source electrode and the drain electrode are electrically connected to the polycrystalline silicon layer.

100: First conductive layer

100’: first conductive material layer

110:Scan line

120,120A,120B: First metal pattern

122:Conductive structure

122a: first side

122b: Second side

122c: Bottom surface

122d:Top surface

200, 200A, 200B: polycrystalline silicon layer

200’: Amorphous silicon layer

210: Passage area

222: First lightly doped region

224: The second lightly doped region

232: First heavily doped region

234: The second heavily doped region

200a: first inclined part

200b: Second inclined part

200d:Platform Department

300: Second conductive layer

310:Data line

320, 320A, 320B: source

330,330A,330B: drain

400,410: Pixel electrode

420: Adapter electrode

430: Common electrode

D1: first direction

h: Thickness

I1: First insulation structure

I1a: silicon oxide layer

I1b: silicon nitride layer

I2: Second insulation structure

I2a: Gate insulation layer

I2b: interlayer dielectric layer

I3: The third insulation structure

I4: The fourth insulation structure

L, L’, L”: length

ND: normal direction

P: pitch

SB:Substrate

T1, T2: thin film transistor

TG1: The first top gate

TG2: The second top gate

θ, θ1, θ2: angle

FIG. 1A is a schematic top view of a pixel structure according to an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view along line A-A' of Fig. 1A.

2A to 2E are diagrams of a polycrystalline silicon layer according to an embodiment of the present invention. Schematic cross-section of the manufacturing method.

FIG. 3 is a schematic cross-sectional view of a pixel structure according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a pixel structure according to an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a pixel structure according to an embodiment of the present invention.

Figure 6 is a scanning electron microscope photograph of a polycrystalline silicon layer according to an embodiment of the present invention.

7A is a scanning electron microscope photograph of a first metal pattern, a first insulating structure and a polycrystalline silicon layer according to an embodiment of the present invention.

7B is a transmission electron microscope photograph of a first metal pattern, a first insulating structure and a polycrystalline silicon layer according to an embodiment of the present invention.

8A to 8C are transmission electron microscopy photos of the first metal pattern formed using different etching parameters.

Figures 9A to 9E are transmission electron microscopy photos of polycrystalline silicon layers formed using excimer laser annealing processes with different energies.

Figure 10 is an experimental data diagram showing the energy of the excimer laser annealing process and the grain length of the polycrystalline silicon layer.

Figure 1A is a top view of a pixel structure according to an embodiment of the present invention. Schematic diagram. Fig. 1B is a schematic cross-sectional view along line A-A' of Fig. 1A. Referring to FIGS. 1A and 1B , the pixel structure includes a thin film transistor T1 and a pixel electrode 400 . The thin film transistor T1 includes a first metal pattern 120 , a first insulation structure I1 , a polycrystalline silicon layer 200 , a source electrode 320 and a drain electrode 330 .

The material of the substrate SB can be glass, quartz, organic polymer, opaque/reflective material (such as conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive materials or metals are used, an insulating layer (not shown) is covered on the substrate SB to avoid short circuit problems.

The first metal pattern 120 is located on the substrate SB. In this embodiment, the first metal pattern 120 is the gate of the thin film transistor T1 , and the first metal pattern 120 is electrically connected to the scan line 110 . In this embodiment, the first metal pattern 120 is directly connected to the scan line 110 . The first metal pattern 120 and the scan line 110 belong to the same first conductive layer 100 . In some embodiments, the material of the first conductive layer 100 includes chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel and other metals, and alloys of the above metals. or stacked layers of the above metals. In some embodiments, the thickness of the first metal pattern 120 is 100 nm to 400 nm.

The angle between at least one side surface of the first metal pattern 120 and the bottom surface of the first metal pattern 120 is 10 degrees to 35 degrees. For example, the first metal pattern 120 includes a plurality of conductive structures 122, and each conductive structure 122 is electrically connected to the same scan line 110. In this embodiment, the plurality of conductive structures 122 are arranged in the first direction D1, and the plurality of conductive structures 122 have a pitch P in the first direction D1, where the pitch P is 0.8 microns to 3.5 microns.

The cross-sectional shape of the first metal pattern 120 includes at least one triangle. In this embodiment, the cross-sectional shape of the first metal pattern 120 includes a plurality of triangles. Specifically, the cross-sectional shape of each conductive structure 122 in the first metal pattern 120 includes a triangle. Each conductive structure 122 includes a first side surface 122a, a second side surface 122b and a bottom surface 122c, wherein the angle θ1 between the first side surface 122a and the bottom surface 122c and the angle θ2 between the second side surface 122b and the bottom surface 122c are both 10 degrees to 35 degrees. Spend. It should be noted that the angle θ1 between the first side surface 122a and the bottom surface 122c refers to the angle between the extension direction of the first side surface 122a and the extension direction of the bottom surface 122c, and the angle between the second side surface 122b and the bottom surface 122c. θ2 refers to the angle between the extending direction of the second side surface 122b and the extending direction of the bottom surface 122c. The first side surface 122a and the bottom surface 122c and the second side surface 122b and the bottom surface 122c may include rounded corners or acute corners. In addition, a rounded corner or an acute corner may also be included between the first side surface 122a and the second side surface 122b. In this embodiment, the cross-sectional shape of each conductive structure 122 includes an isosceles triangle, and the length L of the first side 122a is equal to the length L of the second side 122b.

h

8000Å。在一些實施例中，當厚度h大於5000Å時，第一絕緣結構I1在準分子雷射退火中對多晶矽層200的保溫效果較佳，藉此可以減少準分子雷射退火所需的能量。 The first insulation structure I1 is formed on the first conductive layer 100 . In some embodiments, the first insulation structure I1 is conformally formed on the first metal pattern 120 . The first insulation structure I1 overlaps the scanning line 110 and the first metal pattern 120 in the normal direction ND of the top surface of the substrate SB. In some embodiments, the material of the first insulating structure I1 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide or other insulating materials. In some embodiments, the first insulation structure I1 includes a single-layer structure or a multi-layer structure. For example, the first insulation structure I1 includes a stack of silicon nitride and silicon oxide, where the silicon nitride contacts the first metal pattern 120, And the silicon oxide contacts the polycrystalline silicon layer 200 . In some embodiments, the first insulating structure I1 includes multiple layers of silicon nitride and multiple layers of silicon oxide, wherein silicon nitride and silicon oxide are alternately stacked. In some embodiments, the thickness of the first insulating structure I1 is h, 3000 Å

h

8000Å. In some embodiments, when the thickness h is greater than 5000 Å, the first insulating structure I1 has a better heat preservation effect on the polycrystalline silicon layer 200 during excimer laser annealing, thereby reducing the energy required for excimer laser annealing.

In this embodiment, since the angle between at least one side surface of the first metal pattern 120 and the bottom surface of the first metal pattern 120 is 10 degrees to 35 degrees, the first insulation structure I1 formed on the first metal pattern 120 is The top surface includes a bevel.

The polycrystalline silicon layer 200 is conformally formed on the first insulation structure I1 and overlaps the first metal pattern 120 in the normal direction ND of the top surface of the substrate SB. Since the top surface of the first insulation structure I1 includes a slope, the polycrystalline silicon layer 200 conforming to the first insulation structure I1 includes a plurality of slope portions conforming to the slope. Specifically, the polysilicon layer 200 includes a plurality of first inclined portions 200a overlapping the first side 122a in the normal direction ND and a plurality of second inclined portions 200b overlapping the second side 122b in the normal direction ND, The first inclined portions 200a and the second inclined portions 200b are alternately arranged.

In this embodiment, since the conductive structure 122 has a pitch P in the first direction D1, the length L' of each of the first inclined portion 200a and the second inclined portion 200b is greater than the first side 122a and the second side 122b. The length L of each of them.

In this embodiment, the polycrystalline silicon layer 200 is doped to include a first heavily doped region 232, a second heavily doped region 234, a first lightly doped region 222, and a second lightly doped region. 224 and channel area 210. The channel region 210 is located between the first lightly doped region 222 and the second lightly doped region 224 , the first lightly doped region 222 is located between the channel region 210 and the first heavily doped region 232 , and the second lightly doped region 224 Located between the channel region 210 and the second heavily doped region 234 . In this embodiment, the first lightly doped region 222 and the second lightly doped region 224 respectively overlap with the two outermost side surfaces of the first metal pattern 120 in the normal direction ND. For example, the first lightly doped region 222 overlaps the leftmost first side 122a in the normal direction ND, and the second lightly doped region 224 overlaps the rightmost second side 122b in the normal direction ND. . In this embodiment, the partial channel region 210 overlaps the gap between the two conductive structures 122 in the normal direction ND. In other words, the partial channel area 210 does not overlap the first metal pattern 120 in the normal direction ND.

In some embodiments, the first heavily doped region 232, the second heavily doped region 234, the first lightly doped region 222 and the second lightly doped region 224 in the polycrystalline silicon layer 200 are all N-type semiconductors, wherein the The doping concentrations of the first heavily doped region 232 and the second heavily doped region 234 are greater than the doping concentrations of the first lightly doped region 222 and the second lightly doped region 224 . In other embodiments, the first heavily doped region 232 and the second heavily doped region 234 in the polycrystalline silicon layer 200 are both P-type semiconductors, and the first lightly doped region 222 and the second lightly doped region 224 can be omitted. .

In this embodiment, when the excimer laser annealing technology is used to form the polycrystalline silicon layer 200, the crystal grains in the polycrystalline silicon layer 200 will be elongated by gravity. Therefore, it is not necessary to use a high-energy excimer laser to obtain a longer length. of grains. Specifically, through the design of the first metal pattern 120, the polycrystalline silicon layer 200 located above it can be (The amorphous silicon layer before performing the excimer laser annealing process) has multiple inclined parts. Through the design of the inclined parts, the amorphous silicon can be stretched by gravity during recrystallization, thereby making the crystalline layer after recrystallization Grain has a longer length. In some embodiments, polycrystalline silicon layer 200 contains grains with grain lengths greater than 400 Angstroms. For example, at least some of the grains in the polycrystalline silicon layer 200 have a grain length greater than 500 angstroms, greater than 600 angstroms, greater than 700 angstroms, greater than 800 angstroms, or greater than 900 angstroms. By allowing the polycrystalline silicon layer 200 to include grains with a grain length greater than 400 Angstroms, the carrier mobility of the polycrystalline silicon layer 200 can be improved.

The second insulation structure I2 is located on the polysilicon layer 200 . In some embodiments, the material of the second insulation structure I2 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulating materials or other insulating materials. In some embodiments, the second insulation structure I2 includes a single-layer structure or a multi-layer structure.

The source electrode 320 and the drain electrode 330 are located on the second insulation structure I2 and are electrically connected to the polycrystalline silicon layer 200 . In this embodiment, the source electrode 320 and the drain electrode 330 fill the through holes in the second insulation structure I2 and contact the first heavily doped region 232 and the second heavily doped region 234 of the polycrystalline silicon layer 200 respectively. In this embodiment, the source 320 is directly connected to the data line 310 . The data line 310, the source electrode 320 and the drain electrode 330 belong to the same second conductive layer 300. In some embodiments, the material of the second conductive layer 300 includes chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel and other metals, and alloys of the above metals. or stacked layers of the above metals.

The third insulating structure I3 is located on the second conductive layer 300 and covers the data line 310, the source electrode 320 and the drain electrode 330. In some embodiments, the third insulating structure I3 The materials include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulating materials or other insulating materials. In some embodiments, the third insulation structure I3 includes a single-layer structure or a multi-layer structure.

The pixel electrode 400 is located on the three-insulation structure I3. The pixel electrode 400 fills the through hole in the third insulation structure I3 and contacts the drain electrode 330 . In some embodiments, the material of the pixel electrode 400 includes indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or a stacked layer of at least two of the above.

2A to 2E are schematic cross-sectional views of a method for manufacturing a polycrystalline silicon layer according to an embodiment of the present invention. For example, FIGS. 2A to 2E are schematic cross-sectional views of the manufacturing method of the polycrystalline silicon layer 200 in FIGS. 1A and 1B .

Referring to FIG. 2A, a first conductive material layer 100' is formed on the substrate SB.

Referring to FIG. 2B, one or more patterning processes are performed on the first conductive material layer 100' to form the first metal pattern 120 on the substrate SB. For example, a photoresist layer is formed on the first conductive material layer 100' through one or more photolithography processes, and one or more etchings are performed on the first conductive material layer 100' using the photoresist layer as a mask. To form a first metal pattern 120 including a plurality of conductive structures 122 . In some embodiments, one or more patterning processes are performed on the first conductive material layer 100' to form the first metal pattern 120 and scan lines (not shown in FIG. 2B) on the substrate SB.

Referring to FIG. 2C , a first insulation structure I1 is formed on the first metal pattern 120 .

Referring to FIG. 2D, an amorphous silicon layer 200' is formed on the first insulation structure I1.

Referring to FIG. 2E, a patterning process is performed on the amorphous silicon layer 200', and an excimer laser annealing process is performed from the front side of the amorphous silicon layer 200' to recrystallize the amorphous silicon into polycrystalline silicon. Then, one or more doping processes are used to dope the polycrystalline silicon to form the polycrystalline silicon layer 200 . In some embodiments, before performing the doping process, a mask is formed over the polysilicon, and the mask defines the location in the polysilicon layer 200 where the doping process is to be performed. In some embodiments, after performing the doping process, the mask is removed.

In this embodiment, since the amorphous silicon layer 200' has multiple inclined portions, through the design of the inclined portions, the amorphous silicon can be stretched by gravity during recrystallization, thereby making the recrystallized grains have a larger long length.

In some embodiments, a second insulating structure, a source electrode, and a drain electrode are formed on the polycrystalline silicon layer 200 to obtain a thin film transistor.

FIG. 3 is a schematic cross-sectional view of a pixel structure according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 3 follows the component numbers and part of the content of the embodiment of FIG. 1A and FIG. 1B , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the embodiment of FIG. 3 and the embodiment of FIG. 1A is that in the embodiment of FIG. 3 , the cross-sectional shape of the first metal pattern 120 includes at least one trapezoid.

Referring to FIG. 3 , in this embodiment, the angle between at least one side surface of the first metal pattern 120 and the bottom surface of the first metal pattern 120 is 10 degrees to 35 degrees. For example, the first metal pattern 120 includes a plurality of conductive structures 122, and each conductive structure 122 is electrically connected to the same scan line 110. In this embodiment, the plurality of conductive structures 122 are arranged in the first direction D1, and the plurality of conductive structures 122 have a pitch P in the first direction D1, where the pitch P is 0.8 microns to 3.5 microns.

The cross-sectional shape of the first metal pattern 120 includes at least one trapezoid. In this embodiment, the cross-sectional shape of the first metal pattern 120 includes a plurality of trapezoids. Specifically, the cross-sectional shape of each conductive structure 122 in the first metal pattern 120 includes a trapezoid. Each conductive structure 122 includes a first side surface 122a, a second side surface 122b, a bottom surface 122c and a top surface 122d, wherein the angle θ1 between the first side surface 122a and the bottom surface 122c and the angle θ2 between the second side surface 122b and the bottom surface 122c are both 10 degrees to 35 degrees. It should be noted that the angle θ1 between the first side surface 122a and the bottom surface 122c refers to the angle between the extension direction of the first side surface 122a and the extension direction of the bottom surface 122c, and the angle between the second side surface 122b and the bottom surface 122c. θ2 refers to the angle between the extending direction of the second side surface 122b and the extending direction of the bottom surface 122c. The first side surface 122a and the bottom surface 122c and the second side surface 122b and the bottom surface 122c may include rounded corners or acute corners.

The first insulation structure I1 is conformally formed on the first metal pattern 120 .

The polycrystalline silicon layer 200 is conformally formed on the first insulation structure I1 and overlaps the first metal pattern 120 in the normal direction ND of the top surface of the substrate SB. Since the top surface of the first insulating structure I1 includes a slope, the polycrystalline surface conformal to the first insulating structure I1 The silicon layer 200 includes a plurality of inclined portions conformable to the aforementioned inclined surfaces. Specifically, the polycrystalline silicon layer 200 includes a plurality of first inclined portions 200a overlapping the first side surface 122a in the normal direction ND and a plurality of second inclined portions 200b overlapping the second side surface 122b in the normal direction ND. The first inclined portions 200a and the second inclined portions 200b are alternately arranged. In this embodiment, the polycrystalline silicon layer 200 further includes a plurality of platform portions 200d overlapping the top surface 122d in the normal direction ND. Each first inclined portion 200a and the corresponding second inclined portion 200b are located on both sides of the corresponding platform portion 200d. In some embodiments, the length X1 of the top surface 122d of each conductive structure 122 is less than or equal to 0.5 microns, thereby preventing the length X2 of the platform portion 200d in the polycrystalline silicon layer 200 from being too long. The length X2 of the platform portion 200d is 0.1 micron to 1 micron.

In this embodiment, the first lightly doped region 222 and the second lightly doped region 224 respectively overlap with the two outermost side surfaces of the first metal pattern 120 in the normal direction ND. For example, the first lightly doped region 222 overlaps the leftmost first side 122a, and the second lightly doped region 224 overlaps the rightmost second side 122b. In this embodiment, the partial channel region 210 overlaps the gap between the two conductive structures 122 in the normal direction ND. In other words, the partial channel area 210 does not overlap the first metal pattern 120 in the normal direction ND.

In some embodiments, the first heavily doped region 232, the second heavily doped region 234, the first lightly doped region 222 and the second lightly doped region 224 in the polycrystalline silicon layer 200 are all N-type semiconductors, wherein the The doping concentrations of the first heavily doped region 232 and the second heavily doped region 234 are greater than the doping concentrations of the first lightly doped region 222 and the second lightly doped region 224 . In other embodiments, the first heavily doped region in polysilicon layer 200 232. The second heavily doped region 234 is both a P-type semiconductor, and the first lightly doped region 222 and the second lightly doped region 224 can be omitted.

In this embodiment, when the excimer laser annealing technology is used to form the polycrystalline silicon layer 200, the crystal grains in the polycrystalline silicon layer 200 will be elongated by gravity. Therefore, it is not necessary to use a high-energy excimer laser to obtain a longer length. of grains. Specifically, through the design of the first metal pattern 120, the polycrystalline silicon layer 200 located above it (the amorphous silicon layer before the excimer laser annealing process is performed) can have multiple inclined portions. Through the design of the inclined portions, , which can cause amorphous silicon to be stretched by gravity during recrystallization, thereby making the recrystallized grains have a longer length. In some embodiments, polycrystalline silicon layer 200 contains grains with grain lengths greater than 400 Angstroms. For example, at least some of the grains in the polycrystalline silicon layer 200 have a grain length greater than 500 angstroms, greater than 600 angstroms, greater than 700 angstroms, greater than 800 angstroms, or greater than 900 angstroms. By allowing the polycrystalline silicon layer 200 to include grains with a grain length greater than 400 Angstroms, the carrier mobility of the polycrystalline silicon layer 200 can be improved.

FIG. 4 is a schematic cross-sectional view of a pixel structure according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 4 follows the component numbers and part of the content of the embodiment of FIG. 1A and FIG. 1B , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

Please refer to FIG. 4 . In this embodiment, the pixel structure includes a thin film transistor T1 , a thin film transistor T2 , a pixel electrode 410 , a transfer electrode 420 and a common electrode 430 .

The thin film transistor T1 includes a first metal pattern 120A, a first insulation structure I1, a polysilicon layer 200A, a source electrode 320A, and a drain electrode 330A. The thin film transistor T2 includes a first metal pattern 120B, a first insulation structure I1, a polysilicon layer 200B, a source electrode 320B and a drain electrode 330B.

Each of the first metal pattern 120A and the first metal pattern 120B includes a plurality of conductive structures 122 . In this embodiment, the first metal pattern 120A and the first metal pattern 120B each include three conductive structures 122 . The first metal pattern 120A and the first metal pattern 120B belong to the same film layer. For example, the first metal pattern 120A and the first metal pattern 120B both belong to the first conductive layer. In other words, the first metal pattern 120A and the first metal pattern 120B are formed simultaneously.

The first insulation structure I1 is conformally formed on the first metal pattern 120A and the first metal pattern 120B. In this embodiment, the thin film transistor T1 and the thin film transistor T2 share the first insulation structure I1.

The polycrystalline silicon layer 200A and the polycrystalline silicon layer 200B are conformally formed on the first insulation structure I1 and overlap with the first metal pattern 120A and the first metal pattern 120B respectively in the normal direction ND of the top surface of the substrate SB. Since the top surface of the first insulation structure I1 includes a slope, the polycrystalline silicon layer 200A and the polycrystalline silicon layer 200B conforming to the first insulation structure I1 include a plurality of slope portions conforming to the slope. Through the design of the inclined portion, the amorphous silicon can be stretched by gravity during recrystallization, thereby making the recrystallized grains have a longer length. In some embodiments, polycrystalline silicon layer 200A and polycrystalline silicon layer 200B include grains with grain lengths greater than 400 Angstroms. For example, the grain length of at least some of the grains in the polycrystalline silicon layer 200A and the polycrystalline silicon layer 200B is Greater than 500 Angstroms, greater than 600 Angstroms, greater than 700 Angstroms, greater than 800 Angstroms, or greater than 900 Angstroms. By allowing the polycrystalline silicon layer 200A and the polycrystalline silicon layer 200B to include grains with a grain length greater than 400 Angstroms, the carrier mobility of the polycrystalline silicon layer 200A and the polycrystalline silicon layer 200B can be improved.

In this embodiment, the polysilicon layer 200A is doped to include a first heavily doped region 232 , a second heavily doped region 234 , a first lightly doped region 222 , a second lightly doped region 224 and a channel region 210 . The polysilicon layer 200B is doped to include a first heavily doped region 232, a second heavily doped region 234, and a channel region 210. In this embodiment, the first heavily doped region 232, the second heavily doped region 234, the first lightly doped region 222 and the second lightly doped region 224 in the polycrystalline silicon layer 200A are all N-type semiconductors, wherein the The doping concentrations of the first heavily doped region 232 and the second heavily doped region 234 are greater than the doping concentrations of the first lightly doped region 222 and the second lightly doped region 224 . In this embodiment, the first heavily doped region 232 and the second heavily doped region 234 in the polycrystalline silicon layer 200B are both P-type semiconductors.

The second insulation structure I2 is located on the polycrystalline silicon layer 200A and the polycrystalline silicon layer 200B.

The source electrode 320A, the drain electrode 330A, the source electrode 320B, the drain electrode 330B and the common signal line 340 are located on the second insulating structure I2. The source electrode 320A and the drain electrode 330A are electrically connected to the polysilicon layer 200A, and the source electrode 320B and the drain electrode 330A are electrically connected to the polysilicon layer 200A. Pole 330B is electrically connected to polysilicon layer 200B. In this embodiment, the source electrode 320A and the drain electrode 330A fill the through holes in the second insulation structure I2 and contact the first heavily doped region 232 and the second heavily doped region 234 of the polycrystalline silicon layer 200A respectively. In this example, the source The electrode 320B and the drain electrode 330B fill the through holes in the second insulation structure I2 and contact the first heavily doped region 232 and the second heavily doped region 234 of the polycrystalline silicon layer 200B respectively.

The source electrode 320A, the drain electrode 330A, the source electrode 320B, the drain electrode 330B and the common signal line 340 belong to the same film layer. For example, the source electrode 320A, the drain electrode 330A, the source electrode 320B, the drain electrode 330B and the common signal line 340 are all Belongs to the second conductive layer. In other words, the source electrode 320A, the drain electrode 330A, the source electrode 320B, the drain electrode 330B and the common signal line 340 are formed at the same time.

The third insulating structure I3 is located on the source electrode 320A, the drain electrode 330A, the source electrode 320B, the drain electrode 330B and the common signal line 340.

The transfer electrode 420 and the common electrode 430 are located on the three-insulation structure I3. The transfer electrode 420 fills the through hole in the third insulating structure I3 and contacts the drain electrode 330A. The common electrode 430 fills the through hole in the third insulation structure I3 and contacts the common signal line 340 . In some embodiments, the materials of the transfer electrode 420 and the common electrode 430 include indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or at least two of the above. Stack layers.

The fourth insulation structure I4 is located on the transfer electrode 420 and the common electrode 430 .

The pixel electrode 410 is located on the four-insulation structure I4. The pixel electrode 410 fills the through hole in the fourth insulation structure I4 and contacts the transfer electrode 420.

FIG. 5 is a schematic cross-sectional view of a pixel structure according to an embodiment of the present invention. It must be noted here that the embodiment of Figure 5 follows the elements of the embodiment of Figure 5 Part numbers and part of the content, the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

Please refer to FIG. 5 . In this embodiment, the thin film transistor T1 further includes a first top gate TG1 . The thin film transistor T2 also includes a second top gate TG2.

In this embodiment, the second insulation structure I2 includes a gate insulation layer I2a and an interlayer dielectric layer I2b. The gate insulating layer I2a is located on the polysilicon layer 200A and the polysilicon layer 200B.

The first top gate TG1 and the second top gate TG2 are located on the gate insulating layer I2a, where the first top gate TG1 overlaps the polysilicon layer 200A and the first metal pattern 120A in the normal direction ND, and the second top gate TG1 The gate TG2 overlaps the polysilicon layer 200B and the second metal pattern 120B in the normal direction ND.

In some embodiments, the thin film transistor T1 and the thin film transistor T2 are both dual-gate thin film transistors, in which the first metal pattern 120A and the first top gate TG1 are electrically connected to each other, and the second metal pattern 120B is electrically connected to each other. The second top gates TG2 are electrically connected to each other. In other embodiments, the thin film transistor T1 and the thin film transistor T2 are both top-gate thin film transistors, in which the first metal pattern 120A and the second metal pattern 120B are both light-shielding structures. When the first metal pattern 120A and the second metal pattern 120B are light-shielding structures, the first metal pattern 120A and the second metal pattern 120B may be a floating structure.

The interlayer dielectric layer I2b is located on the gate insulating layer I2a, the first top gate TG1 and the second top gate TG2. Source 320A, drain 330A, source 320B, The drain electrode 330B and the common signal line 340 are located on the interlayer dielectric layer I2b.

Figure 6 is a scanning electron microscope photograph of a polycrystalline silicon layer according to an embodiment of the present invention. For example, after the polycrystalline silicon layer 200 is formed using the process of FIGS. 2A to 2E , the surface of the polycrystalline silicon layer 200 is photographed using an electron microscope. It can be seen from FIG. 6 that the polycrystalline silicon layer 200 includes grains with a grain length L″ greater than 400 Angstroms. In addition, in FIG. 6 , a dotted line is used to illustrate the boundary line corresponding to the first side and the second side of the conductive structure. position, it can be known from Figure 6 that when the cross-sectional shape of the conductive structure is a triangle, at the position corresponding to the intersection line between the first side and the second side, the boundaries of the grains of the polycrystalline silicon layer will be connected to each other to form a nearly straight line. .

7A is a scanning electron microscope photograph of a first metal pattern, a first insulating structure and a polycrystalline silicon layer according to an embodiment of the present invention. 7B is a transmission electron microscope photograph of a first metal pattern, a first insulating structure and a polycrystalline silicon layer according to an embodiment of the present invention.

Please refer to FIGS. 7A and 7B . In this embodiment, the first metal pattern only includes a single conductive structure 122 , and the conductive structure 122 is triangular. In addition, in this embodiment, the first insulating structure I1 includes a silicon oxide layer I1a located on the conductive structure 122 and a silicon nitride layer I1b located on the silicon oxide layer I1a. The polysilicon layer 200 is located on the silicon nitride layer I1b.

8A to 8C are transmission electron microscopy photos of the first metal pattern formed using different etching parameters. It can be known from FIGS. 8A to 8C that by adjusting the etching parameters, the angle θ between the side surface and the bottom surface of the first metal pattern 120 (or conductive structure) can be changed. When the first metal pattern 120 (or conductive structure) The slower the angle θ between the side surface and the bottom surface, the longer the length of the side surface of the first metal pattern 120 (or the conductive structure).

Figures 9A to 9E are transmission electron microscopy photos of polycrystalline silicon layers formed using excimer laser annealing processes with different energies. Below the polycrystalline silicon layer shown in FIGS. 9A to 9E , there is a first insulating structure (please refer to FIG. 1B and its related description) and a first conductive structure with a triangular cross-sectional shape (please refer to FIG. 1B and its related description). The energies of the excimer laser annealing processes used in Figures 9A, 9B, 9C, 9D and 9E are 400mJ/cm ² , 410mJ/cm ² , 420mJ/cm ² , 430mJ/cm ² and 440mJ/cm respectively. ² . Figure 10 is an experimental data diagram showing the energy of the excimer laser annealing process and the grain length of the polycrystalline silicon layer. It can be seen from Figure 9A that through the design of the first metal pattern of the present invention, as long as the energy of the excimer laser annealing process is adjusted to 400mJ/cm ² , the polycrystalline silicon layer can contain grains with a grain length greater than 400 Angstroms. . In addition, it can be known from FIGS. 9A to 9E and FIG. 10 that the higher the energy used in the excimer laser annealing process, the longer the grain length of the grains in the polycrystalline silicon layer. However, when the energy used in the excimer laser annealing process is too high, such as higher than 440mJ/cm ² as shown in Figure 9E, the polycrystalline silicon layer is easily damaged due to the high energy.

In summary, through the design of the first metal pattern of the present invention, gravity can be used to increase the grain length of the crystal grains in the polycrystalline silicon layer during the excimer laser annealing process. Therefore, there is no need to use the excimer laser annealing process. By adjusting the energy to a high level, a sufficiently long grain length can be obtained, thereby increasing the carrier mobility in the polycrystalline silicon layer.

120: First metal pattern

122:Conductive structure

122a: first side

122b: Second side

122c: Bottom surface

200:Polycrystalline silicon layer

210: Passage area

222: First lightly doped region

224: The second lightly doped region

232: First heavily doped region

234: The second heavily doped region

200a: first inclined part

200b: Second inclined part

320:Source

330:Jiji

400: Pixel electrode

D1: first direction

h: Thickness

I1: First insulation structure

I2: Second insulation structure

I3: The third insulation structure

L, L’: length

ND: normal direction

P: pitch

SB:Substrate

T1: thin film transistor

θ1, θ2: angle

Claims (11)

A thin film transistor, including: a first metal pattern, located on a substrate, wherein the angle between at least one side surface of the first metal pattern and the bottom surface of the first metal pattern is 10 degrees to 35 degrees; an insulation A structure is conformally formed on the first metal pattern; a polycrystalline silicon layer is conformally formed on the insulating structure and overlaps the first metal pattern, wherein the polycrystalline silicon layer includes crystals with a grain length greater than 400 angstroms. particles, wherein the first metal pattern includes a plurality of conductive structures, the angle between a first side and the bottom surface of each conductive structure is 10 degrees to 35 degrees; and a source electrode and a drain electrode are electrically connected to the Polycrystalline silicon layer. The thin film transistor according to claim 1, wherein the cross-sectional shape of each conductive structure includes a triangle. The thin film transistor of claim 1, wherein the cross-sectional shape of each conductive structure includes a trapezoid, and the length of the top surface of each conductive structure is less than or equal to 0.5 microns. The thin film transistor of claim 1, wherein each conductive structure includes the bottom surface, the first side surface and a second side surface, and the polycrystalline silicon layer includes a plurality of first inclined portions and overlapping portions overlapping the first side surfaces. On the plurality of second inclined portions on the second side surfaces, the length of each first inclined portion is greater than the length of each of the first side surfaces. The thin film transistor according to claim 4, wherein the first inclined portions and the second inclined portions are arranged alternately. The thin film transistor of claim 4, wherein the polycrystalline silicon layer further includes a plurality of platform portions, each first inclined portion and the corresponding second inclined portion are located on both sides of the corresponding platform portion, and each of the platform portions Length is 0.1 micron to 1 micron. The thin film transistor according to claim 1, wherein the thickness of the insulating structure is h, 3000Å

h

8000Å. The thin film transistor of claim 1, wherein the insulating structure includes a stack of silicon nitride and silicon oxide. The thin film transistor of claim 1, further comprising: a gate insulating layer located on the polycrystalline silicon layer; and a top gate located on the gate insulating layer and overlapping the polycrystalline silicon layer and the first Metallic pattern. A thin film transistor includes: a first metal pattern located on a substrate, wherein the cross-sectional shape of the first metal pattern includes at least one triangle; an insulating structure formed on the first metal pattern; a polycrystalline silicon layer, Formed on the insulating structure and overlapping the first metal pattern, the polycrystalline silicon layer includes grains with a grain length greater than 400 Angstroms; and a source electrode and a drain electrode are electrically connected to the polycrystalline silicon layer. The thin film transistor of claim 10, wherein the first metal pattern includes a plurality of conductive structures, the cross-sectional shape of each conductive structure includes a triangle, and the angle between a first side surface and the bottom surface of each conductive structure is 10 degrees to 35 degrees.