TWI823503B - Silicon chip edge roughness detection fixture and detection method - Google Patents

Abstract

Embodiments of the present invention provide a silicon wafer edge roughness detection fixture and a detection method. The silicon wafer edge roughness detection fixture includes: a base for carrying a silicon wafer sample. The base includes a horizontal bottom surface and a horizontal bottom surface. An inclined bearing surface with a preset angle α between the bottom surfaces, 0<α≤90°; and a clamping component for clamping and fixing the silicon wafer sample, the clamping component is arranged on the inclined bearing surface. The silicon wafer edge roughness detection fixture and detection method provided by embodiments of the present invention can analyze the roughness and surface morphology of the silicon wafer edge, reduce measurement errors, and ensure test reliability.

Description

Silicon chip edge roughness detection fixture and detection method

The invention belongs to the field of semiconductor processing technology, and in particular relates to a silicon chip edge roughness detection jig and detection method.

In recent years, the demand for large-diameter silicon wafers has increased dramatically, and issues related to the edges of silicon wafers have received widespread attention in semiconductor production. In the processing and production of silicon wafers, there are two main problems at the edges of silicon wafers: one is that the silicon wafers break due to micro-nicks and cracks caused by corrosion; the other is that dust particles and foreign matter adhere to the edges of the silicon wafers. These two problems often lead to a reduction in wafer yield during the wafer manufacturing process, so it is crucial to have a smooth, defect-free surface at the edge of the silicon wafer.

In related technologies, Atomic Force Microscope (AFM) is used to detect the surface roughness of silicon wafers. However, this method can only detect the roughness of the silicon wafer surface and cannot detect the roughness and edge roughness of the silicon wafer edges. Check the edge surface condition.

Embodiments of the present invention provide a silicon wafer edge roughness detection fixture and detection method, which can analyze the roughness and surface morphology of the silicon wafer edge, reduce measurement errors, and ensure test reliability.

90°；及，用於夾持固定該矽片樣品的夾持部件，該夾持部件設置於該傾斜承載面上。 The technical solutions provided by the embodiments of the present invention are as follows: A silicon wafer edge roughness detection fixture of the present invention includes: a base for carrying a silicon wafer sample. The base includes a horizontal bottom surface and a predetermined distance between the horizontal bottom surface and the horizontal bottom surface. Assume an inclined bearing surface with an included angle α, 0<α

90°; and, a clamping component used to clamp and fix the silicon wafer sample, the clamping component is arranged on the inclined bearing surface.

Exemplarily, the silicon wafer sample includes an edge chamfer, and opposite first and second surfaces. On a cross-section perpendicular to the first surface, the edge chamfer includes an outermost vertex O, passing through the outermost vertex The tangent line of O is perpendicular to the first surface, and the vertical distance between the intersection point a of the first surface and the edge chamfer structure and the tangent line passing through the outermost vertex O is A1, and the second surface and the edge chamfer structure The vertical distance between the intersection point b and the tangent line passing through the outermost vertex O is A2, the vertical distance between the outermost vertex O of the edge chamfer structure and the first surface is B1, and the vertical distance between the outermost vertex O and the second surface is B1. The vertical distance is B2; where the preset angle α and the edge chamfer of the silicon wafer sample satisfy the following relationship: tanα=B1/A1 or tanα=B2/A2.

Exemplarily, the clamping component adopts an integrated structure made of elastically deformable material.

Exemplarily, the clamping component includes a first part perpendicular to the inclined bearing surface and a second part connected to the first part and parallel to the inclined bearing surface. The first part, the second part and the inclined bearing surface are A clamping groove is formed by cooperation, and the notch of the clamping groove faces the side with the highest horizontal position in the inclined bearing surface.

Exemplarily, the second part is provided with an arc-shaped guide surface at the clamping entrance of the clamping groove.

For example, the base is made of hard material that is not easily deformed.

Embodiments of the present invention also provide a method for detecting edge roughness of silicon wafers, including: Cut a silicon wafer sample on the edge of the silicon wafer to be detected, and the silicon wafer sample includes at least a part of the edge of the silicon wafer to be detected and a part of the surface of the silicon wafer sample to be detected; clamp and fix the silicon wafer sample on the On the silicon wafer edge roughness detection jig provided by the embodiment of the invention, the edge of the silicon wafer sample and the surface of the silicon wafer sample are at least partially not blocked by the clamping component; the silicon wafer edge roughness detection jig is placed On the sample stage of the atomic force display mirror, the area to be detected at the edge chamfer of the silicon wafer sample is kept level with the sample stage; the area to be detected is scanned by the probe of the atomic force microscope to obtain a test image; The test image is processed to obtain the edge roughness value of the silicon wafer and the edge morphology of the silicon wafer.

Exemplarily, cutting a silicon wafer sample at a predetermined position on the edge of the silicon wafer to be detected specifically includes: dividing the edge of the silicon wafer to be detected into N detection points evenly and sequentially along the circumference of the silicon wafer to be detected, A silicon wafer sample is cut at each detection point, and the N silicon wafer samples are marked with serial numbers in sequence.

For example, the size of each silicon wafer sample is 1cm×1cm.

The beneficial effects brought by the embodiments of the present invention are as follows: the silicon wafer edge roughness detection jig and detection method provided by the embodiments of the present invention design a special silicon wafer edge roughness detection jig, which can detect the silicon wafer edge roughness. After cutting the silicon wafer sample from the edge, place the silicon wafer sample on the jig so that the edge of the silicon wafer sample to be detected remains horizontal, so that the roughness and surface morphology of the silicon wafer edge can be measured using an atomic force microscope. Analyze and reduce measurement errors to ensure test reliability.

100: base

110: Horizontal bottom

120: Inclined bearing surface

200: Clamping parts

210:Part One

220:Part 2

221: Arc guide surface

230: Clamping slot

10:Silicon wafer sample

10a: Incline

11: Edge chamfering

12: First surface

13: Second surface

Figure 1 shows a schematic structural diagram of a silicon wafer edge roughness detection fixture provided in an embodiment of the present invention; Figure 2 shows a schematic diagram of the cross-sectional morphology at the edge of a silicon wafer sample; Figure 3 shows the edge of a silicon wafer provided in an embodiment of the present invention A schematic structural diagram of a silicon wafer sample carried on a roughness detection jig; Figure 4 shows a schematic diagram of one embodiment of cutting a silicon wafer sample in the silicon wafer edge roughness detection method provided in the embodiment of the present invention; Figure 5 shows the implementation of the present invention A schematic diagram of another implementation of cutting a silicon wafer sample in the silicon wafer edge roughness detection method provided in the example; Figure 6 shows another implementation of cutting a silicon wafer sample in the silicon wafer edge roughness detection method provided in the embodiment of the present invention. Schematic diagram of the method.

In order to help the review committee understand the technical features, content and advantages of the present invention and the effects it can achieve, the present invention is described in detail below in the form of embodiments with the accompanying drawings and attachments, and the drawings used therein are , its purpose is only for illustration and auxiliary description, and may not represent the actual proportions and precise configurations after implementation of the present invention. Therefore, the proportions and configuration relationships of the attached drawings should not be interpreted or limited to the actual implementation of the present invention. The scope shall be stated first.

In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical" ", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience and simplicity in describing the embodiments of the present invention. describe, rather than indicate or imply It is intended that devices or elements must have a specific orientation, be constructed and operate in a specific orientation and therefore are not to be construed as limitations of the invention.

In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, features defined as “first” and “second” may explicitly or implicitly include one or more of the described features. In the description of the embodiments of the present invention, "plurality" means two or more than two, unless otherwise explicitly and specifically limited.

In the embodiments of the present invention, unless otherwise expressly stipulated and limited, the terms "installation", "connection", "connection", "fixing" and other terms should be understood in a broad sense. For example, it can be a fixed connection or a removable connection. Disassembly and connection, or integration; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interaction between two elements. For those with ordinary knowledge in the art, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

Before describing the embodiments of the present invention in detail, it is necessary to make the following description of the related technology: In the related technology, the edge polishing of the silicon wafer is to remove the remaining corrosion pits on the edge of the silicon wafer, smooth the edge, and make the silicon wafer more beautiful. Strong, polished edges can minimize particle adsorption to ensure processing accuracy and high yield on the edge surface of silicon wafers. In the processing technology of silicon wafer edge surface polishing, mechanical belt-type edge rough polishing is first performed, and then the edge surface is finely polished by alkaline colloidal silica chemical mechanical polishing.

During the processing of silicon wafers and the manufacturing of semiconductor devices, there are some very rapid heating and cooling processes, so it is easier for thermal stress to concentrate in the edge areas of the silicon wafers. Once this thermal stress exceeds the limit of the silicon crystal itself, the crystal will produce defects such as dislocations and dislocations. Therefore, it is particularly important to measure and evaluate the edge roughness and surface of silicon wafers.

However, among related technologies, for the measurement of surface roughness of silicon wafers, the most widely recognized one is the atomic force microscope (AFM), which is mainly used to monitor the surface roughness of silicon wafers. However, there is no method for measuring the surface roughness of silicon wafers. Detection of edge roughness and edge surface condition.

In order to detect the edge roughness and edge surface state of the silicon wafer, embodiments of the present invention provide a silicon wafer edge roughness detection jig and a detection method, which can analyze the roughness and surface morphology of the silicon wafer edge, and can Reduce measurement errors and ensure test reliability.

1 and 3 are schematic structural diagrams of a silicon wafer edge roughness detection jig provided by an embodiment of the present invention.

90°，該夾持部件200用於夾持固定該矽片樣品10，該夾持部件200設置於該傾斜承載面120上。 As shown in Figures 1 and 3, the silicon wafer edge roughness detection fixture includes: a base 100 and a clamping component 200. The base 100 is used to carry the silicon wafer sample 10. The base 100 includes a horizontal bottom surface 110 and The inclined bearing surface 120 forms a preset angle α with the horizontal bottom surface 110, 0<α

90°, the clamping component 200 is used to clamp and fix the silicon wafer sample 10, and the clamping component 200 is disposed on the inclined bearing surface 120.

Since the edge of the silicon wafer is usually chamfered, if the silicon wafer sample 10 is placed directly on the sample stage of the atomic force microscope, due to the chamfering of the edge of the silicon wafer, the part to be detected on the edge will be a bevel 10a, causing the atomic force microscope to The probe cannot accurately scan the bevel, and therefore cannot obtain accurate test images. Therefore, in the embodiment of the present invention, a special silicon wafer edge roughness detection fixture is designed, which mainly includes two parts: a base 100 and a clamping component 200. When the silicon wafer sample 10 is loaded on the inclined bearing surface 120 of the base 100 By doing so, the bevel at the edge of the silicon wafer sample 10 can be kept level with the horizontal base, so that the probe of the atomic force microscope can accurately scan the bevel 10a, thereby obtaining accurate test images.

As shown in FIG. 2 , the silicon wafer sample 10 includes an edge chamfer 11 and opposite first and second surfaces 12 and 13 . In a cross section perpendicular to the first surface 12 , the edge chamfer 11 includes an outermost edge chamfer 11 . At vertex O, the tangent line passing through the outermost vertex O is perpendicular to the first surface 12, and the vertical distance between the intersection point a of the first surface 12 and the edge chamfer 11 structure and the tangent line passing through the outermost vertex O is A1 , the vertical distance between the intersection point b of the second surface 13 and the edge chamfer 11 structure and the tangent line passing through the outermost vertex O is A2, and the distance between the outermost vertex O of the edge chamfer 11 structure and the first surface 12 The vertical distance between is B1, and the vertical distance between the second surface 13 and the second surface 13 is B2; wherein, the preset angle α is equal to β1 or β2; that is, the preset angle α and the edge of the silicon wafer sample 10 The following relationship should be satisfied between chamfers 11: tanα=B1/A1 or tanα=B2/A2.

Using the above solution, as shown in Figure 3, when the silicon wafer sample 10 is carried on the inclined bearing surface 120, due to the inclination angle of the inclined bearing surface 120 and the slope on the edge chamfer 11 of the silicon wafer sample 10 The angles are complementary, so that the portion to be detected at the edge chamfer 11 on the final silicon wafer sample 10, that is, the bevel at the chamfer can remain level.

It should be noted that in some embodiments, the inclined bearing surface 120 of the base 100 may have a fixed inclination angle, or the inclined bearing surface 120 of the base 100 may be designed to have an inclination angle according to actual product requirements. tone structure.

In addition, in some exemplary embodiments, the base 100 can be made of hard non-deformable material, and the clamping component 200 can be made of an integral structure made of elastically deformable material.

Specifically, in one embodiment, as shown in FIGS. 1 and 3 , the clamping component 200 includes a first part 210 perpendicular to the inclined bearing surface 120 , and a first part 210 connected to the first part 210 and parallel to the inclined bearing surface 120 the second part 220, the first part 210, the second part 220 and the inclined bearing surface 120 A clamping groove 230 is formed in cooperation, and the notch of the clamping groove 230 faces the side with the highest horizontal position in the inclined bearing surface 120 .

In the above solution, the clamping component 200 is made of elastically deformable material, and the first part 210 and the second part 220 are generally connected to form an L-shaped structure, and cooperate with the inclined bearing surface 120 to form a clamping groove 230. The opening width of the clamping groove 230, that is, the distance between the second part 220 and the inclined bearing surface 120, can be slightly smaller than the thickness between the first surface 12 and the second surface 13 of the silicon wafer sample 10. In this way, the silicon wafer sample 10 can be inserted into the clamping groove 230, and the silicon chip sample 10 is clamped and fixed through the elastic deformation of the second part 220.

In some embodiments, the second part 220 is provided with an arc-shaped guide surface 221 at the clamping entrance of the clamping groove 230 , which facilitates the silicon wafer sample 10 to enter the clamping groove 230 .

It should be noted that the fact that the first part 210 is perpendicular to the inclined bearing surface 120 here means that the first part 210 is substantially perpendicular to the inclined bearing surface 120. For example, the angle between the first part 210 and the inclined bearing surface 120 is 90°. °±10°, here the parallel between the second part 220 and the inclined bearing surface 120 means that the second part 220 and the inclined bearing surface 120 are substantially parallel, for example, the distance between the second part 220 and the inclined bearing surface 120 The angle is 0±10°.

The clamping structure in the above solution uses elastically deformable material, and uses the first part 210 and the second part 220 to form an L-shaped structure to clamp the silicon wafer sample 10, which can not damage the silicon wafer sample 10 on the one hand, and maintain the The surface of the silicon chip sample 10 is parallel to the inclined bearing surface 120 .

Of course, it can be understood that the specific structure of the clamping component 200 is not limited to this. As long as the silicon wafer sample 10 can be clamped and the silicon wafer sample 10 is not damaged, any structure can be applied.

In addition, embodiments of the present invention also provide a method for detecting edge roughness of silicon wafers, including: step S01, cutting a silicon wafer sample 10 on the edge of the silicon wafer to be detected, and the silicon wafer sample 10 at least includes the silicon wafer to be detected A part of the edge and a part of the surface of the silicon wafer sample to be detected; step S02, clamp and fix the silicon wafer sample 10 on the silicon wafer edge roughness detection jig provided by the embodiment of the present invention, wherein the silicon wafer sample 10 The edge of the silicon wafer sample 10 and the surface of the silicon wafer sample 10 are at least partially not blocked by the clamping component 200; step S03, place the silicon wafer edge roughness detection jig on the sample stage of the atomic force display mirror, wherein the silicon wafer sample 10 The area to be detected at the edge chamfer 11 is kept level with the sample stage; Step S04, scan the area to be detected through the probe of the atomic force microscope to obtain a test image; Step S05, process the test image, The edge roughness value of the silicon wafer and the edge morphology of the silicon wafer were obtained.

In the above scheme, a silicon wafer sample 10 is cut on the edge of the silicon wafer, and at least part of the edge and at least part of the surface are retained on the silicon wafer sample 10 to facilitate analysis of the edge roughness and edge morphology of the silicon wafer; and then through this The special silicon wafer edge detection fixture provided by the embodiment of the invention is used to perform atomic force microscopy inspection on the silicon wafer sample 10, and the slope of the part to be detected at the edge of the silicon wafer sample 10 is kept level, so as to realize the edge roughness and edge detection of the silicon wafer. Accurate detection of morphology.

In some embodiments, the above step S01 specifically includes: dividing the edge of the silicon wafer to be detected into N detection points evenly along the circumference of the silicon wafer to be detected, and cutting a silicon wafer sample 10 at each detection point, The N silicon wafer samples 10 are sequentially marked with serial numbers.

For example, as shown in Figure 4, the edge of the silicon wafer to be detected is evenly divided into 4 detection points along the circumference, and a silicon wafer sample 10 is cut at each detection point to obtain 4 silicon wafer samples 10. For the four silicon wafers, Sample 10 is sorted in sequence, sample No. 1, sample No. 2, sample No. 3 and sample No. 4, and then 4 Each sample is placed on the jig in turn, and the test image is obtained through an atomic force microscope to obtain the edge roughness and edge morphology analysis of the silicon wafer to be detected.

For example, as shown in Figure 5, the four detection points in Figure 5 are selected at different positions than the four detection points in Figure 4. Figure 5 also shows that the edge of the silicon wafer to be detected is evenly divided into four detection points along the circumference. , cut a silicon wafer sample 10 at each detection point to obtain 4 silicon wafer samples 10. Sort the four silicon wafer samples 10 in sequence, sample No. 1, sample No. 2, sample No. 3 and sample No. 4 , and then place the four samples on the jig in sequence, and obtain the test image through the atomic force microscope, thereby obtaining the edge roughness and edge morphology analysis of the silicon wafer to be detected.

For example, as shown in Figure 6, the edge of the silicon wafer to be detected is evenly divided into 8 detection points along the circumference, and a silicon wafer sample 10 is cut at each detection point to obtain 8 silicon wafer samples 10. For four silicon wafer samples, Samples 10 are sorted in sequence, sample No. 1, sample No. 2, sample No. 3, sample No. 4, sample No. 5, sample No. 6, sample No. 7 and sample No. 8, and then pass through the 8 Each sample is placed on the jig in turn, and the test image is obtained through an atomic force microscope to obtain the edge roughness and edge morphology analysis of the silicon wafer to be detected.

It should be noted that the above are only examples. In actual applications, the silicon wafer sample 10 can be cut from the edge of the silicon wafer to be detected according to different testing requirements.

In some embodiments, the dimensions of each silicon wafer sample 10 are approximately 1 cm x 1 cm. Of course it is not limited to this.

The following points need to be explained: (1) The drawings of the embodiments of the present invention only relate to the structures related to the embodiments of the present invention, and other structures can refer to common designs; (2) For the sake of clarity, in the drawings used to describe embodiments of the present invention, the thicknesses of layers or regions are exaggerated or reduced, that is, these drawings are not drawn according to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element Or there may be intermediate elements; (3) Without conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other to obtain new embodiments.

The above are only preferred embodiments of the present invention and are not intended to limit the implementation scope of the present invention. If the present invention is modified or equivalently substituted without departing from the spirit and scope of the present invention, the protection shall be covered by the patent scope of the present invention. within the range.

100: base

110: Horizontal bottom

120: Inclined bearing surface

200: Clamping parts

210:Part One

220:Part 2

221: Arc guide surface

230: Clamping slot

Claims (9)

A silicon chip edge roughness detection fixture, including: A base for carrying silicon wafer samples. The base includes a horizontal bottom surface and an inclined bearing surface with a preset angle α between the horizontal bottom surface and the horizontal bottom surface, 0＜α≤90°; and, used for clamping and fixing the silicon wafer. The clamping component of the sample is arranged on the inclined bearing surface. The silicon wafer edge roughness detection fixture according to claim 1, wherein the silicon wafer sample includes edge chamfers, and opposite first and second surfaces. On a cross-section perpendicular to the first surface, the The edge chamfering includes the outermost vertex O, the tangent passing through the outermost vertex O is perpendicular to the first surface, and the intersection point a of the first surface and the edge chamfering structure is perpendicular to the tangent passing through the outermost vertex O. The distance is A1, the vertical distance between the intersection point b of the second surface and the edge chamfer structure and the tangent line passing through the outermost vertex O is A2, and the distance between the outermost vertex O of the edge chamfer structure and the first surface is The vertical distance to the second surface is B1, and the vertical distance to the second surface is B2; where the preset angle α and the edge chamfer of the silicon wafer sample satisfy the following relationship: tanα=B1/A1 or tanα=B2 /A2. The silicon chip edge roughness detection fixture according to claim 1, wherein the clamping component adopts an integrated structure made of elastically deformable material. The silicon chip edge roughness detection fixture according to claim 3, wherein the clamping component includes a first part perpendicular to the inclined bearing surface, and a second part connected to the first part and parallel to the inclined bearing surface. , the first part and the second part cooperate with the inclined bearing surface to form a clamping groove, and the notch of the clamping groove faces the side with the highest horizontal position in the inclined bearing surface. The silicon chip edge roughness detection jig according to claim 4, wherein the second part is provided with an arc-shaped guide surface at the clamping entrance of the clamping groove. The silicon chip edge roughness detection fixture as described in claim 1, wherein the base is made of hard and non-deformable material. A method for detecting edge roughness of silicon wafers, including: Cutting a silicon wafer sample on the edge of the silicon wafer to be detected, the silicon wafer sample includes at least a part of the edge of the silicon wafer to be detected and a part of the surface of the silicon wafer sample to be detected; The silicon wafer sample is clamped and fixed on the silicon wafer edge roughness detection fixture as described in any one of claims 1 to 6, wherein at least part of the edge of the silicon wafer sample and the surface of the silicon wafer sample are not The clamping part is blocked; The silicon wafer edge roughness detection fixture is placed on the sample stage of the atomic force display mirror, wherein the area to be detected at the edge chamfer of the silicon wafer sample is kept level with the sample stage; Scan the area to be detected with the probe of an atomic force microscope to obtain a test image; The test image is processed to obtain the edge roughness value of the silicon wafer and the edge morphology of the silicon wafer. The silicon wafer edge roughness detection method as described in claim 7, wherein the silicon wafer sample is cut at a predetermined position on the edge of the silicon wafer to be detected, specifically including: The edge of the silicon chip to be detected is evenly divided into N detection points along the circumference of the silicon chip to be detected. A silicon chip sample is cut at each detection point, and the N silicon chip samples are sequentially marked with serial numbers. The silicon wafer edge roughness detection method as described in claim 8, wherein the size of each silicon wafer sample is 1cm × 1cm.