TWI818465B - 多層印刷電路板結構 - Google Patents
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 115
- 239000002184 metal Substances 0.000 claims abstract description 115
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 230000017525 heat dissipation Effects 0.000 abstract description 9
- 238000002955 isolation Methods 0.000 abstract description 4
- 238000012545 processing Methods 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 230000005540 biological transmission Effects 0.000 abstract description 2
- 238000005476 soldering Methods 0.000 description 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/062—Means for thermal insulation, e.g. for protection of parts
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0969—Apertured conductors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09854—Hole or via having special cross-section, e.g. elliptical
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Abstract
本發明係一種多層印刷電路板結構,包括一底層金屬、複數中間金屬層及一頂層金屬,各中間金屬層依序疊設在底層金屬上,頂層金屬設置於各中間金屬層上,頂層金屬、各中間金屬層及底層金屬皆貫穿設有複數導通孔,部份中間金屬層分別設有對應各導通孔的複數槽孔組,每一槽孔組包括複數通槽,且各通槽共同圍繞相對應的導通孔而分隔出複數連接通道;藉此多層印刷電路板可在保有高頻傳輸及訊號隔離的同時,減緩導通孔的散熱速率以避免焊盤溫度過低而影響銲錫加工的效率。
Description
本發明係有關於一種電路板,尤指一種能夠減緩焊盤的散熱速率以提升焊錫加工效率的多層印刷電路板結構。
隨著印刷電路板(Printed circuit board,PCB)及電子元件等製程技術的進步,印刷電路板的設計也逐漸邁向高速化及小型化,以符合現行電子產品的高效輕薄需求。故為了減少印刷電路板的尺寸,多層印刷電路板的佈局設計相應被提出以增加可佈線的面積。
且一般為了避免高頻訊號間產生串音干擾,大多會在多層印刷電路板上打貫孔隔離訊號以降低影響。然而,在焊盤上慣孔的設計會使得後續在進行焊錫的加工作業時,焊盤的散熱速率過快而導致焊錫溫度不足,從而影響焊錫的加工效率及良率。
有鑑於此,本發明人遂針對上述現有技術的缺失,特潛心研究並配合學理的運用,盡力解決上述之問題點,即成為本發明人改良之目標。
本發明之主要目的,在於能夠讓多層印刷電路板保有高頻傳輸及訊號隔離的同時,減緩導通孔的散熱速率以避免焊盤溫度過低而影響銲錫加工的效率。
為了達成上述之目的,本發明提供一種多層印刷電路板結構,包括一底層金屬、複數中間金屬層及一頂層金屬,各中間金屬層依序疊設在底層金屬上,頂層金屬設置於各中間金屬層上,頂層金屬、各中間金屬層及底層金屬皆貫穿設有複數導通孔,該些中間金屬層分別設有對應各導通孔的複數槽孔組,每一槽孔組包括複數通槽,且各通槽共同圍繞相對應的導通孔而分隔出複數連接通道。
本發明還具有以下功效:藉由頂層金屬、各中間金屬層及底層金屬皆貫穿設有複數導通孔,可產生訊號隔離以降低高頻訊號間的串音干擾。透過導通孔周圍的各通槽,能夠減少導通孔周圍的傳導面積而減緩散熱速率,以避免焊盤的溫度過低並方便的銲錫加工作業。藉由調整槽孔組中通槽及連接通道的數量,可對應增加或減緩導通孔周圍的散熱速率。
10:底層金屬
11、31:金屬接腳
12、22、32:導通孔
20:中間金屬層
21:槽孔組
211:通槽
212:連接通道
23:讓位槽
30:頂層金屬
40:基材
50:導電銅柱
L1:第一中間金屬層
L2:第二中間金屬層
L3:第三中間金屬層
L4:第四中間金屬層
圖1 係本發明第一實施例之立體分解圖。
圖2 係本發明第一實施例中間金屬層之立體外觀圖。
圖3 係本發明第一實施例之剖視圖。
圖4 係本發明第一實施例之立體外觀圖。
圖5 係本發明第二實施例之立體分解圖。
圖6 係本發明第一實施例槽孔組之俯視圖。
圖7 係本發明第三實施例槽孔組之俯視圖。
圖8 係本發明第四實施例槽孔組之俯視圖。
圖9 係本創作第五實施例槽孔組之俯視圖。
有關本發明之詳細說明及技術內容,將配合圖式說明如下,然而所附圖式僅作為說明用途,並非用於侷限本發明。
本發明係提供一種多層印刷電路板結構,請參照圖1至圖4所示,其主要包括一底層金屬10、複數中間金屬層20及一頂層金屬30。
底層金屬10、各中間金屬層20及頂層金屬30等各金屬層係以鋁、鋼、銅、或鐵中的任一種金屬所製成,但本發明不以此為限。較佳地,以鋁、鋼或鐵所製成的金屬層還可進一步在表面批覆銅箔,從而增加導電效率。底層金屬10及頂層金屬30的表面分別設有複數金屬接腳11、31,從而方便與連接器(圖未示出)進行插拔接觸。
於本實施例中,中間金屬層20的數量為四,但本發明不以此為限,例如中間金屬層20的數量也可以為二、六、八或十個以上。具體而言,本實施例中的各中間金屬層20包括一第一中間金屬層L1、一第二中間金屬層L2、一第三中間金屬層L3及一第四中間金屬層L4。各中間金屬層20係依序由上而下地疊設在底層金屬10上,頂層金屬30則係設置於各中間金屬層20上,即頂層金屬30及底層金屬10係分別位於各中間金屬層20的上下兩側。
頂層金屬30、各中間金屬層20及底層金屬10皆貫穿設有複數導通孔12、22、32,藉以產生訊號隔離以降低高頻訊號間的串音干擾。於本實施例中,至少二相連的中間金屬層20設有各槽孔組21,即部分相連的各中間金屬層20分別設有對應各導通孔22的複數槽孔組21,但本發明不以此為限,請參閱圖5
之第二實施例,各槽孔組21也可以設置在全部的中間金屬層20上。復參閱圖1至圖4,本實施例中其餘的該些中間金屬層20中的二中間金屬層20分別設有一讓位槽23,且讓位槽23係覆蓋二中間金屬層20的各導通孔22。又,設有各讓位槽23的二中間金屬層20係分別相鄰於底層金屬10及頂層金屬30。具體而言,本實施例中的各槽孔組21係設置在第二中間金屬層L2及第三中間金屬層L3上,各讓位槽23則係分別設置在第一中間金屬層L1及第四中間金屬層L4上,但本發明不以此為限。
每一槽孔組21包括有複數通槽211,且各通槽211係共同圍繞相對應的導通孔22,從而分隔出複數連接通道212。於本實施例中,每一槽孔組21中的各通槽211係共同圍繞相對應的導通孔22而呈環狀排列,但本發明不以此為限。藉此能夠透過各通槽211來減少導通孔22周圍的傳導面積,從而減緩散熱速率以避免焊盤的溫度過低,並方便後續的銲錫加工作業。於本發明的第一實施例中,每一通槽211係概呈彎月形,但本發明不以此為限,例如每一通槽211也可以係概呈矩形、三角形、橢圓形、扇形或不規則形狀等,其中每一通槽211概呈矩形狀之示意請參閱圖9,而三角形、橢圓形、扇形或不規則形狀等則可依此類推,故不再於圖示中一一示出。
進一步說明,連接通道212的數量係對應通槽211的數量而定。請參閱圖6所示,於本實施例的每一槽孔組21中,通槽211的數量為四,且連接通道212的數量亦為四,但本發明不以此為限。請接著參閱圖7所示,係本發明之第三實施例,每一槽孔組21中通槽211的數量為二,且連接通道212的數量亦為二。請再參閱圖8所示,係本發明之第四實施例,每一槽孔組21中通槽211的數量為三,且連接通道212的數量亦為三。藉此,設計者可因應所需的散熱速率來對槽孔組21中通槽211及連接通道212的數量進行調整,從而增加或減緩導通孔12、22、32周圍的散熱速率。
又,請參閱圖3及圖4所示,本發明之多層印刷電路板結構還包括一基材40及複數導電銅柱50。於本實施例中,基材40係塑膠或其絕緣材料射出所一體成型,但本發明不以此為限。基材40係包覆各中間金屬層20並且連接底層金屬10及頂層金屬30,同時分隔底層金屬10、各中間金屬層20及頂層金屬30以避免各金屬層之間直接形成電性連接。各導電銅柱50係設置在各導通孔12、22、32內並由基材40所包覆,且各導電銅柱50分別和底層金屬10、頂層金屬30及設有槽孔組21的該些中間金屬層20形成電性連接,從而使底層金屬10及頂層金屬30上的各金屬接腳11、31和多層印刷電路板內部的銅箔形成導通。
綜上所述,本發明已具有產業利用性、新穎性與進步性,完全符合專利申請要件,爰依專利法提出申請。當然,本發明還可有其他多種實施例,在不背離本發明精神及其實質的情況下,熟悉本領域的技術人員當可根據本發明演化出各種相應的改變和變形,但這些相應的改變和變形都應屬於本發明所申請專利的保護範圍。
10:底層金屬
11、31:金屬接腳
12、22、32:導通孔
20:中間金屬層
21:槽孔組
23:讓位槽
30:頂層金屬
L1:第一中間金屬層
L2:第二中間金屬層
L3:第三中間金屬層
L4:第四中間金屬層
Claims (7)
- 一種多層印刷電路板結構,包括:一底層金屬;複數中間金屬層,依序疊設在該底層金屬上;及一頂層金屬,設置於各該中間金屬層上;其中該頂層金屬、各該中間金屬層及該底層金屬皆貫穿設有複數導通孔,至少二該中間金屬層分別設有對應各該導通孔的複數槽孔組,每一該槽孔組包括複數通槽,且各該通槽共同圍繞相對應的該導通孔而分隔出複數連接通道,其餘的該些中間金屬層中的二該中間金屬層分別設有一讓位槽,該讓位槽係覆蓋對應的該中間金屬層的各該導通孔,且設有各該讓位槽的該些中間金屬層係分別相鄰於該底層金屬及該頂層金屬。
- 如請求項1所述之多層印刷電路板結構,其中每一該通槽係概呈彎月形或矩形。
- 如請求項1所述之多層印刷電路板結構,其中每一該槽孔組中的各該通槽係圍繞相對應的該導通孔而呈環狀排列。
- 如請求項3所述之多層印刷電路板結構,其中每一該槽孔組的通槽數量為二,且連接通道的數量為二。
- 如請求項3所述之多層印刷電路板結構,其中每一該槽孔組的通槽數量為三,且連接通道的數量為三。
- 如請求項3所述之多層印刷電路板結構,其中每一該槽孔組的通槽數量為四,且連接通道的數量為四。
- 如請求項1所述之多層印刷電路板結構,其還包括複數導電銅柱,各該導電銅柱係設置在各該導通孔內,且各該導電銅柱分別和該底層金屬、該頂層金屬及設有各該槽孔組的該些中間金屬層電性連接。
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| Application Number | Priority Date | Filing Date | Title |
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| TW111109159A TWI818465B (zh) | 2022-03-14 | 2022-03-14 | 多層印刷電路板結構 |
| US17/829,319 US12213254B2 (en) | 2022-03-14 | 2022-05-31 | Multi-layer printed circuit board |
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| Application Number | Priority Date | Filing Date | Title |
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| TW111109159A TWI818465B (zh) | 2022-03-14 | 2022-03-14 | 多層印刷電路板結構 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20190200450A1 (en) * | 2016-09-19 | 2019-06-27 | Intel Corporation | Alternative circuit apparatus for long host routing |
| US20190208630A1 (en) * | 2016-02-16 | 2019-07-04 | Microsoft Technology Licensing, Llc | Laser diode chip on printed circuit board |
| TWM611951U (zh) * | 2021-02-18 | 2021-05-11 | 十銓科技股份有限公司 | 耐用型記憶體儲存裝置 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6646886B1 (en) * | 2002-04-12 | 2003-11-11 | Cisco Technology, Inc. | Power connection structure |
| JP4105148B2 (ja) * | 2004-12-10 | 2008-06-25 | 株式会社ケーヒン | プリント基板 |
| JP5369685B2 (ja) * | 2006-08-02 | 2013-12-18 | 日本電気株式会社 | プリント配線基板および電子機器 |
| WO2015116090A1 (en) * | 2014-01-30 | 2015-08-06 | Hewlett-Packard Development Company, L.P. | Thermal relief pad |
-
2022
- 2022-03-14 TW TW111109159A patent/TWI818465B/zh active
- 2022-05-31 US US17/829,319 patent/US12213254B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20190208630A1 (en) * | 2016-02-16 | 2019-07-04 | Microsoft Technology Licensing, Llc | Laser diode chip on printed circuit board |
| US20190200450A1 (en) * | 2016-09-19 | 2019-06-27 | Intel Corporation | Alternative circuit apparatus for long host routing |
| TWM611951U (zh) * | 2021-02-18 | 2021-05-11 | 十銓科技股份有限公司 | 耐用型記憶體儲存裝置 |
Also Published As
| Publication number | Publication date |
|---|---|
| US12213254B2 (en) | 2025-01-28 |
| US20230292437A1 (en) | 2023-09-14 |
| TW202337275A (zh) | 2023-09-16 |
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