TWI817871B - Reference voltage generating circuits, electronic chips and information processing devices - Google Patents

Abstract

The present invention mainly discloses a reference voltage generating circuit for integration into an integrated circuit chip, and includes: a bias current generating unit, a reference voltage generating unit and a voltage regulating unit, wherein the bias current generating unit The unit generates a bias current, so that the reference voltage generating unit generates a first reference voltage according to the bias current. According to the design of the present invention, the voltage adjustment unit is coupled to the reference voltage generation unit and the bias current generation unit, and is used to perform a voltage adjustment process on the first reference voltage, thereby generating an output voltage that is fed back to the bias current. Set up the current generating unit. Furthermore, the output voltage is supplied as a second reference voltage to other circuit units of the integrated circuit chip as a reference voltage. The advantage of the reference voltage generating circuit of the present invention is that it not only ensures that the output voltage has low temperature drift characteristics, but also effectively reduces the output offset voltage.

Description

Reference voltage generating circuits, electronic chips and information processing devices

The present invention relates to the technical field related to integrated circuits, and in particular, to a reference voltage generating circuit with low temperature drift and low input offset voltage drift characteristics.

It is known that integrated circuit chips such as microcontroller chips, driver chips, and SoC chips have been widely used in various electronic devices. Electronic engineers who are familiar with the design and production of integrated circuit chips must know that the integrated circuit chip contains a reference voltage circuit, which is used to provide a reference voltage that is independent of changes in ambient temperature for other circuits in the integrated circuit chip. The base voltage of the unit. Figure 1 is a circuit topology diagram of a conventional reference voltage circuit. As shown in Figure 1, the conventional reference voltage circuit 1a includes: an operational amplifier 11a, a first MOSFET element M1a, a second MOSFET element M2a, a first BJT element Q1a, a second BJT element Q2a, a first A resistor R1a, and a second resistor R2a. Electronic engineers familiar with the design and production of the reference voltage circuit 1a also know that due to the base-emitter voltage of the BJT component is inversely proportional to temperature and is directly proportional to the temperature, therefore, by and By superposing at a certain ratio, a reference voltage with low temperature drift characteristics can be obtained. .

Further, FIG. 2 is an internal circuit topology diagram of the operational amplifier 11a shown in FIG. 1 . As shown in Figure 2, the operational amplifier 11a generally includes: an input differential pair including a first N-type MOSFET element Mn1a and a second N-type MOSFET element Mn2a, a third MOSFET element M3a and a fourth MOSFET A current mirror of element M4a, and a current source 111a. Practical experience shows that the MOSFT device mismatch caused by process variations will also cause the input offset voltage of the operational amplifier 11a. ) drifts. Therefore, for the simultaneous fabrication of multiple integrated circuit dies on a single silicon wafer, the operational amplifiers 11a of the reference voltage circuit 1a inside any two integrated circuit dies may have different input offset voltages. Similarly, two operational amplifiers 11a fabricated on two different silicon wafers may also have different input offset voltages. Therefore, during normal operation, the operational amplifier 11a ) will be amplified by the circuit and finally superimposed on the reference voltage above, resulting in a reference voltage The output offset voltage is difficult to remove. It can be seen from the foregoing description that when designing and manufacturing the reference voltage circuit 1a, in addition to the temperature drift problem, it is also necessary to further consider the temperature drift of the operational amplifier 11a caused by the drift of the process parameters. The problem of drift.

From the above description, it can be seen that a new type of reference voltage generating circuit is urgently needed in this field.

The main purpose of the present invention is to provide a reference voltage generating circuit, which has the following advantages: ensuring that the output voltage has low temperature drift characteristics and effectively reducing the output offset voltage at the same time.

To achieve the above object, the present invention proposes an embodiment of the reference voltage generating circuit, which includes: a bias current generating unit, used to generate a bias current; a reference voltage generating unit coupled to the bias current generating unit and generating a first reference voltage based on the bias current; and A voltage adjustment unit is coupled to the reference voltage generation unit and the bias current generation unit, and is used to perform a voltage adjustment process on the first reference voltage, thereby generating an output voltage that is fed back to the bias current generation unit.

In one embodiment, the bias current generating unit includes: A first operational amplifier having a positive input terminal, a negative input terminal and an output terminal, and the negative input terminal is coupled to the output voltage; A first P-type MOSFET component has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the output terminal of the first operational amplifier, and the source terminal is coupled to an operating voltage; and a first resistor, a first end and a second end of which are respectively coupled to the drain terminal and a ground terminal of the first P-type MOSFET component; Wherein, the positive input terminal of the first operational amplifier is coupled to a first common node between the first terminal of the first resistor and the drain terminal of the first P-type MOSFET element.

In one embodiment, the reference voltage generating unit includes: A second P-type MOSFET component has a gate terminal, a drain terminal and a source terminal, wherein the source terminal is coupled to the operating voltage, and the gate terminal is coupled to the gate terminal of the first P-type MOSFET component and a second common contact point between the output terminals of the first operational amplifier; A first N-type MOSFET component has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the drain terminal, and the drain terminal is simultaneously coupled to the drain terminal of the second P-type MOSFET component ;as well as A second resistor has a first end and a second end respectively coupled to the source terminal and the ground terminal of the first N-type MOSFET component.

In one embodiment, the voltage regulation unit includes: A second operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and the negative input terminal is coupled to the drain terminal of the second P-type MOSFET component and the first N-type MOSFET component. a third common contact between the drain terminals; A third P-type MOSFET component has a gate terminal, a drain terminal and a source terminal, wherein the source terminal is coupled to the operating voltage, and the gate terminal is coupled to the output terminal of the second operational amplifier; a third resistor, a first end of which is coupled to the drain terminal of the third P-type MOSFET element; a fourth resistor, a first end and a second end of which are respectively coupled to a second end of the third resistor and the positive input end of the second operational amplifier; A fifth resistor, a first end of which is coupled to a fourth common node between the second end of the fourth resistor and the positive input end of the second operational amplifier, and a second end of which is coupled to Connect to the ground terminal; Wherein, a fifth common contact point between the second end of the third resistor and the first end of the fourth resistor serves as an output end of the voltage adjustment unit, and generates the output voltage to be fed back to the the negative input of the first operational amplifier.

Furthermore, the present invention also proposes an embodiment of an integrated circuit chip, which is characterized in that it includes a reference voltage generating circuit, and the reference voltage generating circuit includes: a bias current generating unit, used to generate a bias current; a reference voltage generating unit coupled to the bias current generating unit and generating a first reference voltage based on the bias current; and A voltage adjustment unit is coupled to the reference voltage generation unit and the bias current generation unit, and is used to perform a voltage adjustment process on the first reference voltage, thereby generating an output voltage that is fed back to the bias current generation unit.

In one embodiment, the integrated circuit chip is selected from the group consisting of a system on chip (SoC), an application specific integrated circuit (ASIC), a microcontroller chip, and a processor chip. , graphics chips, display driver chips, touch chips, touch and display integration (TDDI) chips, fingerprint recognition chips, and automotive electronic chips.

In one embodiment, the bias current generating unit includes: A first operational amplifier having a positive input terminal, a negative input terminal and an output terminal, and the negative input terminal is coupled to the output voltage; A first P-type MOSFET component has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the output terminal of the first operational amplifier, and the source terminal is coupled to an operating voltage; and a first resistor, a first end and a second end of which are respectively coupled to the drain terminal and a ground terminal of the first P-type MOSFET component; Wherein, the positive input terminal of the first operational amplifier is coupled to a first common node between the first terminal of the first resistor and the drain terminal of the first P-type MOSFET element.

In one embodiment, the reference voltage generating unit includes: A second P-type MOSFET component has a gate terminal, a drain terminal and a source terminal, wherein the source terminal is coupled to the operating voltage, and the gate terminal is coupled to the gate terminal of the first P-type MOSFET component and a second common contact point between the output terminals of the first operational amplifier; A first N-type MOSFET component has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the drain terminal, and the drain terminal is simultaneously coupled to the drain terminal of the second P-type MOSFET component ;as well as A second resistor has a first end and a second end respectively coupled to the source terminal and the ground terminal of the first N-type MOSFET component.

In one embodiment, the voltage regulation unit includes: A second operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and the negative input terminal is coupled to the drain terminal of the second P-type MOSFET component and the first N-type MOSFET component. a third common contact between the drain terminals; A third P-type MOSFET component has a gate terminal, a drain terminal and a source terminal, wherein the source terminal is coupled to the operating voltage, and the gate terminal is coupled to the output terminal of the second operational amplifier; a third resistor, a first end of which is coupled to the drain terminal of the third P-type MOSFET element; a fourth resistor, a first end and a second end of which are respectively coupled to a second end of the third resistor and the positive input end of the second operational amplifier; A fifth resistor, a first end of which is coupled to a fourth common node between the second end of the fourth resistor and the positive input end of the second operational amplifier, and a second end of which is coupled to Connect to the ground terminal; Wherein, a fifth common contact point between the second end of the third resistor and the first end of the fourth resistor serves as an output end of the voltage adjustment unit, and generates the output voltage to be fed back to the the negative input of the first operational amplifier.

Furthermore, the present invention also proposes an information processing device, which is characterized in that it includes at least one integrated circuit chip of the present invention as described above. In a feasible embodiment, the information processing device is selected from the group consisting of smart TVs. , smart phones, smart watches, smart bracelets, head-mounted display devices, tablet computers, desktop computers, notebook computers, all-in-one computers, industrial computers, server computers, financial transaction devices, vehicle entertainment systems, It is an electronic device among the group consisting of access control devices, fingerprint punch-in devices, and electronic door locks.

In order to enable the review committee to further understand the structure, characteristics, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are attached below.

Please refer to FIG. 3, which is a circuit diagram of a reference voltage generating circuit of the present invention. The present invention proposes a reference voltage generating circuit 1, which is integrated into an integrated circuit chip and used to generate a reference voltage as a reference voltage for other circuit units in the integrated circuit chip. As shown in Figure 3, the reference voltage generation circuit 1 of the present invention includes: a bias current generation unit 11, a reference voltage generation unit 12 and a voltage adjustment unit 13, wherein the bias current generation unit 11 is used to generate a bias Set current Ibias. Furthermore, the reference voltage generating unit 12 is coupled to the bias current generating unit and generates a first reference voltage _VR according to the bias current Ibias. According to the design of the present invention, the voltage adjustment unit 13 is coupled to the reference voltage generation unit 12 and the bias current generation unit 11, and is used to perform a voltage adjustment process on the first reference voltage _VR , thereby generating an output voltage. V _O . It should be understood that this output voltage V _O serves as a second reference voltage, which is transmitted to other circuit units in the integrated circuit chip, thereby serving as a reference voltage for other circuit units. Moreover, the output voltage V _O is fed back to the bias current generating unit 11 at the same time.

As shown in FIG. 3 , the bias current generating unit 11 includes: a first operational amplifier 111 , a first P-type MOSFET element 11P1 and a first resistor 11R1 , wherein the first operational amplifier 111 has a positive input terminal. , a negative input terminal and an output terminal, and the negative input terminal is coupled to the output voltage V _O . On the other hand, the first P-type MOSFET element 11P1 has a gate terminal, a drain terminal and a source terminal. The gate terminal is coupled to the output terminal of the first operational amplifier 111, and the source terminal is coupled to an operating voltage. _VDD . Furthermore, a first terminal and a second terminal of the first resistor 11R1 are respectively coupled to the drain terminal and a ground terminal of the first P-type MOSFET element 11P1, and the positive input terminal of the first operational amplifier 111 is coupled to Connected to a first common contact between the first terminal of the first resistor 11R1 and the drain terminal of the first P-type MOSFET element 11P1.

To further explain, the reference voltage generating unit 12 includes: a second P-type MOSFET element 12P2, a first N-type MOSFET element 12N1 and a second resistor 12R2, wherein the second P-type MOSFET element 12P2 has a gate terminal. , a drain terminal and a source terminal, the source terminal is coupled to the operating voltage V _DD , and the gate terminal is coupled to the gate terminal of the first P-type MOSFET element 11P1 and the output terminal of the first operational amplifier 111 a second common contact between them. As shown in Figure 3, the first N-type MOSFET element 12N1 has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the drain terminal, and the drain terminal is simultaneously coupled to the second P-type The drain terminal of MOSFET element 12P2. Furthermore, a first terminal and a second terminal of the second resistor 12R2 are respectively coupled to the source terminal and the ground terminal of the first N-type MOSFET element 12N1.

As shown in Figure 3, the voltage adjustment unit 13 includes: a second operational amplifier 131, a third P-type MOSFET element 13P3, a third resistor 13R3, a fourth resistor 13R4, and a fifth resistor 13R5, wherein, The second operational amplifier 131 has a positive input terminal, a negative input terminal and an output terminal, and the negative input terminal is coupled to the drain terminal of the second P-type MOSFET element 12P2 and the first N-type MOSFET element 12N1 A third common contact between the sink terminals. On the other hand, the third P-type MOSFET device 13P3 has a gate terminal, a drain terminal and a source terminal, wherein the source terminal is coupled to the operating voltage V _DD , and the gate terminal is coupled to the second operational amplifier 131 of this output. To explain in more detail, a first terminal of the third resistor 13R3 is coupled to the drain terminal of the third P-type MOSFET element 13P3, and a first terminal and a second terminal of the fourth resistor 13R4 are coupled respectively. to a second terminal of the third resistor 13R3 and the positive input terminal of the second operational amplifier 131 . On the other hand, a first terminal of the fifth resistor 13R5 is coupled to a fourth common node between the second terminal of the fourth resistor 13R4 and the positive input terminal of the second operational amplifier 131, and A second end is coupled to the ground end. It is worth noting that a fifth common contact point of the second end of the third resistor 13R3 and the first end of the fourth resistor 13R4 serves as an output end of the voltage adjustment unit 13, and generates the The output voltage V _O is fed back to the negative input terminal of the first operational amplifier 111 .

Continuously refer to FIG. 3 , and please refer to FIG. 4 at the same time, which is a circuit topology diagram of the reference voltage generating unit 12 shown in FIG. 3 . In Figure 3, a first offset voltage generated at the gate terminal of the second P-type MOSFET element 12P2, and Multiplied by a certain coefficient and then superimposed to the output voltage . And, in Figure 3, a second offset voltage is generated at the gate terminal of the first N-type MOSFET element 12N1, and Superimposed directly to the output voltage . In other words, the output voltage offset voltage It mainly comes from the second P-type MOSFET component 12P2 and the first N-type MOSFET component 12N1, and it can be calculated using the following formula: ··································· (1)

In the above formula (1), and The sum is the transconductance of the second P-type MOSFET element 12P2 and the first N-type MOSFET element 12N1. Thus, in In the case of . Therefore, as shown in Figure 3, just make sure à à The gain of the positive feedback loop is lower than 0Db, which can ensure at the correct DC operating point.

It should be supplemented that the output voltage Vout (ie, the reference voltage output to other circuit units) of the conventional reference voltage generating circuit 1a shown in Figure 1 can be expressed by the following formula (2): ····················· (2)

Analyzing the above equation (2), it can be seen that the operational amplifier 11a After being amplified 1+(R2a/R1a) times, it is superimposed to the output voltage Vout of the reference voltage generating circuit 1a. Among them, the value of the amplification factor 1+ (R2a/R1a) is related to the zero temperature coefficient. Therefore, in the common case where the ratio of the number of BJT components is 1:8, the value of the amplification factor 1+ (R2a/R1a) is usually 50 ~70. Finally, when ignoring the device mismatch of BJT components, resistors, and current mirrors (i.e., MOSFET components), the output offset voltage superimposed on the output voltage Vout can be expressed by the following equation (3): ······························(3)

Therefore, since the output offset voltage of the reference voltage generating circuit of the present invention is only , so it is significantly smaller than the output offset voltage of the conventional reference voltage generating circuit 1a.

In this way, the reference voltage generating circuit of the present invention has been completely and clearly described above; and from the above, it can be seen that the present invention has the following advantages:

(1) The present invention provides a reference voltage generating circuit, which has the following advantages: ensuring that the output voltage has low temperature drift characteristics and effectively reducing the output offset voltage at the same time.

(2) Furthermore, the present invention also provides an integrated circuit chip, which is characterized in that it includes a reference voltage generating circuit of the present invention as described above.

(3) Further, the present invention also proposes an information processing device, which is characterized in that it includes at least one integrated circuit chip of the present invention as described above. In a feasible embodiment, the information processing device is selected from the group consisting of: Smart TV, smart phone, smart watch, smart bracelet, head-mounted display device, tablet computer, desktop computer, notebook computer, all-in-one computer, industrial computer, server computer, financial transaction device, vehicle-mounted computer An electronic device among the group consisting of entertainment systems, access control devices, fingerprint punch-in devices, and electronic door locks.

It must be emphasized that the foregoing disclosed in this case are preferred embodiments. Any partial changes or modifications derived from the technical ideas of this case and easily inferred by those familiar with the art do not deviate from the patent of this case. category of rights.

To sum up, regardless of the purpose, means and effects of this case, it shows that it is completely different from the conventional technology, and that the invention is practical first, and indeed meets the patent requirements for inventions. I sincerely ask the review committee to take a clear look and grant the patent as soon as possible for your benefit. Society is a prayer for the Supreme Being.

1a: Reference voltage circuit

11a: Operational amplifier

M1a: The first MOSFET element

M2a: Second MOSFET component

M3a: The third MOSFET component

M4a: The fourth MOSFET component

Mn1a: The first N-type MOSFET component

Mn2a: The second N-type MOSFET component

Q1a: The first BJT component

Q2a: Second BJT component

R1a: first resistor

R2a: first resistor

111a: Current source

1: Reference voltage circuit

11: Bias current generation unit

12: Reference voltage generation unit

13:Voltage adjustment unit

111: First operational amplifier

11P1: The first P-type MOSFET component

11R1: first resistor

12P2: The second P-type MOSFET component

12N1: The first N-type MOSFET component

12R2: Second resistor

131: Second operational amplifier

13P3: The third P-type MOSFET component

13R3: The third resistor

13R4: The fourth resistor

13R5: The fifth resistor

Figure 1 is a circuit topology diagram of a conventional reference voltage circuit; Figure 2 is the internal circuit topology of the operational amplifier shown in Figure 1; Figure 3 is a circuit diagram of a reference voltage generating circuit according to the present invention; and FIG. 4 is a circuit topology diagram of the reference voltage generating unit shown in FIG. 3 .

1: Reference voltage circuit

11: Bias current generation unit

12: Reference voltage generation unit

13:Voltage regulating unit

111: First operational amplifier

11P1: The first P-type MOSFET component

11R1: first resistor

12P2: The second P-type MOSFET component

12N1: The first N-type MOSFET component

12R2: Second resistor

131: Second operational amplifier

13P3: The third P-type MOSFET component

13R3: The third resistor

13R4: The fourth resistor

13R5: The fifth resistor

Claims (4)

A reference voltage generating circuit includes: a bias current generating unit for generating a bias current, which includes: a first operational amplifier having a positive input terminal, a negative input terminal and an output terminal, and the negative input terminal is The input terminal is coupled to the output voltage; a first P-type MOSFET component has a gate terminal, a drain terminal and a source terminal, the gate terminal is coupled to the output terminal of the first operational amplifier, and the source terminal is coupled to connected to an operating voltage; and a first resistor, a first end and a second end of which are respectively coupled to the drain end and a ground end of the first P-type MOSFET element; wherein, the positive end of the first operational amplifier The input terminal is coupled to a first common contact between the first terminal of the first resistor and the drain terminal of the first P-type MOSFET element; a reference voltage generating unit coupled to the bias current generating unit , a first reference voltage is generated according to the bias current, and includes: a second P-type MOSFET component having a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage, and the gate terminal terminal is coupled to a second common contact between the gate terminal of the first P-type MOSFET component and the output terminal of the first operational amplifier; a first N-type MOSFET component has a gate terminal, a drain terminal terminal and a source terminal, the gate terminal is coupled to the drain terminal, and the drain terminal is simultaneously coupled to the drain terminal of the second P-type MOSFET component; and a second resistor, a first terminal thereof and a second terminals respectively coupled to the source terminal and the ground terminal of the first N-type MOSFET component; and A voltage adjustment unit is coupled to the reference voltage generation unit and the bias current generation unit, and includes: a second operational amplifier having a positive input terminal, a negative input terminal and an output terminal, and the negative input terminal Coupled to a third common contact between the drain terminal of the second P-type MOSFET component and the drain terminal of the first N-type MOSFET component; a third P-type MOSFET component having a gate terminal, a A drain terminal and a source terminal, the source terminal is coupled to the operating voltage, and the gate terminal is coupled to the output terminal of the second operational amplifier; a third resistor, a first terminal of which is coupled to the third P the drain terminal of the MOSFET element; a fourth resistor, a first end and a second end of which are respectively coupled to a second end of the third resistor and the positive input end of the second operational amplifier; a first Five resistors, a first end of which is coupled to a fourth common node between the second end of the fourth resistor and the positive input end of the second operational amplifier, and a second end of which is coupled to the Ground terminal; wherein, a fifth common contact point of the second terminal of the third resistor and the first terminal of the fourth resistor serves as an output terminal of the voltage adjustment unit, and generates an output voltage feedback to the negative input terminal of the first operational amplifier. An integrated circuit chip is characterized in that it includes a reference voltage generating circuit, and the reference voltage generating circuit includes: a bias current generating unit for generating a bias current, which includes: A first operational amplifier having a positive input terminal, a negative input terminal and an output terminal, and the negative input terminal is coupled to the output voltage; a first P-type MOSFET element having a gate terminal, a drain terminal and a source terminal, the gate terminal is coupled to the output terminal of the first operational amplifier, and the source terminal is coupled to an operating voltage; and a first resistor, a first end and a second end of which are respectively coupled to the first The drain terminal of a P-type MOSFET component and a ground terminal; wherein, the positive input terminal of the first operational amplifier is coupled to the first terminal of the first resistor and the drain terminal of the first P-type MOSFET component a first common contact between; a reference voltage generating unit, coupled to the bias current generating unit, generating a first reference voltage according to the bias current, and including: a second P-type MOSFET element having A gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage, and the gate terminal is coupled to between the gate terminal of the first P-type MOSFET element and the output terminal of the first operational amplifier a second common contact between; a first N-type MOSFET component having a gate terminal, a drain terminal and a source terminal, the gate terminal is coupled to the drain terminal, and the drain terminal is simultaneously coupled to the second the drain terminal of the P-type MOSFET component; and a second resistor, a first terminal and a second terminal of which are respectively coupled to the source terminal and the ground terminal of the first N-type MOSFET component; and a voltage adjustment unit, The reference voltage generating unit and the bias current generating unit are coupled, and include: A second operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and the negative input terminal is coupled to the drain terminal of the second P-type MOSFET component and the first N-type MOSFET component. a third common contact between the drain terminals; a third P-type MOSFET component having a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage, and the gate terminal is coupled to the the output end of the second operational amplifier; a third resistor with a first end coupled to the drain end of the third P-type MOSFET element; a fourth resistor with a first end and a second end respectively a second terminal coupled to the third resistor and the positive input terminal of the second operational amplifier; a fifth resistor having a first terminal coupled to the second terminal of the fourth resistor and the second A fourth common contact point between the positive input terminal of the operational amplifier, and a second terminal thereof coupled to the ground terminal; wherein, the second terminal of the third resistor and the first terminal of the fourth resistor A fifth common contact serves as an output terminal of the voltage adjustment unit, and generates an output voltage that is fed back to the negative input terminal of the first operational amplifier. The integrated circuit chip as described in claim 2, wherein the integrated circuit chip is selected from the group consisting of system on chip (SoC), application specific integrated circuit (ASIC) chip, Among the groups consisting of microcontroller chips, processor chips, graphics chips, display driver chips, touch chips, touch and display integration (TDDI) chips, fingerprint recognition chips, and automotive electronic chips Either. An information processing device, characterized by having at least one integrated circuit chip as described in any one of claims 2 to 3.

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