TWI817691B - Semiconductor device - Google Patents

Abstract

Embodiments provide a semiconductor device. The semiconductor device includes a semiconductor substrate, a first deep well region, at least two second well regions, at least one isolation structure and an implantation region. The first deep well region is disposed in the semiconductor substrate, wherein the first deep well region has a first conductive type. The second well regions are disposed on the first deep well region, wherein the second well regions have a second conductive type. The isolation structure covers a portion of the first deep well region and surrounds at least a portion of the second well regions. The implantation region is disposed under a top surface of the semiconductor substrate, wherein the implantation region has a discontinuous portion partially overlaps with the first deep well region.

Description

Semiconductor device

This invention relates to semiconductor devices, and more particularly to Schottky diodes.

Schottky barrier diode is a semiconductor device with a metal-semiconductor junction. The contact between metal and lightly doped semiconductor material will produce a contact structure similar to a PN junction (Schottky barrier diode). contact), can be used to make Schottky diodes. When the Schottky diode is in forward bias (that is, a positive voltage is applied to the anode and a negative voltage is applied to the cathode), the carriers can be turned on, and when the Schottky diode is in reverse bias (that is, a negative voltage is applied to the anode and a negative voltage is applied to the cathode) Applying a positive voltage to the cathode) makes it difficult for carriers to conduct, so it has the same one-way conduction characteristics as a general PN junction diode. In addition, since the Schottky diode system moves as a single carrier, it has a relatively low critical voltage when biased in the forward direction and the reaction speed is extremely fast when switching between forward and reverse bias voltages. In fact, the Schottky diode is not an ideal device and a small amount of reverse leakage current will flow. Reverse leakage current will affect the performance of the circuit and reduce the efficiency of the circuit. In order to reduce the reverse leakage current, argon ions will be planted in the anode area, but this will reduce the conduction current of the Schottky diode.

To sum up, there is a need for new Schottky diodes that can still take into account their conduction current while reducing their reverse leakage current.

Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a semiconductor substrate, a first deep well region, at least two second well regions, at least one isolation structure and a implantation region. A first deep well region is disposed in the semiconductor substrate, wherein the first deep well region has a first conductivity type; at least two second well regions are disposed on the first deep well region, wherein the second well region has a second conductivity type; the isolation structure covers Part of the first deep well area and surrounding at least part of the second well area; the implantation area is located under the top surface of the semiconductor substrate, wherein the implantation area has a discontinuous portion, and the discontinuous portion partially overlaps the first deep well area.

The present disclosure will be more fully explained below with reference to the drawings of embodiments of the present invention. However, the present disclosure can also be implemented in various different implementations and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numbers refer to the same or similar elements in the various drawings.

Embodiments of the present invention provide a semiconductor device, such as a Schottky barrier diode. An implantation region that partially covers the anode region is provided in the semiconductor device. The implantation region is only located in the second well region for clamping the off-state leakage current and conducts the on-state leakage current. -state current) does not have a planting area in the first deep well area. Therefore, the reduction of the on-current of the Schottky diode can be avoided and the problem of off-state leakage can be improved.

Figure 1 is a schematic top view of a semiconductor device 500 according to some embodiments of the present invention. Figure 2 is a schematic cross-sectional view along line A-A' of the semiconductor device 500 in Figure 1 according to some embodiments of the present invention. For illustration, Figure 1 only shows some components, and the remaining components can be seen in the schematic cross-section in Figure 2 . In some embodiments, semiconductor device 500 includes a Schottky diode. As shown in FIGS. 1 and 2 , in some embodiments, the semiconductor device 500 includes a semiconductor substrate 200 , a first deep well region 206 , a second well region 208 , an isolation structure 204 and a implantation region 218 .

In some embodiments, the semiconductor substrate 200 includes elemental semiconductors, such as silicon (Si), germanium (Ge), etc.; compound semiconductors, such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), phosphorus Gallium (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), etc.; alloy semiconductors, such as silicon germanium alloy (SiGe), gallium arsenic phosphorus alloy (GaAsP), aluminum indium arsenide Alloy (AlInAs), arsenic aluminum gallium alloy (AlGaAs), arsenic indium gallium alloy (GaInAs), phosphorus indium gallium alloy (GaInP), phosphorus indium gallium arsenic alloy (GaInAsP), or a combination of the above materials. In addition, the semiconductor substrate 200 may also include a semiconductor on insulator (SOI). In some embodiments, the conductivity type of the semiconductor substrate 200 may be P-type or N-type according to design requirements.

As shown in FIGS. 1 and 2 , a first deep well region 206 and a plurality of second well regions 208 are provided in the semiconductor substrate 200 . The plurality of second well areas 208 are respectively provided on and outside the first deep well area 206 . The second well area 208 provided on the first deep well area 206 includes second well area portions 208-1, 208-2, and 208-3. In the top view as shown in FIG. 1 , the boundary 206E of the first deep well area 206 surrounds the second well area 208 disposed within the first deep well area 206 . In the cross-sectional view shown in FIG. 2 , the bottom surface 206B of the first deep well area 206 is located below the bottom surface 208B of the second well area 208 . In other words, the first deep well area 206 surrounds the second well area 208 disposed on the first deep well area 206 .

In some embodiments, the second well area 208 surrounded by the first deep well area 206 is in the shape of a plurality of annular portions arranged adjacently in the top view as shown in FIG. 1 . In some embodiments, the second well zone 208 surrounded by the first deep well zone 206 includes a plurality of finger-shaped second well zone portions 208-1, 208-2, 208-3 that are substantially parallel to each other. In the cross-sectional view shown in Figure 2, they are arranged at intervals, for example, in a sun shape. In some embodiments, the second well region 208 may not include the second well region portion 208-2 between the second well region portions 208-1, 208-3, and thus be annular in top view as shown in Figure 1 .

As shown in Figures 1 and 2, the second well area 208 arranged outside the first deep well area 206 surrounds the first deep well area 206, and the second well area 208 arranged outside the boundary 206E of the first deep well area 206 and The first deep well area 206 is adjacent. In some embodiments, the semiconductor device 500 further includes a wiring doped region 216 disposed on the second well region 208 outside the boundary 206E of the first deep well region 206 .

In some embodiments, first deep well region 206 has a first conductivity type. In some embodiments, the second well region 208 and the wire doped region 216 have a second conductivity type that is opposite to the first conductivity type. For example, when the first deep well region 206 is an N-type deep well region (DNW), the second well region 208 is, for example, a P-type well region (such as a P-type high pressure well region (HVPW)), and the wiring doping region 216 is, for example, It is the P-type wiring doped region. However, the present invention is not limited to this, and those skilled in the art can make adjustments according to actual needs. In some embodiments, the doping concentration of the wiring doped region 216 is greater than the doping concentration of the second well region 208 , and the doping concentration of the second well region 208 is greater than the doping concentration of the semiconductor substrate 200 . In some embodiments, the doping concentration of the first deep well region 206 is approximately between 1E12 atoms/cm ² and 1E13 atoms/cm ² , and the doping concentration of the second well region 208 is approximately between 1E12 atoms/cm ² and 1E13 atoms /cm ² .

In some embodiments, when the semiconductor device 500 is forward biased, the conduction current flows primarily through the first deep well region 206 in the anode region 230 . In some embodiments, when the semiconductor device 500 is reverse biased, a depletion region is generated in the first deep well region 206 between the second well region portions 208-1, 208-2, and 208-3 in the anode region 230. , which has a clamping effect (pinch) on the off-state leakage. In some embodiments, the semiconductor substrate 200 is electrically connected to the base (Bulk) of the final semiconductor device 500 through the second well region 208 outside the first deep well region 206 and the wiring doping region 216 thereon.

As shown in FIGS. 1 and 2 , the semiconductor device 500 further includes a third well region 210 in the semiconductor substrate 200 and a wiring doping region 212 disposed on the third well region 210 . The third well region 210 and the wiring doping region 212 are disposed on the first deep well region 206 . The third well region 210 and the wiring doped region 212 are close to the boundary 206E of the first deep well region 206 and are respectively disposed on opposite sides of the isolation structure 204 from the second well region portions 208-1 and 208-3. The third well region 210 and the wiring doping region 212 are also respectively disposed on opposite sides of the isolation structure 204 on the boundary 206E of the first deep well region 206 with the second well region 208 outside the boundary 206E of the first deep well region 206 . As shown in FIG. 2 , the bottom surface 210B of the third well area 210 is located above the bottom surface 206B of the first deep well area 206 and the bottom surface 208B of the second well area 208 . As shown in FIGS. 1 and 2 , the third well region 210 and the wiring doping region 212 directly above it surround the second well region 208 on the first deep well region 206 . In some embodiments, the third well region 210 and the wiring doped region 212 have the first conductivity type. For example, when the first deep well region 206 is an N-type deep well region (DNW), the third well region 210 is, for example, an N-type well region (such as an N-type low-pressure well region (NW)), and the wiring doping region 212 is, for example, It is the N-type wiring doped region. However, the present invention is not limited to this, and those skilled in the art can make adjustments according to actual needs. In some embodiments, the doping concentration of the wiring doped region 212 is greater than the doping concentration of the third well region 210 , and the doping concentration of the third well region 210 is greater than the doping concentration of the first deep well region 206 . The first deep well region 206 is electrically connected to the cathode region 232 of the final semiconductor device 500 through the third well region 210 and the wiring doping region 212 thereon. In some embodiments, the doping concentration of the third well region 210 is approximately between 1E13 atoms/cm ² and 1E14 atoms/cm ² , and the doping concentration of the wiring doped region 212 is approximately between 1E15 atoms/cm ² and 1E16 atoms /cm ² .

As shown in FIGS. 1 and 2 , in one embodiment, the semiconductor device 500 further includes a fourth well region 211 in the semiconductor substrate 200 . The fourth well area 211 is disposed on the second well area 208 and includes fourth well area portions 211-1, 211-2, and 211-3. The fourth well area parts 211-1, 211-2, and 211-3 are respectively located on the second well area parts 208-1, 208-2, and 208-3, and are respectively surrounded by the second well area parts 208-1, 208- 2. Surrounded by 208-3. As shown in FIG. 2 , the bottom surface 211B of the fourth well area 211 is located above the bottom surface 208B of the second well area 208 . In some embodiments, the fourth well region 211 has a second conductivity type. For example, when the first deep well area 206 is an N-type deep well area (DNW), the fourth well area 211 is, for example, a P-type well area (eg, a P-type low-pressure well area (PW)). However, the present invention is not limited to this, and those skilled in the art can make adjustments according to actual needs. In some embodiments, the doping concentration of the fourth well region 211 is greater than the doping concentration of the second well region 208 and less than the doping concentration of the wiring doped region 216 . The second well region 208 is electrically connected to the anode region 230 of the final semiconductor device 500 through the fourth well region 211 thereon. In some embodiments, the doping concentration of the fourth well region 211 is approximately between 1E13 atoms/cm ² and 1E14 atoms/cm ² .

In some embodiments, a multi-channel ion implantation process can be used to implant dopants having the first conductivity type and the second conductivity type into the semiconductor substrate 200 to form the first deep well region 206, the second well region 208, The third well region 210, the fourth well region 211 and the wiring doped regions 212 and 216. In some embodiments, the first conductivity type dopant is, for example, an N-type dopant, which may include phosphorus, arsenic, nitrogen, antimony, or a combination thereof. In some embodiments, the second conductive type dopant, such as a P-type dopant, may include boron, gallium, aluminum, indium, boron trifluoride ions (BF ₃ ⁺ ), or a combination thereof.

As shown in FIGS. 1 and 2 , a plurality of isolation structures 204 are disposed on the semiconductor substrate 200 in the first deep well area 206 , on the boundary 206E of the first deep well area 206 , and in the second well area 208 outside the first deep well area 206 superior. In the cross-sectional view shown in Figure 2, the isolation structure 204 in the first deep well area 206 surrounds the second well area portions 208-1, 208-2, and 208-3, and is connected to the second well area portion 208-1 respectively. It partially overlaps with the second well area part 208-3. In some embodiments, the bottom surface 206B of the first deep well region 206 and the bottom surface 208B of the second well region 208 are located below the bottom surface 204B of the isolation structure. As shown in FIGS. 1 and 2 , the isolation structure 204 defines the location where the anode region 230 and the cathode region 232 of the final semiconductor device 500 are formed. In some embodiments, any number of isolation structures 204 can be disposed on the semiconductor substrate 200 according to design requirements. In some embodiments, the isolation structure 204 is a field oxide (FOX) layer formed using a local oxidation of silicon (LOCOS) process, a shallow trench isolation formed using a deposition process, STI) structure, or other suitable isolation structure. In some embodiments, the isolation structure 204 is formed using a thermal oxidation process, including a dry oxidation process, a wet oxidation process, or other suitable thermal oxidation processes.

As shown in FIGS. 1 and 2 , the implantation area 218 is provided on the surface of the semiconductor substrate 200 and is located in the first deep well area 206 and the second well area 208 . In some embodiments, the top view shape of the implanted region 218 substantially overlaps the top view shape of the second well region 208 above the first deep well region 206, as shown in FIG. 1 . As shown in Figures 1 and 2, the implantation area 218 is annular or has a shape in which a plurality of annular regions are arranged adjacently in the top view as shown in Figure 1, such as a sun shape. In some embodiments, the implantation area 218 includes a plurality of finger-shaped implantation area portions 218-1, 218-2, 218-3 that are substantially parallel to each other. In the cross-sectional view shown in FIG. are arranged at intervals from each other and are arranged corresponding to the second well area portions 208-1, 208-2, and 208-3. For example, the implantation area portion 218-1 is disposed corresponding to the second well area portion 208-1 and may extend to the isolation structure 204 adjacent to the second well area portion 208-1. In some embodiments, the second well zone portion 208-1 is bounded 208-1E, the second well zone portion 208-2 is bounded 208-2E, and the second well zone portion 208-3 is bounded 208-3E. They are respectively located at the boundary 218-1E of the corresponding planting area part 218-1, the boundary 218-2E of the planting area part 218-2, and the boundary 218-3E of the planting area part 218-3. Technology in this field Personnel can adjust the relative positions of the second well area boundaries 208-1E, 208-2E, and 208-3E and the planting area boundaries 218-1E, 218-2E, and 218-3E, and the invention is not limited thereto.

As shown in Figures 1 and 2, the planting area 218 has discontinuous portions 220-1 and 220-2, and the discontinuous portions 220-1 and 220-2 partially overlap the first deep well area 206. For example, the discontinuous portion 220-1 of the implanted region 218 is located in the first deep well zone 206 between the second well zone portions 208-1, 208-2 of the second well zone 208. The discontinuous portion 220-2 of the implanted zone 218 is located in the first deep well zone 206 between the second well zone portions 208-2, 208-3 of the second well zone 208. In some embodiments, the discontinuous portions 220 - 1 , 220 - 2 of the implanted region 218 completely overlap at least a portion of the first deep well region 206 surrounded by the second well region 208 . Alternatively, the portion of the first deep well area 206 surrounded by the second well area 208 may partially overlap with the discontinuous portions 220 - 1 , 220 - 2 of the implantation area 218 . In some embodiments, the discontinuous portions 220-1, 220-2 of the implanted area 218 do not overlap at all with the second well portions 208-1, 208-2, 208-3 of the second well 208. As shown in FIG. 2 , the bottom surface 218B of the implantation area 218 is above the bottom surface 204B of the isolation structure 204 . In some embodiments, an ion implantation process may be used to implant ions of argon, silicon, germanium, fluorine, nitrogen, selenium, sulfur, or a combination thereof into a region of the semiconductor substrate 200 close to the top surface 201 to form implants. area 218 and convert the material of the semiconductor substrate 200 in the implantation area 218 into an amorphous semiconductor material, such as amorphous silicon (α-Si). Therefore, the implanted region 218 can also be regarded as the amorphous semiconductor material region 218 . The above-mentioned amorphous semiconductor material has high resistance to form a Schottky energy barrier, which can reduce the current flowing through the anode region 230 . In some embodiments, the doping concentration of the implanted region 218 is approximately between 1E14 atoms/cm ² and 1E15 atoms/cm ² .

As shown in FIGS. 1 and 2 , the semiconductor device 500 further includes a gate structure 228 , which is disposed on the semiconductor substrate 200 in the first deep well region 206 and extends to cover the isolation structure 204 and the adjacent second well region 208 . In the top view shown in FIG. 1 , the gate structure 228 surrounds the second well region 208 and is connected to the isolation structure 204 within the first deep well region 206 and surrounding the second well region 208 and the adjacent second well region. 208 partially overlaps. In some embodiments, the gate structure 228 includes a gate dielectric layer 222 disposed on the semiconductor substrate 200 , a gate electrode layer 224 disposed above the gate dielectric layer 222 , and a gate dielectric layer 222 disposed between the gate dielectric layer 222 and the gate dielectric layer 222 . Gate spacers 226 on the sidewalls of the gate electrode layer 224 . The gate structure 228 can be electrically connected to the anode region 230 of the semiconductor device, and has an electric field dispersion effect when the semiconductor device 500 is under reverse bias, which can improve the voltage collapse performance of the semiconductor device 500 under reverse bias.

In some embodiments, gate dielectric layer 222 includes silicon oxide, silicon nitride, silicon oxynitride, high-k materials, other suitable dielectric materials, and /or a combination of the above. The above-mentioned high dielectric constant materials are, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide alloy, and/or the above combination or similar materials. In some embodiments, an oxidation process, a deposition process, or other suitable processes may be used to form the gate dielectric layer 222 on the semiconductor substrate 200 .

In some embodiments, the gate electrode layer 224 includes polycrystalline silicon, amorphous silicon, metal (such as tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, other suitable metals, or combinations thereof), metal alloys, metal Nitride (such as tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, other suitable metal nitrides, or combinations of the above), metal oxides (ruthenium oxide, indium tin oxide, other suitable metal oxides , or a combination of the above), other suitable materials, or a combination of the above. In some embodiments, dopants may be implanted into the gate electrode layer 224 using in-situ doping.

In some embodiments, gate spacer 226 includes silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant materials, other suitable dielectric materials, and/or or a combination of the above. In some embodiments, an oxidation process, a deposition process, or other suitable processes may be used to form gate spacers 226 on the sidewalls of gate dielectric layer 222 and gate electrode layer 224 .

As shown in Figures 1 and 2, the semiconductor device 500 further includes a conductive component 229, which is disposed on the semiconductor substrate 200 and contacts (physically contacts) the second well area 208 on the first deep well area 206 and the second well area 208 surrounding it. part of the first deep well area 206. Furthermore, in one embodiment, the conductive component 229 contacts the discontinuous portions 220-1, 220-2 of the implanted area 218. In one embodiment, the conductive component 229 contacts the second well portion 208-2 of the second well portion 208, the first deep well region 206 between the second well portions 208-1, 208-2, and the second well region. The first deep well area 206 between parts 208-2 and 208-3. In some embodiments, the conductive component 229 is electrically connected to the gate structure 228 . In some embodiments, the conductive component 229 may serve as an anode electrode of the semiconductor device 500, including metals such as nickel (Ni), cobalt (Co), platinum (Pt), titanium (Ti), tungsten (W), aluminum ( Al), a combination of the above, or similar materials) to form metal silicide with the semiconductor substrate 200. In some embodiments, conductive component 229 may also include doped polysilicon. In some embodiments, conductive features 229 may be formed using a deposition process (eg, physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or a combination thereof) and a subsequent patterning process.

In some embodiments, the semiconductor device 500 is formed by providing a semiconductor substrate 200 and then forming the isolation structure 204 in the semiconductor substrate 200 . Next, a first deep well region 206 is formed in the semiconductor substrate 200 . Then, a second well area 208 is formed on the first deep well area 206 . Afterwards, a fourth well area 211 is formed on the second well area 208. Then, a third well area 210 is formed on the first deep well area 206 . Then, a gate structure 228 is formed on the semiconductor substrate 200 in the first deep well region 206 . Afterwards, a wiring doped region 212 is formed on the first deep well region 206 . Next, a implantation region 218 is formed on the surface of the semiconductor substrate 200 and in the first deep well region 206 and the second well region 208 . Then, the conductive member 229 is formed on the semiconductor substrate 200 . Finally, the semiconductor device 500 according to the embodiment of the present invention is formed.

As shown in Figures 1 and 2, a portion of the first deep well region 206 between the second well region 208 and the second well region portions 208-1, 208-2, and 208-3 serves as a semiconductor such as a Schottky diode. Anode region 230 of device 500 . In other words, in the top view as shown in FIG. 1 , the second well region 208 and the portion of the first deep well region 206 surrounded by the second well region 208 serve as the anode region 230 of the semiconductor device 500 , such as a Schottky diode. . Furthermore, the portion of the first deep well region 206 located on the opposite side of the isolation structure 204 and the second well region portions 208-1, 208-3 of the second well region 208 and the third well region 210 thereon are, for example, Schottky diodes. cathode region 232 of bulk semiconductor device 500 . In other words, the portion of the first deep well zone 206 located between the boundary 206E of the first deep well zone 206 and the second well zone portions 208 - 1 , 208 - 3 of the second well zone 208 and the third well zone 210 thereon The cathode region 232 of the semiconductor device 500 is, for example, a Schottky diode. In some embodiments, anode region 230 of semiconductor device 500 includes discontinuous portions 220 - 1 , 220 - 2 of implanted region 218 . In other words, part of the anode region 230 of the semiconductor device 500 does not have the implanted region 218 .

FIG. 3 is a cumulative percentage distribution diagram of the conduction current of a semiconductor device according to some embodiments of the present invention and a Schottky diode according to a comparative embodiment. The data point group 302 in Figure 3 represents the conduction current of the relative embodiment (the implantation area completely covers the anode area), and the data point group 304 represents some embodiments of the present invention, such as the semiconductor device 500 of Schottky diode ( The implanted area has discontinuous parts) conduction current. As can be seen from Figure 3, compared to the Schottky diode in the relative embodiment, the semiconductor device 500 in some embodiments of the present invention does not have a implanted area (or only has a partial implanted area) due to the first deep well area 206 through which the conduction current flows. area), the resistance of part of the anode area (Schottky barrier height) can be reduced, thereby significantly increasing the conduction current of the semiconductor device 500 .

FIG. 4 is a cumulative percentage distribution graph of off-state current (leakage) for a semiconductor device according to some embodiments of the present invention and a Schottky diode according to a comparative embodiment. The data point group 402 in FIG. 4 represents the off-state current of the relative embodiment (the implanted area completely covers the anode area), and the data point group 404 represents the semiconductor device 500 of some embodiments of the present invention, such as a Schottky diode. (the implanted area has discontinuous parts). As can be seen from FIG. 4 , the semiconductor device 500 in some embodiments of the present invention still has a implanted region due to the second well region 208 through which the off-state current (leakage) flows. Therefore, the off-state current of the semiconductor device 500 is compared with the relative embodiment. Low.

Embodiments of the present invention provide a semiconductor device, such as a Schottky barrier diode. The semiconductor device includes an implantation region covering part of the anode region. The implantation region is located only in the second-type well region for clamping off-state current (leakage) to form an amorphous semiconductor material with higher resistance therein. region, improve the Schottky energy barrier, and reduce the leakage current of the semiconductor device 500 in the off state. However, there is no implantation area in the first type deep well area that conducts on-state current in the semiconductor device, which can reduce the adverse impact on the on-state current. Therefore, the semiconductor device according to the embodiment of the present invention can avoid the reduction of the on-current of the Schottky diode and at the same time improve the problem of off-state leakage.

Although the present invention is disclosed in the foregoing embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

200:Semiconductor substrate

201:Top surface

206:The first deep well area

206E,208-1E,208-2E,208-3E,218-1E,218-2E,218-3E:Boundary

204B, 206B, 208B, 210B, 211B, 218B: Bottom

208:Second well area

208-1, 208-2, 208-3: Part of the second well area 204:Isolation structure 210:Third well area 211:The fourth well area 211-1, 211-2, 211-3: Part of the fourth well area 212,216: Wiring doping area 218:Planting area 218-1, 218-2, 218-3: Planting area part 220-1, 220-2: discontinuous part 222: Gate dielectric layer 224: Gate electrode layer 226: Gate spacer 228: Gate structure 229: Conductive parts 230: Anode area 232:Cathode area 302,304,402,404: Data point population 500:Semiconductor device A-A’: Tangent line

Views of embodiments of the present invention may be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced in order to clearly illustrate the features of the embodiments of the invention.

Figure 1 is a schematic top view of a semiconductor device according to some embodiments of the present invention.

Figure 2 is a schematic cross-sectional view along line A-A' of the semiconductor device in Figure 1 according to some embodiments of the present invention.

Figure 3 is a comparison diagram of the on-current of semiconductor devices according to some embodiments of the present invention and conventional Schottky diodes.

Figure 4 is a comparison diagram of the off-state current of a semiconductor device according to some embodiments of the present invention and a conventional Schottky diode.

200:Semiconductor substrate

201:Top surface

204:Isolation structure

206:The first deep well area

206E,208-1E,208-2E,208-3E,218-1E,218-2E,218-3E:Boundary

204B, 206B, 208B, 210B, 211B, 218B: Bottom

208:Second well area

208-1, 208-2, 208-3: Part of the second well area

210:Third well area

211:The fourth well area

211-1, 211-2, 211-3: Part of the fourth well area

212,216: Wiring doping area

218:Planting area

218-1, 218-2, 218-3: Planting area part

220-1, 220-2: discontinuous part

222: Gate dielectric layer

224: Gate electrode layer

226: Gate spacer

228: Gate structure

229: Conductive parts

230: Anode area

232:Cathode area

500:Semiconductor device

A-A’: Tangent line

Claims (15)

A semiconductor device, including: a semiconductor substrate; a first deep well region disposed in the semiconductor substrate; wherein the first deep well region has a first conductivity type; at least two second well regions disposed in the first deep well on the region; wherein the second well regions have a second conductivity type; at least one isolation structure covering part of the first deep well region and surrounding at least part of the second well regions; and a implantation region located on the semiconductor A top surface of the substrate; wherein the implantation area has a discontinuous portion, the discontinuity portion partially overlaps the first deep well area, and the implantation area completely covers the second well areas, wherein the implantation area is A region of amorphous semiconductor material. The semiconductor device of claim 1, wherein the discontinuous portion of the implantation region is located in the first deep well region between the second well regions. The semiconductor device of claim 1, wherein the second well regions surround the discontinuous portion of the implantation region. The semiconductor device of claim 1, wherein the discontinuous portion of the implantation region completely overlaps the portion of the first deep well region surrounded by the second well regions. The semiconductor device of claim 1, wherein the discontinuous portion of the implantation region does not overlap at all with the second well regions. The semiconductor device of claim 1, wherein a bottom surface of the implantation area above a bottom surface of the isolation structure. The semiconductor device of claim 1, wherein the implantation region extends within the isolation structure. The semiconductor device of claim 1, wherein the second well regions partially overlap the adjacent isolation structures. The semiconductor device of claim 1, further comprising: a gate structure disposed on the semiconductor substrate in the first deep well region and extending to cover the isolation structure and one of the adjacent second well regions. . The semiconductor device of claim 9 further includes: a conductive component disposed on the semiconductor substrate and contacting the second well areas and the first deep well areas between the second well areas. The semiconductor device of claim 10, wherein the conductive component contacts the discontinuous portion of the implantation area. The semiconductor device of claim 10, wherein the conductive component is electrically connected to the gate structure. The semiconductor device of claim 10, wherein the portion of the first deep well region between the second well regions serves as an anode region of a Schottky diode and is located between the isolation structure and the plurality of second well regions. The portion of the first deep well region on the opposite side of the second well region serves as a cathode region of the Schottky diode. The semiconductor device of claim 13, wherein the anode region of the Schottky diode includes the discontinuous portion of the implantation region. The semiconductor device of claim 1, wherein the implanted region includes ions of argon, silicon, germanium, fluorine, nitrogen, selenium, sulfur or a combination thereof.

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