TWI815280B - Transistor structure - Google Patents

Abstract

A transistor structure including a substrate, an isolation structure, a first gate electrode, a second gate electrode, a dielectric spacer, and a conductive spacer is provided. The isolation structure is disposed in the substrate. The first gate is disposed on the substrate. The first gate and the substrate are electrically isolated from each other. The second gate is disposed on the isolation structure. The first gate and the second gate are separated from each other and electrically isolated from each other. The dielectric spacer surrounds a sidewall of the first gate and a sidewall of the second gate. The conductive spacer is disposed on the dielectric spacer and surrounds the sidewall of the first gate electrode and the sidewall of the second gate electrode. The second gate electrode and the conductive spacer are electrically connected to each other.

Description

transistor structure

The present invention relates to a semiconductor structure, and in particular to a transistor structure.

The figure of merit (FOM) of a transistor element is determined by the product of the on-resistance (R _on ) and the gate/drain charge (Q _gd ). In addition, the amount of gate/drain charge is determined by the miller capacitance (eg, fringe capacitance) between the gate and drain. Currently, in order to improve the energy conversion efficiency of transistor elements and suppress power loss, it is necessary to reduce the quality factor of transistor elements. Therefore, how to effectively reduce the quality factor of transistor elements is the current goal of continuous efforts.

The present invention provides a transistor structure that can effectively reduce the quality factor of the transistor element.

The invention proposes a transistor structure, which includes a substrate, an isolation structure, a first gate, a second gate, a dielectric spacer and a conductive spacer. The isolation structure is set at in the base. The first gate is disposed on the substrate. The first gate and the substrate are electrically isolated from each other. The second gate is disposed on the isolation structure. The first gate and the second gate are separated from each other and electrically isolated from each other. The dielectric spacer surrounds the sidewalls of the first gate and the sidewalls of the second gate. The conductive spacer is disposed on the dielectric spacer and surrounds the sidewall of the first gate and the sidewall of the second gate. The second gate electrode and the conductive gap wall are electrically connected to each other.

According to an embodiment of the invention, in the above transistor structure, the second gate is not located on any active region.

According to an embodiment of the invention, in the above transistor structure, the first gate and the second gate may be arranged in the gate width direction of the first gate.

According to an embodiment of the present invention, in the above transistor structure, part of the dielectric spacer may be located between the first gate and the second gate. A portion of the conductive spacer may be located between the first gate and the second gate.

According to an embodiment of the invention, in the above transistor structure, the conductive spacer and the first gate are electrically connected to different voltage sources.

According to an embodiment of the present invention, the above-mentioned transistor structure may further include a shared contact. The common contact window is electrically connected to the second gate and the conductive gap wall.

According to an embodiment of the present invention, the above transistor structure may further include a third gate. The third gate is arranged on the isolation structure. The second gate is located between the first gate and the third gate. The first gate and the third gate are separated from each other and electrically isolated from each other. The dielectric spacer and the conductive spacer respectively surround the sidewalls of the third gate. The second gate electrode, the third gate electrode and the conductive gap wall are electrically connected to each other.

According to an embodiment of the present invention, in the above transistor structure, part of the dielectric spacer may be located between the first gate and the second gate and between the second gate and the third gate. A portion of the conductive spacer may be located between the first gate and the second gate and between the second gate and the third gate.

According to an embodiment of the present invention, the transistor structure may include a plurality of first gates separated from each other and a plurality of second gates separated from each other. The third gate can be located on the same side of the plurality of second gates.

According to an embodiment of the present invention, the above transistor structure may include a plurality of first gates separated from each other. The second gate can be located on the same side of the plurality of first gates.

Based on the above, in the transistor structure proposed by the present invention, the first gate and the second gate are electrically isolated from each other, the conductive gap wall surrounds the side walls of the first gate and the second gate, and the second gate The pole and the conductive gap wall are electrically connected to each other. Therefore, the fringing capacitance can be suppressed by applying a voltage (eg, ground voltage) to the conductive spacer wall, thereby reducing the overall Miller capacitance. In this way, the quality factor of the transistor element can be effectively reduced, thereby improving the energy conversion efficiency of the transistor element and suppressing power loss.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

10,20,30,40:Transistor structure

100:Base

102:Isolation structure

104,106: Gate

108: Dielectric spacer

110: Conductive gap wall

112,114: Doped area

116:Well area

118:Sham Tseng District

120: Gate dielectric layer

122: Shared contact window

124:Contact window

126:Dielectric layer

AA: active area

D1: Gate width direction

D2: channel length direction

R: Groove

Figure 1A is a top view of a transistor structure according to some embodiments of the present invention.

Fig. 1B is a cross-sectional view along the line I-I' in Fig. 1A.

Figure 1C is a cross-sectional view along the II-II' section line in Figure 1A.

FIG. 2 is a top view of a transistor structure according to other embodiments of the present invention.

FIG. 3 is a top view of a transistor structure according to other embodiments of the present invention.

FIG. 4 is a top view of a transistor structure according to other embodiments of the present invention.

Examples are listed below and described in detail with reference to the drawings. However, the provided examples are not intended to limit the scope of the present invention. To facilitate understanding, the same components will be identified with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to original size. Also, the features in the upper view are not drawn to the same scale as those in the section view. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Figure 1A is a top view of a transistor structure according to some embodiments of the present invention. Fig. 1B is a cross-sectional view along the line I-I' in Fig. 1A. Figure 1C is a cross-sectional view along the II-II' section line in Figure 1A.

Referring to FIGS. 1A to 1C , the transistor structure 10 includes a substrate 100 , an isolation structure 102 , a gate 104 , a gate 106 , a dielectric spacer 108 and a conductive spacer 110 . In some embodiments, the transistor structure 10 may be a power metal oxide semiconductor (MOS) transistor, such as a lateral diffused metal oxide semiconductor (LDMOS) transistor. . The substrate 100 may be a semiconductor substrate, Such as silicon substrate. Isolation structure 102 is provided in substrate 100 . The isolation structure 102 may define an active area AA in the substrate 100 . The isolation structure 102 is, for example, a shallow trench isolation structure (shallow trench isolation, STI). The material of the isolation structure 102 may be, for example, silicon oxide, silicon nitride or a combination thereof.

In addition, the transistor structure 10 may further include at least one of a doped region 112 , a doped region 114 , a well region 116 and a deep well region 118 . The doped regions 112 and 114 are located in the substrate 100 on both sides of the gate 104 . The doped region 112 and the doped region 114 may serve as one or the other of the source region and the drain region, respectively. In addition, the doping region 112 and the doping region 114 may be located in the active area AA. The doped region 112 and the doped region 114 may have a first conductivity type (eg, N type). Hereinafter, the first conductivity type and the second conductivity type may be one or the other of N-type conductivity type and P-type conductivity type respectively. In this embodiment, the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type, for example, but the invention is not limited thereto. In other embodiments, the first conductivity type may be P-type conductivity type, and the second conductivity type may be N-type conductivity type.

Well region 116 is located in substrate 100 . Well region 116 may have a second conductivity type (eg, P-type). The doped regions 112 and 114 may be located in the well region 116 . Deep well region 118 is located in substrate 100 . Deep well region 118 may have a first conductivity type (eg, N-type). Well area 116 may be located in deep well area 118 .

The gate 104 is disposed on the substrate 100 . In some embodiments, part of the gate 104 may be located on the active area AA, and part of the gate 104 may be located on the isolation structure 102 . The material of the gate 104 is, for example, doped polysilicon. The gate 104 and the substrate 100 are electrically isolated from each other. For example, the transistor structure 10 may further include a gate dielectric layer 120 . The gate dielectric layer 120 is located between the gate 104 and the substrate 100, whereby the gate 104 and the substrate 100 can be electrically isolated from each other. The material of the gate dielectric layer 120 is, for example, silicon oxide.

Gate 106 is disposed on isolation structure 102 . Gate 104 and gate 106 are separated from each other and electrically isolated from each other. The gate 104 and the gate 106 may be arranged in the gate width direction D1 of the gate 104 . In some embodiments, the gate width direction D1 may be perpendicular to the channel length direction D2. In this embodiment, the "channel length direction" is defined as the direction extending through the doped region 112 and the doped region 114 . In some embodiments, gate 106 is not located on any active region. The material of the gate 106 is, for example, doped polysilicon.

Dielectric spacers 108 surround sidewalls of gate 104 and gate 106 . In some embodiments, dielectric spacers 108 may be a continuous structure surrounding the sidewalls of gate 104 and gate 106 . In some embodiments, a portion of dielectric spacer 108 may be located between gate 104 and gate 106 . In some embodiments, the dielectric spacers 108 may be disposed on the sidewalls of the gate 104 , the sidewalls of the gate 106 , the isolation structure 102 and the gate dielectric layer 120 . The material of the dielectric spacer 108 is, for example, silicon nitride.

The conductive spacer 110 is disposed on the dielectric spacer 108 and surrounds the sidewalls of the gate 104 and the gate 106 . In some embodiments, the conductive spacer 110 may be a continuous structure surrounding the sidewalls of the gate 104 and the gate 106 . Conductive spacers 110 may be located in recesses R of dielectric spacers 108 . In some embodiments, a portion of conductive spacer 110 may be located between gate 104 and gate 106 . The conductive spacer 110 is made of, for example, doped polysilicon.

The gate 106 and the conductive spacer 110 are electrically connected to each other. For example, The transistor structure 10 may further include a common contact 122 . The common contact 122 is electrically connected to the gate 106 and the conductive spacer 110 , whereby the gate 106 and the conductive spacer 110 can be electrically connected to each other. In addition, the arrangement position of the common contact windows 122 is not limited to the position in the figure, and the number of the common contact windows 122 is not limited to the number in the figure. As long as the position and number of the common contact windows 122 can enable the common contact windows 122 to be electrically connected to the gate 106 and the conductive spacer 110 , it falls within the scope of the present invention. The material of the common contact window 122 is, for example, tungsten.

The transistor structure 10 may further include at least one of a contact 124 and a dielectric layer 126 . The contact window 124 is electrically connected to the gate 104 . The common contact window 122 and the contact window 124 can be electrically connected to different voltage sources, whereby the conductive spacer 110 and the gate electrode 104 can be electrically connected to different voltage sources. The material of the contact window 124 is, for example, tungsten. The dielectric layer 126 may cover the substrate 100, the isolation structure 102, the gate 104, the gate 106, the dielectric spacer 108 and the conductive spacer 110. The common contact 122 and the contact 124 may be located in the dielectric layer 126 . The material of the dielectric layer 126 is, for example, silicon oxide.

Based on the above embodiments, it can be seen that in the transistor structure 10 , the gate 104 and the gate 106 are electrically isolated from each other, the conductive spacer 110 surrounds the side walls of the gate 104 and the side walls of the gate 106 , and the gate 106 and the conductive spacer 110 are electrically connected to each other. Therefore, the fringe capacitance can be suppressed by applying a voltage (eg, ground voltage) to the conductive spacer 110, thereby reducing the overall Miller capacitance. In this way, the quality factor of the transistor element can be effectively reduced, thereby improving the energy conversion efficiency of the transistor element and suppressing power loss.

FIG. 2 is a top view of a transistor structure according to other embodiments of the present invention.

Please refer to FIG. 1A and FIG. 2 . The differences between the transistor structure 20 of FIG. 2 and the transistor structure 10 of FIG. 1A are as follows. As shown in FIG. 2 , the transistor structure 20 may further include a gate 202 . Gate 202 is disposed on isolation structure 102 . Gate 106 is located between gate 104 and gate 202 . Gate 104 and gate 202 are separated from each other and electrically isolated from each other. The gate 104 , the gate 106 and the gate 202 may be arranged in the gate width direction D1 of the gate 104 . In some embodiments, gate 202 is not located on any active region. The material of the gate 202 is, for example, doped polysilicon.

The dielectric spacers 108 and the conductive spacers 110 respectively surround the sidewalls of the gate 202 . In some embodiments, dielectric spacers 108 and conductive spacers 110 may be continuous structures surrounding the sidewalls of gate 104 , the sidewalls of gate 106 , and the sidewalls of gate 202 , respectively. Portions of dielectric spacers 108 may be located between gate 104 and gate 106 and between gate 106 and gate 202 . Portions of conductive spacers 110 may be located between gate 104 and gate 106 and between gate 106 and gate 202 . Gate 106, gate 202 and conductive spacer 110 are electrically connected to each other. For example, gate 106 , gate 202 and conductive spacer 110 may be electrically connected to each other through a common contact 122 . In this embodiment, the common contact window 122 can be disposed between the gate 106 and the gate 202 , but the position of the common contact window 122 is not limited to the position in the figure. As long as the common contact window 122 is positioned so that the common contact window 122 can be electrically connected to the gate 106 , the gate 202 and the conductive spacer 110 , it falls within the scope of the present invention.

In addition, the same components in the transistor structure 20 and the transistor structure 10 are represented by the same symbols, and the same or similar contents in the transistor structure 20 and the transistor structure 10 can be referred to the description of the transistor structure 10 in the above embodiments. , not this Explain again.

FIG. 3 is a top view of a transistor structure according to other embodiments of the present invention.

Please refer to FIG. 1A and FIG. 3 . The differences between the transistor structure 30 of FIG. 3 and the transistor structure 10 of FIG. 1A are as follows. As shown in FIG. 3 , the transistor structure 30 may include a plurality of gates 104 separated from each other. The plurality of gates 104 can be respectively located on corresponding active areas AA. The gate 106 may be located on the same side of multiple gates 104 . In addition, the number of gates 104 is not limited to the number in the figure. As long as the number of gates 104 is multiple, it falls within the scope of the present invention.

In addition, the same components in the transistor structure 30 and the transistor structure 10 are represented by the same symbols, and for the same or similar contents in the transistor structure 30 and the transistor structure 10 , please refer to the description of the transistor structure 10 in the above embodiments. , will not be explained here.

FIG. 4 is a top view of a transistor structure according to other embodiments of the present invention.

Please refer to FIGS. 2 and 4 . The differences between the transistor structure 40 of FIG. 4 and the transistor structure 20 of FIG. 2 are as follows. As shown in FIG. 4 , the transistor structure 40 may include a plurality of gates 104 separated from each other and a plurality of gates 106 separated from each other. The plurality of gates 104 can be respectively located on corresponding active areas AA. Gate 202 may be located on the same side of multiple gates 106 . Additionally, the transistor structure 40 may include a plurality of common contacts 122 . The plurality of common contact windows 122 are electrically connected to the gate 202 , the conductive spacer 110 and the corresponding gate 106 respectively. In addition, the number of gates 104 , the number of gates 106 and the number of common contacts 122 are not limited to the numbers in the figures. As long as the number of gates 104, the number of gates 106 and the number of common contact windows 122 are multiple respectively, it belongs to the present invention. Explain the scope covered.

In addition, the same components in the transistor structure 40 and the transistor structure 20 are represented by the same symbols, and for the same or similar contents in the transistor structure 40 and the transistor structure 20 , please refer to the description of the transistor structure 20 in the above embodiment. , will not be explained here.

In summary, in the transistor structure of the above embodiments, the fringe capacitance can be suppressed by applying a voltage (eg, ground voltage) to the conductive spacer wall, thereby reducing the overall Miller capacitance. In this way, the quality factor of the transistor element can be effectively reduced, thereby improving the energy conversion efficiency of the transistor element and suppressing power loss.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

10: Transistor structure 102: Isolation Structure 104, 106: Gate 108: Dielectric spacer 110: Conductive gap wall 112, 114: Doped area 122: Shared contact window 124: Contact window AA: active area D1: Gate width direction D2: Channel length direction

Claims (10)

A transistor structure including: base; an isolation structure disposed in the substrate; A first gate disposed on the substrate, wherein the first gate and the substrate are electrically isolated from each other; a second gate disposed on the isolation structure, wherein the first gate and the second gate are separated from each other and electrically isolated from each other; a dielectric spacer surrounding the sidewall of the first gate and the sidewall of the second gate; and a conductive spacer disposed on the dielectric spacer and surrounding the sidewalls of the first gate and the second gate, wherein the second gate and the conductive spacer are electrically connected to each other connection. The transistor structure of claim 1, wherein the second gate is not located on any active region. The transistor structure of claim 1, wherein the first gate and the second gate are arranged in a gate width direction of the first gate. The transistor structure of claim 1, wherein part of the dielectric spacer is located between the first gate and the second gate, and part of the conductive spacer is located between the first gate and the first gate. between the gate and the second gate. The transistor structure of claim 1, wherein the conductive spacer and the first gate are electrically connected to different voltage sources. The transistor structure as described in claim 1 further includes: A common contact window is electrically connected to the second gate and the conductive spacer. The transistor structure as described in claim 1 further includes: The third gate is arranged on the isolation structure, wherein The second gate is located between the first gate and the third gate, the first gate and the third gate are separated from each other and electrically isolated from each other, The dielectric spacers and the conductive spacers respectively surround sidewalls of the third gate, and The second gate, the third gate and the conductive spacer are electrically connected to each other. The transistor structure of claim 7, wherein A portion of the dielectric spacer is located between the first gate and the second gate and between the second gate and the third gate, and Part of the conductive spacer is located between the first gate and the second gate and between the second gate and the third gate. The transistor structure of claim 7, comprising a plurality of first gates separated from each other and a plurality of second gates separated from each other, wherein the third gate is located at a plurality of the first gates. The same side of the two gates. The transistor structure of claim 1, including a plurality of first gates separated from each other, wherein the second gates are located on the same side of the plurality of first gates.

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