TWI812651B - Integrated circuit and method of manufacturing the same - Google Patents

Abstract

An integrated circuit and a method of manufacturing the same are provided. The integrated circuit including a series of field effect transistors. Each field effect transistor includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, and a drain contact on the drain region. Upper surfaces of the source and drain contacts are spaced below an upper surface of the gate by a depth.

Description

Integrated circuits and methods of manufacturing same

The present invention claims priority and rights to U.S. Provisional Application No. 62/587,214 filed on November 16, 2017. The entire content of the U.S. Provisional Application is incorporated into this application for reference.

The present invention relates generally to field effect transistors and methods of making said field effect transistors.

State-of-the-art standard cell architectures that include gate contacts above the active region are not suitable for the scaled contact poly pitch (CPP) required to scale cell width and cell area. For example, as shown in FIG. 1A , the prior art unit structure 100 includes a pair of field effect transistors (FETs) 101 and 102 (for example, n-type FET (n-FET) and p-type FET (p- FET)), each of the pair of field effect transistors 101 and 102 includes contacts 103 and 104 respectively located on the source region 105 and the drain region 106 and a contact 107 located on the active region of the gate 108 . FIG. 1B is a cross-sectional view along line 1B-1B of FIG. 1A. As shown in FIG. 1B , the heights of the contacts 103 and 104 on the source region 105 and the drain region 106 are at least as high as the height of the gate 108 so that the contacts 103 and 104 on the source region 105 and the drain region 106 are at least as high as the height of the gate 108 . The upper surfaces 109, 110 of the gate 104 are at least as high in the cell 100 as the upper surface 111 of the gate 108. In some technology standard cell architectures, the heights of the contacts 103 and 104 on the source region 105 and the drain region 106 may be higher than the height of the gate 108 so that the contacts 103 and 104 on the source region 105 and the drain region 106 The upper surfaces 109, 110 of 104 are located above the upper surface 111 of gate 108. In this prior art configuration, the lateral spacing between the contacts 103 and 104 on the source region 105 and the drain region 106 and the gate contact 107 on the active region cannot be too small, otherwise there will be a gap between the source region 105 and the gate contact 107 on the active region. An electrical short will occur between the contacts 103, 104 on the drain region 106 and the gate contact 107 on the active region.

Traditionally, thick nitride spacers 112 are provided adjacent the edge of the gate 108 to sufficiently separate the contacts 103, 104 on the source region 105 and drain region 106 from the edge of the gate 108, and therefore from the edges of the gate 108. The gate contacts 107 over the active region are sufficiently spaced to avoid electrical shorts between the contacts 103, 104 over the source region 105 and drain region 106 and the gate contacts 107 over the active region. However, the use of thick spacers 112 limits the reduction of the gate-to-gate spacing in the standard cell architecture 100 because there must be enough space to form contacts 103, 104. As such, the use of thick spacers limits the contact polysilicon pitch (CPP) reduction of the prior art standard cell architecture 100 .

The present invention relates to various embodiments of integrated circuits. In one embodiment, the integrated circuit includes a series of field effect transistors. Each field effect transistor includes: a source region; a drain region; a channel region extending between the source region and the drain region; a gate located on the channel region; and a gate contact , located on the gate at the active region of the gate; a source contact located on the source region; and a drain contact located on the drain region. The upper surface of the source contact and the upper surface of the drain contact are spaced apart a depth below the upper surface of the gate.

The depth may be from approximately 10 nm to approximately 40 nm, or from approximately 12 nm to approximately 25 nm.

Each field effect transistor may include a via on the source contact or the drain contact, the vias being staggered relative to the gate contact. The via may be longitudinally offset relative to the gate contact by a distance of approximately 10 nm to approximately 25 nm in a length direction of the source contact or the drain contact.

The integrated circuit may further include a shallow trench isolation region between a first transistor of the plurality of field effect transistors and a second transistor of the plurality of field effect transistors. A source or drain region of one of the field effect transistors may extend across the shallow trench isolation region and connect the first transistor to the second transistor. A via of one of the first transistor and the second transistor may be located at the shallow trench isolation region and extend across an upper surface or drain of a source region of the shallow trench isolation region. The upper surface of the polar region may include notches.

The integrated circuit may include at least one power rail at a boundary of the integrated circuit and a via connecting a source contact of one of the transistors to the at least one power rail.

In another embodiment, the integrated circuit includes a series of field effect transistors, each field effect transistor having: a source region; a drain region; and a channel region, between the source region and the drain region. extending between regions; a gate located on the channel region; a gate contact located on the gate at an active region of the gate; a source contact located on the source region; A pole contact is located on the drain region; and a via is located on the source contact or the drain contact, the via hole being staggered relative to the gate contact.

The via may be longitudinally offset relative to the gate contact by a distance of approximately 10 nm to approximately 25 nm in a length direction of the source contact or the drain contact.

The upper surface of the source contact and the upper surface of the drain contact may be separated by a depth of approximately 10 nm to approximately 40 nm below the upper surface of the gate.

The integrated circuit may include at least one power rail at a boundary of the integrated circuit and a second via connecting a source contact of one of the transistors to the power rail.

The integrated circuit may include a shallow trench isolation region between a first transistor and a second transistor, and a source or drain region of one of the field effect transistors may extend across the Shallow trench isolation regions and connect the first transistor to the second transistor.

A via of one of the first transistor and the second transistor may be located at the shallow trench isolation region and extend across an upper surface of the source region of the shallow trench isolation region Or the upper surface of the drain region may include a gap.

The invention also relates to a method of manufacturing an integrated circuit including a series of field effect transistors. In one embodiment, the method includes: forming a source contact and a drain contact on the respective source region and drain region of each field effect transistor; forming a gate electrode on the gate electrode of each field effect transistor. contacts; and forming a through hole on the source region or the drain region of each field effect transistor. The upper surface of the source contact and the upper surface of the drain contact are spaced a depth below the upper surface of the gate, and the vias are staggered relative to the gate contact.

Forming the source contact and the drain contact may include etching holes in a dielectric material on the source region and the drain region; using the source contact and the drain region; Filling the hole with material of the pole contact; and timing etching the material of the source contact and the drain contact. The timed etching may include forming grooves in the material of the source and drain contacts.

Forming the gate contact may include: depositing a second dielectric material on the gate; etching a hole through the second dielectric material to the gate; and etching a hole through the second dielectric. The holes of the electrical material are filled with metallic material.

Forming the via may include depositing a second dielectric material in the recess in the material of the source contact and the drain contact; etching a hole through the dielectric material and the drain contact; A second dielectric material reaches a hole in the material of the source contact and the drain contact; and filling the hole through the dielectric material and the second dielectric material with a metallic material.

The metal material of the through hole may be the same as or different from the material of the source contact and the drain contact.

This summary is provided to introduce a selection of features and concepts of embodiments of the invention that are further explained below in the detailed description. This Summary is not intended to identify key or critical features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. One or more of the described features may be combined with one or more other described features to provide a feasible apparatus.

The present invention relates to various embodiments of integrated circuits that include a series of field effect transistors (FETs) configured to achieve higher performance than prior art FETs. Short Contact Poly Pitch (CPP) without electrical shorting.

Hereinafter, exemplary embodiments will be explained in more detail with reference to the accompanying drawings, in which like drawing symbols refer to like elements throughout. This invention may, however, be embodied in various different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the various aspects and features of the invention to those skilled in the art. Accordingly, processes, components, and techniques that are not necessary for a person of ordinary skill in the art to fully understand the various aspects and features of the invention may not be described. Unless otherwise indicated, the same drawing symbols refer to the same elements throughout the accompanying drawings and written description, and therefore repeated description may not be necessary.

In the drawings, the relative sizes of components, layers and regions may be exaggerated and/or simplified for clarity. For ease of explanation, terms such as "beneath", "below", "lower", "under", "above" may be used herein. Spatially relative terms such as "above" and "upper" are used to describe the relationship between one element or feature shown in the figure and another (other) element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "beneath" other elements or features would then be oriented "below" or "beneath" the other elements or features. above". Thus, the exemplary terms "below" and "below" may encompass both "above" and "below" orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, These elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish between individual elements, components, regions, layers or sections. Therefore, a first element, element, region, layer or section described below could also be termed a second element, element, region, layer or section without departing from the spirit and scope of the invention.

It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, the element or layer A layer can be directly on, directly connected to, or directly coupled to another element or layer, or one or more intervening elements or layers may be present. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers. , or one or more intermediate elements or layers may also be present.

The terminology used herein is for the purpose of describing specific embodiments and is not intended to be limiting of the invention. As used herein, the singular forms "a," "a" and "an" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that when the words "comprises, comprising, includes and including" are used in this specification, they indicate the presence of stated features, integers, steps, operations, elements and/or elements, but do not exclude the presence of one or The presence or addition of multiple other features, integers, steps, operations, elements, elements, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when preceding a list of elements, modify the entire list of elements rather than modifying the individual elements in the list of elements.

As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation, not as terms of degree, and are intended to take into account measurements or calculations that would be known to one of ordinary skill in the art. Inherent changes in value. In addition, the use of "may" when describing embodiments of the present invention refers to "one or more embodiments of the present invention." As used herein, the terms "use", "using" and "used" may be deemed to be the same as the terms "utilize", "utilizing" and "being utilized" respectively. (utilized)" synonymous. Additionally, the term "exemplary" is intended to mean an example or illustration.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It should also be understood that terms (such as those defined in commonly used dictionaries) should be construed to have meanings consistent with their meaning in the context of the relevant technology and/or this specification, and should not be used unless expressly defined herein. Interpret it as having an idealized or overly formal meaning.

Referring now to FIGS. 2A to 2C , an integrated circuit 200 according to one embodiment of the present invention includes a first field effect transistor (FET) 201 (eg, n-FET or p-FET) and a second FET 202 (eg, p-FET). -FET or n-FET). In the illustrated embodiment, integrated circuit 200 further includes a first power rail 203 (eg, a power rail in an upper metal routing layer) extending along a boundary of FET 201 or 202 (eg, a boundary of first FET 201 ) and A second power rail 204 (eg, a second power rail in the upper metal routing layer) extending along the boundary of FET 201 or 202 (eg, the boundary of second FET 202). Additionally, in the illustrated embodiment, the first FET 201 and the second FET 202 are separated by a shallow trench isolation (STI) region 205 .

In the illustrated embodiment, each of FETs 201, 202 includes a source region 206 and a drain region 207, a channel region 208 extending between the source region 206 and the drain region 207, Gate oxide layer 209 on gate oxide layer 208 and gate electrode 210 on gate oxide layer 209 . Additionally, in the illustrated embodiment, each of the FETs 201, 202 includes a contact 211 (eg, directly located) on the gate 210 at the active region of the gate 210 on the channel region 208. , contact over active gate (COAG)). In the illustrated embodiment, each of the FETs 201, 202 further includes contacts 212, 213 located (eg, directly located) on the source region 206 and the drain region 207, respectively. Additionally, in the illustrated embodiment, each of the FETs 201, 202 further includes a via 214 located (eg, directly located) at the contacts connecting the source region 206 and the drain region 207 on at least one of items 212 and 213.

Figure 2B is a cross-sectional view along line 2B-2B of Figure 2A. Figure 2C is a cross-sectional view along line 2C-2C of Figure 2A. As shown in FIGS. 2B to 2C , for each of the FETs 201 and 202 , the upper surfaces 215 and 216 of the contacts 212 and 213 respectively located on the source region 206 and the drain region 207 are at the gate 210 The upper surface 217 of the top surface 217 is spaced apart (for example, the top surfaces 215 and 216 of the contacts 212 and 213 located on the source region 206 and the drain region 207 away from the source region 206 and the drain region 207 are far away from the gate 210 spaced below the top surface 217 of the channel region 208). Accordingly, the top surfaces 215, 216 of the contacts 212, 213 on the source region 206 and the drain region 207 are also spaced apart from the lower surface 218 of the contact 211 on the upper surface 217 of the gate 210 (eg, The upper surfaces 215 and 216 of the contacts 212 and 213 located on the source region 206 and the drain region 207 are lower than the interfaces 217 and 218 between the gate 210 and the contacts 211 located on the gate 210). Space the upper surfaces 215 and 216 of the contacts 212 and 213 on the source region 206 and the drain region 207 under the upper surface 217 of the gate 210 and the lower surface 218 of the contact 211 on the gate 210 Opening enables a shorter contact poly pitch (CPP) compared to prior art ICs (e.g., a shorter pitch between adjacent gates 210 of IC 200 ) without creating a gap between adjacent gates 210 in source region 206 And an electrical short circuit is caused between the contacts 212 and 213 on the drain region 207 and the contact 211 located on the active region of the gate 210. In addition, the upper surfaces 215 and 216 of the contacts 212 and 213 located on the source region 206 and the drain region 207 are placed under the upper surface 217 of the gate 210 and the contact 211 located above the active area of the gate 210 The spacing under the lower surface 218 can reduce the Miller capacitance between the contacts 212, 213 and the gate 210 compared to the prior art FET, which is located in the source and drain regions. The upper surface of the contact is not lower than the upper surface of the gate.

In one or more embodiments, the upper surfaces of the contacts 212, 213 on the source region 206 and the drain region 207 are spaced approximately 100 degrees below the lower surface 218 of the contact 211 on the active region of the gate 210. A distance D (e.g., depth) of 10 nm to approximately 40 nm (e.g., upper surfaces 215, 216 of contacts 212, 213 located on source region 206 and drain region 207 are spaced below upper surface 217 of gate 210 Open a distance D) of approximately 10 nm to approximately 40 nm. In one or more embodiments, the upper surfaces 215 and 216 of the contacts 212 and 213 on the source and drain regions 206 and 207 are under the lower surface 218 of the contact 211 on the active area of the gate 210 are separated by a distance (eg, depth) of approximately 12 nm to approximately 25 nm (eg, upper surfaces 215 , 216 of contacts 212 , 213 on source region 206 and drain region 207 are on gate 210 The lower surface 218 of the contacts 211 is spaced apart by a distance D) of approximately 12 nm to approximately 25 nm. In one or more embodiments, the contacts 212, 213 located on the source region 206 and the drain region 207 have a height H of approximately 2 nm to approximately 10 nm. In one or more embodiments, contacts 212, 213 on source region 206 and drain region 207 may be formed from a silicide metal (eg, titanium (Ti), cobalt (Co), or nickel (Ni)).

As shown in FIG. 2A , for each of the FETs 201 , 202 , a via 214 on one of the contacts 212 , 213 on the source region 206 and the drain region 207 is opposite to the one on the gate. Contacts 211 on the active area of gate 210 are staggered (eg, offset diagonally) such that the vias are not laterally aligned with contacts 211 on the active area of gate 210 . For example, as shown in FIG. 2A , for each of FETs 201 , 202 , contacts 211 on the active region of gate 210 are in contact with corresponding power rails 203 , 204 along the length of gate 210 . are longitudinally spaced a first distance L ₁ , and the vias 214 are spaced apart from the respective power rails 203 , 204 along the length of the contact 212 or 213 by a second distance L ₂ that is greater than the first distance L ₁ (e.g., for For each FET 201, 202, the vias 214 are spaced closer to the STI region 205 of the integrated circuit 200 than the contacts 211 on the active region of the gate 210). In one or more embodiments, the contact 211 located on the active area of the gate 210 may be longitudinally spaced apart from the via 214 along the length of the contact 212 or 213 by a third distance of approximately 10 nm to approximately 25 nm. _L3 . Staggering the vias 214 and the contacts 211 on the active area of the gate 210 so that the vias 214 are not laterally aligned with the contacts 211 on the active area of the gate 210 can achieve better performance than prior art FETs. A short CPP (eg, a shorter spacing between adjacent gates 210 of the integrated circuit 200 ) without causing an electrical short between the via 214 and the contact 211 located on the active area of the gate 210 . For example, in one or more embodiments, the integrated circuit 200 of the present invention may have a CPP of less than approximately 48 nm (eg, approximately 40 nm or less than 40 nm).

Referring now to FIG. 3 , in one or more embodiments, each of FETs 201 , 202 of integrated circuit 200 may include vias 219 , 220 that will be located in source region 206 and drain region 206 , respectively. One of the contacts 212, 213 on the source region 207 is connected to one of the power rails 203, 204 (e.g., vias 219, 220 from the contacts 212, 213 on the source region 206 and drain region 207 The upper surfaces 215, 216 of 213 extend to power rails 203, 204) located in one of the upper metal routing layers (eg, the upper metal routing layer).

In the embodiment of the integrated circuit 200 shown in FIGS. 2A and 3 , one of the contacts 212 , 213 located on one of the source region 206 and the drain region 207 is above the STI region 205 (eg, , extending across the STI region 205) and connecting the first FET 201 and the second FET 202 together. Referring now to FIG. 4 , one of the contacts 212 , 213 located on one of the source region 206 and the drain region 207 extends over the STI region 205 and connects the first FET 201 and the second FET 202 In one or more embodiments connected together, one of vias 214 (eg, via 214 of first FET 201 ) may be located on contact 213 in STI region 205 . Additionally, in the illustrated embodiment, the portion of gate 210 located in STI region 205 includes grooves 221 located in upper surface 217 of gate 210 . In the side view of FIG. 4 , the groove 221 in the upper surface 217 of the gate 210 is located below the via 214 on the contact 213 in the STI region 205 (e.g., the via 214 on the contact 213 is not the same as the via 214 in the gate 210 The grooves 221 are longitudinally aligned along the length direction of the contact 213 and the gate 210). The groove 221 located in the portion of the gate 210 below the via 214 in the STI region 205 is used to improve the process margin between the via 214 and the gate 210 .

5 is a flowchart illustrating various tasks of a method of fabricating an integrated circuit including a plurality of FETs according to one embodiment of the present invention. In the illustrated embodiment, method 300 includes the task 310 of forming contacts on the source and drain regions of each of the FETs. The task of forming contacts 310 may be performed using a self-aligned contact (SAC) process. In one or more embodiments, the task of forming contacts 310 on the source and drain regions may include depositing a cap (eg, nitride) over the gate of each of the FETs. cap); etching holes through the dielectric material (e.g., oxide material on the source and drain regions) to the underlying source and drain regions; using contact material (e.g., cobalt ( Co), ruthenium (Ru), copper (Cu), or tungsten (W)) to fill the holes; perform a chemical mechanical planarization (CMP) process on the contact material filled in the holes of the dielectric material ; and performing a timed groove etch on the contact material that fills the hole in the dielectric material to recess the material to a desired depth. A timed recess etch of the contact material filling the holes in the dielectric material is selective to the dielectric material on the source and drain regions and to the cap (e.g., nitride cap) on the gate. materials are selective.

In the illustrated embodiment, for each of the FETs of the integrated circuit, the method 300 further includes the task 320 of forming a via in at least one of the contacts located on the source region and the drain region. and the task of forming contacts on the gate 330 . The tasks 320, 330 of forming vias on the contacts in the source and drain regions and forming contacts on the gate may be performed by depositing a second dielectric material (e.g., different from the nitride cap on the gate). oxide) to fill the grooves formed in the contact material during the task of forming the contacts 310 . The tasks 320, 330 of forming vias on the contacts in the source and drain regions and forming contacts on the gate may also include forming via openings in the dielectric material to the underlying contact material (e.g., , the lithography process used to pattern the via openings and the etching used to form the via openings through the dielectric material to the underlying contact material); and in the dielectric material located on the gate (e.g., oxidation and nitride cap) (eg, a lithography process to pattern the contact openings and an etch to form the contact openings through the dielectric material to the underlying gate). In one or more embodiments, the tasks 320, 330 of forming vias on the contacts in the source and drain regions and forming contacts on the gates may include depositing metal in the via openings and contact openings ( For example, Co, Ru, Cu or tungsten (W)). In one or more embodiments, the metallic material deposited in the via opening may be the same as the metallic material deposited in the contact opening, but in one or more embodiments, the metallic material deposited in the via opening may be Unlike the metallic material deposited in the contact opening. Therefore, the vias on the contacts in the source and drain regions may be formed of the same metal or a different metal than the contacts on the gate.

After task 310 of forming contacts on the source and drain regions for each of the FETs of the integrated circuit, the upper surfaces of the contacts located on the source and drain regions are on the upper surface of the gate. (eg, the upper surfaces of the contacts may be spaced apart below the upper surface of the gate by a depth of approximately 10 nm to approximately 40 nm (eg, approximately 12 nm to approximately 25 nm)). Additionally, after task 330 of forming contacts on the gate, the upper surfaces of the contacts on the source and drain regions are spaced below the lower surfaces of the contacts on the upper surface of the gate (e.g., on the source The upper surfaces of the contacts on the pole and drain regions may be spaced apart from the lower surface of the contacts on the gate by a depth of approximately 10 nm to approximately 40 nm (eg, approximately 12 nm to approximately 25 nm). As described above, by spacing the upper surfaces of the contacts on the source and drain regions under the upper surface of the gate and the lower surface of the contacts on the gate, it is possible to achieve the same effect as the conventional integrated circuit. Compared to the shorter contact polysilicon pitch (CPP), no electrical shorts are created between the contacts located on the source and drain regions and the contacts located on the active area of the gate. The upper surfaces of the contacts over the source and drain regions are also spaced below the upper surface of the gate and under the lower surface of the contacts over the active region of the gate, thereby being consistent with prior art FETs. To reduce the Miller capacitance between the contact and the gate, in the prior art FET, the upper surface of the contact located on the source region and the drain region is not lower than the upper surface of the gate.

Additionally, after the tasks 320, 330 of forming a via on one of the contacts in the source and drain regions and the contact on the gate, align the via with respect to the contact on the active area of the gate. Staggered (e.g., offset diagonally) so that vias are not laterally aligned with contacts located on the active area of the gate (e.g., contacts located on the active area of the gate may be aligned along the length of the gate) direction spaced approximately 10 nm to approximately 25 nm longitudinally from the via). As described above, the vias on the contacts in one of the source and drain regions are staggered relative to the contacts on the active area of the gate such that the vias are aligned with the contacts on the active area of the gate. The lack of lateral alignment of the contacts enables a shorter CPP compared to prior art integrated circuits without causing an electrical short between the via and the contacts located on the active area of the gate.

While the present invention has been described in detail with specific reference to its exemplary embodiments, the exemplary embodiments described herein are not intended to be exhaustive or to limit the scope of the invention to the precise form disclosed. It will be understood by those skilled in the art and technology to which the present invention belongs that modifications to the structure and methods of assembly and operation may be practiced without materially departing from the principle, spirit and scope of the invention as set forth in the above claims. and change form.

100‧‧‧Prior technology cell architecture/unit/standard cell architecture/prior technology standard cell architecture 101, 102‧‧‧Field effect transistor 103, 104, 211, 212, 213‧‧‧Contacts 105, 206‧‧‧ Source area 106, 207‧‧‧Drain area 107‧‧‧Contact/Gate contact 108, 210‧‧‧Gate 109, 110, 111‧‧‧Upper surface 112‧‧‧ above the active area Thick Nitride Spacer/Thick Spacer 200‧‧‧Integrated Circuit 201‧‧‧First Field Effect Transistor/First FET/FET202‧‧‧Second Field Effect Transistor/Second FET/FET203‧ ‧‧First power rail/power rail 204‧‧‧Second power rail/power rail 205‧‧‧Shallow trench isolation area (STI area) 208‧‧‧Trench area 209‧‧‧Gate oxide layer 214 , 219, 220‧‧‧Through hole 215, 216‧‧‧Upper surface/Top surface 217‧‧‧Upper surface/Top surface/Interface 218‧‧‧Lower surface/Interface 221‧‧‧Groove 300‧‧‧Method 310, 320, 330‧‧‧Task 1B-1B, 2B-2B, 2C-2C‧‧‧Line D‧‧‧Distance H‧‧‧Height L ₁ ‧‧‧First distance L ₂ ‧‧‧Second distance L ₃ ‧‧‧Third distance

These and other features and advantages of embodiments of the present invention will become more apparent by referring to the following detailed description in conjunction with the following drawings. In the drawings, the same drawing symbols are used throughout the drawings to refer to the same features and components. Figures are not necessarily drawn to scale. 1A to 1B are layout diagrams and cross-sectional views of a prior art integrated circuit. 2A to 2C are respectively a layout diagram and a cross-sectional view of an integrated circuit according to an embodiment of the present invention. Figure 3 is a layout diagram of an integrated circuit according to one embodiment of the present invention. Figure 4 is a cross-sectional view of an integrated circuit according to one embodiment of the present invention. 5 is a flowchart illustrating various tasks of a method of manufacturing an integrated circuit according to one embodiment of the present invention.

200‧‧‧Integrated Circuit

201‧‧‧The first field effect transistor/the first FET/FET

202‧‧‧Second field effect transistor/second FET/FET

203‧‧‧First power rail/power rail

204‧‧‧Second Power Rail/Power Rail

205‧‧‧Shallow trench isolation area (STI area)

206‧‧‧Source region

207‧‧‧Drainage area

208‧‧‧Channel Area

210‧‧‧Gate

211, 212, 213‧‧‧Contacts

214, 219, 220‧‧‧Through hole

Claims (10)

An integrated circuit includes: a plurality of field effect transistors, each field effect transistor including: a source region; a drain region; a channel region extending between the source region and the drain region; and a gate. The gate electrode is located on the channel area; the gate contact is located on the gate at the active area of the gate; the source contact is located on the source area; the drain contact is located on the gate. on the drain region; and vias on the source contact or the drain contact, wherein the vias are staggered relative to the gate contacts such that the vias are in plan view Not aligned laterally with the gate contact, wherein the via is longitudinally offset by 10 nm relative to the gate contact along the length of the source contact or the drain contact to a distance of 25 nm. The integrated circuit as claimed in claim 1, wherein the upper surface of the source contact and the upper surface of the drain contact are spaced apart by a depth below the upper surface of the gate. As for the integrated circuit described in item 2 of the patent application, the depth is from 10 nanometers to 40 nanometers. The integrated circuit described in item 1 of the patent application scope further includes: At least one power rail located at a boundary of the integrated circuit; and a second via connecting the source contact of one of the plurality of field effect transistors to the at least one power rail. An integrated circuit includes: a plurality of field effect transistors, each field effect transistor including: a source region; a drain region; a channel region extending between the source region and the drain region; and a gate. The gate electrode is located on the channel area; the gate contact is located on the gate at the active area of the gate; the source contact is located on the source area; the drain contact is located on the gate. on the drain region; and vias on the source contact or the drain contact, wherein the vias are staggered relative to the gate contacts; and shallow trench isolation regions on between a first transistor of the plurality of field effect transistors and a second transistor of the plurality of field effect transistors, wherein the source of one of the plurality of field effect transistors A region or the drain region extends across the shallow trench isolation region and connects the first transistor to the second transistor. The integrated circuit as claimed in claim 5, wherein the through hole of one of the first transistor and the second transistor is located in the shallow trench spacer. away from the region, and wherein the upper surface of the source region or the upper surface of the drain region extending across the shallow trench isolation region includes a gap. The integrated circuit of claim 5, wherein the upper surface of the source contact and the upper surface of the drain contact are spaced apart by a depth below the upper surface of the gate. A method of manufacturing an integrated circuit including a plurality of field effect transistors, including: forming a source contact on a respective source region and a drain region of each field effect transistor in the plurality of field effect transistors; a drain contact; forming a gate contact on the gate of each field effect transistor in the plurality of field effect transistors; and the gate contact in each field effect transistor in the plurality of field effect transistors. A through hole is formed in the source region or the drain region, wherein the upper surface of the source contact and the upper surface of the drain contact are spaced apart by a depth below the upper surface of the gate, and wherein The vias are staggered relative to the gate contact such that the vias are not laterally aligned with the gate contact in plan view, wherein the vias are located between the source contact or the gate contact. The length direction of the drain contact is longitudinally offset relative to the gate contact by a distance of 10 nm to 25 nm. The method of manufacturing an integrated circuit including a plurality of field effect transistors as described in claim 8, wherein forming the source contact and the drain contact includes: Etching holes in the dielectric material on the source and drain regions; filling the holes with material of the source and drain contacts; and configuring the source contacts The material of the source contact and the drain contact is timed etched, the timed etching forming grooves in the material of the source contact and the drain contact. The method of manufacturing an integrated circuit including a plurality of field effect transistors as described in claim 9, wherein forming the gate contact includes: depositing a second dielectric material on the gate; etching a through hole; a hole through the second dielectric material to the gate; and filling the hole through the second dielectric material with a metallic material.