TWI810791B - Manufacturing method of memory device using pillar-shaped semiconductor element - Google Patents

Abstract

In a manufacturing method of a dynamic flash memory which performs a data holding operation of holding an electric hole group generated by impact ionization phenomenon inside Si pillars 12a to 12d and a data erase operation of removing the electric hole group from inside the Si pillars 12a to 12d by controlling the voltage applied to a source line SL, a plate line PL, word lines WL1, WL2 and bit lines BL1, BL2, a N+ layer 11a which is connected to the source line SL located at one end of the Si pillars 12a to 12d standing in the vertical direction, a N+ layer 13a to 13d which is connected to the bit lines BL1 and BL2 located at the other end of Si pillars 12a to 12d, a TiN layer 18 which is connected to the plate line PL and surrounds a gate HfO2 layer 17a surrounding the Si pillars 12a to 12d and is continuous between the Si pillars 12a to 12d, and TiN layers 26a and 26b which surrounds a gate HfO2 layer 17b surrounding the Si pillars 12a to 12d and is connected to the word lines WL1, WL2 are formed on a substrate 10, wherein a SiO2 layer 23a between them is formed by selectively depositing a SiGe layer on the TiN layer 18 and then oxidizing the SiGe layer.

Description

Manufacturing method of memory device using columnar semiconductor element

The present invention relates to a manufacturing method of a memory device using a columnar semiconductor element.

In recent years, in the development of LSI (Large Scale Integration; large-scale integrated circuit) technology, the pursuit of high-integration and high-performance memory components has been pursued.

In a common planar MOS transistor, the channel extends horizontally along the upper surface of the semiconductor substrate. On the other hand, the channel of the SGT (Surrounding Gate Transistor; Surrounding Gate Transistor) extends in a direction perpendicular to the upper surface of the semiconductor substrate (see, for example, Patent Document 1 and Non-Patent Document 1). Therefore, compared with planar MOS transistors, SGT can achieve higher density of semiconductor devices. Using this SGT as a selection transistor, a DRAM (Dynamic Random Access Memory; dynamic random access memory; refer to, for example, Non-Patent Document 2) connected with a capacitor, and a PCM (Phase Change Memory; For phase change memory, see, for example, Non-Patent Document 3), RRAM (Resistive Random Access Memory; resistive random access memory, see, for example, Non-Patent Document 4), using current to change the direction of the spin magnetic moment to change the resistance MRAM (Magneto-resistive Random Access Memory; Magneto-resistive Random Access Memory, refer to, for example, Non-Patent Document 5) and other high-level integration. In addition, there is also a DRAM memory cell composed of a single MOS transistor that does not have a capacitor (see Non-Patent Documents 6 and 7). This case relates to a dynamic flash memory (Dynamic Flash Memory) that can only be composed of MOS transistors without resistance variable elements, capacitors, etc.

Fig. 9 shows the writing operation of the aforementioned DRAM memory cell composed of a MOS transistor without capacitance, Fig. 10 shows the problems in the operation, and Fig. 11 shows the reading operation (refer to non-patent documents 7~10) .

FIG. 9 shows the writing operation of a DRAM memory cell. Figure 9(a) shows the state of writing "1". Here, the memory cell is formed on an SOI (silicon-on-insulator) substrate 100, with a source N ⁺ layer 103 connected to the source line SL (hereinafter, the semiconductor region containing high-concentration donor impurities is referred to as "N ⁺ layer"), the drain N ⁺ layer 104 connected to the bit line BL, the gate conductive layer 105 connected to the word line WL, and the floating body (Floating Body) 102 of the MOS transistor 110a, without capacitance, And a MOS transistor 110a constitutes a memory cell of the DRAM. Also, the SiO ₂ layer 101 of the SOI substrate is in contact with the floating body 102 directly below. When writing "1" into a memory cell constituted by one MOS transistor 110a, the MOS transistor 110a is operated in a saturation region. That is, the channel 107 for electrons extending from the source N ⁺ layer 103 has a pinch point 108 and does not reach the drain N ⁺ layer 104 connected to the bit line. In this way, if the bit line BL connected to the drain N ⁺ layer 104 and the word line WL connected to the gate conductive layer 105 are both high voltage, the gate voltage is about 1/2 of the drain voltage. When the MOS transistor 110a is operated, the electric field intensity becomes maximum at the pinch point 108 near the drain N ⁺ layer 104 . As a result, the accelerated electrons flowing from the source N ⁺ layer 103 toward the drain N ⁺ layer 104 collide with the crystal lattice of Si, and electron-hole pairs are generated by the kinetic energy lost at that point. Most of the generated electrons (not shown) reach the drain N ⁺ layer 104 . In addition, a very small part of the very hot electrons passes through the gate oxide film 109 to reach the gate conductive layer 105 . In addition, the electric holes 106 generated at the same time charge the floating body 102 . At this time, since the floating body 102 is P-type Si, the generated holes contribute to the increase of majority carriers. When the floating body 102 is filled with the generated holes 106 so that the voltage of the floating body 102 is higher than that of the source N ⁺ layer 103 to be above Vb, the further generated holes will discharge the source N ⁺ layer 103 . Here, Vb is the built-in voltage of the PN junction between the source N ⁺ layer 103 and the floating body 102 of the P layer, which is about 0.7V. FIG. 9( b ) shows the situation that the floating body 102 has been saturated charged by the generated electric holes 106 .

Next, the operation of writing "0" in the memory cell 110 will be described using FIG. 9( c ). For the common selected word line WL, there are randomly present a memory cell 110a in which “1” is written and a memory cell 110b in which “0” is written. FIG. 9( c ) shows the situation of rewriting from the state of writing "1" to the state of writing "0". When writing "0", the voltage of the bit line BL is negatively biased, and the PN junction between the drain N ⁺ layer 104 and the floating body 102 of the P layer is forward biased. As a result, the hole 106 generated in the floating body 102 in the previous cycle flows to the drain N ⁺ layer 104 connected to the bit line BL. If the writing operation ends, two kinds of memory cells 110a ( FIG. 9( b )) filled with the generated holes 106 and memory cells 110 b ( FIG. 9 ( c )) in which the generated holes have been discharged are obtained. The state of the memory cell. The potential of the floating body 102 of the memory cell 110a filled with the holes 106 is higher than that of the floating body 102 without the generated holes. Therefore, the threshold voltage of the memory cell 110a is lower than the threshold voltage of the memory cell 110b, which is the situation shown in FIG. 9( d ).

Next, problems in the operation of such a memory cell composed of one MOS transistor will be described with reference to FIG. 10 . As shown in FIG. 10( a ), the capacitance C _FB of the floating body 102 is the sum of the capacitance C _WL , the junction capacitance C _SL and the junction capacitance C _BL , as shown in the following equation (1).

C _FB =C _WL +C _BL +C _SL (1)

Wherein, the capacitance C _WL is the capacitance connected between the gate of the word line and the floating body 102, and the junction capacitance C _SL is the PN junction connected between the source N ⁺ layer 103 of the source line and the floating body 102. The junction capacitance of the surface, the junction capacitance C _BL is the junction capacitance of the PN junction connected between the drain N ⁺ layer 104 of the bit line and the floating body 102 . Therefore, if the word line voltage V _WL oscillates during writing, the voltage of the floating body 102 which becomes the memory node (Node) of the memory cell will also be affected by it, as shown in FIG. 10( b ). If the word line voltage V _WL rises from 0V to V _ProgWL during writing, the voltage V _FB of the floating body 102 rises from the initial voltage V _FB1 before the word line voltage changes due to the capacitive coupling of the word line. high to V _FB2 . The amount of voltage change ΔV _FB is expressed in the following formula (2).

△V _FB =V _FB2 -V _FB1 =C _WL /(C _WL +C _BL +C _SL )×V _ProgWL (2)

Here, as shown in the following formula (3),

β=C _WL /(C _WL +C _BL +C _SL ) (3)

When C _WL /(C _WL +C _BL +C _SL ) in the formula (2) is expressed as β, β is called a coupling ratio. In this kind of memory unit, the contribution rate of C _WL is relatively large, for example, C _WL : C _BL : C _SL =8:1:1. At this time, β=0.8. For example, if the word line is 5V during writing and becomes 0V after writing, the floating body 102 will suffer oscillation noise of 5V×β=4V due to the capacitive coupling between the word line and the floating body 102 . Therefore, there is a problem in that the margin of difference between the potential difference between the "1" potential and the "0" potential of the floating body 102 at the time of writing cannot be sufficiently obtained.

Fig. 11 shows the read operation, Fig. 11(a) shows the state of writing "1", and Fig. 11(b) shows the state of writing "0". However, in fact, even if Vb is written into the floating body 102 by writing "1", when the word line returns to 0V due to the end of writing, the floating body 102 will drop to a negative bias. to write In case of "0", since the negative bias becomes even more negative, the difference margin of the potential difference between "1" and "0" cannot be sufficiently increased at the time of writing. For this DRAM memory cell, such a small difference in motion becomes a major problem. In addition, there is a problem of increasing the density of this DRAM memory cell.

In addition, there are also memory elements that use two MOS transistors in the SOI (Silicon on Insulator; silicon-on-insulator) layer to form a memory cell (see, for example, patent documents 4 and 5, which are incorporated herein by these references (by these references) These references are hereby incorporated)). In these devices, the N ⁺ layer that separates the floating body channels of the two MOS transistors and becomes the source or drain is formed in contact with the insulating layer. By connecting the N ⁺ layer with the insulating layer, the floating body channels of the two MOS transistors are electrically separated from each other. Therefore, as mentioned above, the voltage of the separated floating body channel that accumulates the hole group belonging to the signal charge will be different from that shown in the formula (2) due to the pulse voltage applied to the gate electrode of each MOS transistor. Same big change. Therefore, there is a problem that the difference margin of the potential difference between "1" and "0" at the time of writing cannot be sufficiently increased.

[Prior Art Literature]

[Patent Document]

[Patent Document 1] Japanese Patent Application Laid-Open No. 2-188966

[Patent Document 2] Japanese Patent Application Laid-Open No. 3-171768

[Patent Document 3] Japanese Patent No. 3957774

[Patent Document 4] US2008/0137394 A1

[Patent Document 5] US2003/0111681 A1

[Non-patent literature]

[Non-Patent Document 1] Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol.38, No.3, pp.573-578 (1991) .

[Non-Patent Document 2] H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, K. Dong, J. Kim, Y.C. Oh, Y. Hwang, H. Hong, G. Jin, and C. Chung: “4F2 DRAM Cell with Vertical Pillar Transistor(VPT),” 2011 Proceeding of the European Solid-State Device Research Conference, (2011).

[Non-Patent Document 3] H. S. Philip Wong, S. Raoux, S. Kim, Jiale Liang, J. R. Reifenberg, B. Rajendran, M. Asheghi and K. E. Goodson: “Phase Change Memory,” Proceeding of IEEE, Vol.98, No. 12, December, pp.2201-2227 (2010).

[Non-Patent Document 4] T. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama: “Low Power and high Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3V,” IEDM (2007).

[Non-Patent Document 5] W. Kang, L. Zhang, J. Klein, Y. Zhang, D. Ravelosona, and W. Zhao: “Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology,” IEEE Transaction on Electron Devices, pp.1-9 (2015).

[Non-Patent Document 6] M. G. Ertosum, K. Lim, C. Park, J. Oh, P. Kirsch, and K. C. Saraswat: “Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electron,” IEEE Electron Device Letter, Vol. 31, No.5, pp.405-407 (2010).

[Non-Patent Document 7] J. Wan, L. Rojer, A. Zaslavsky, and S. Critoloveanu: “A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration,” Electron Device Letters, Vol. 35, No.2, pp.179-181 (2012).

[Non-Patent Document 8] T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi: “Memory design using a one-transistor gain cell on SOI,” IEEE JSSC, vol.37, No.11, pp1510-1522 (2002).

[Non-Patent Document 9] T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F. Matsuoka, Y. Kajitani, R. Fukuda, Y. Watanabe, Y. Minami, A. Sakamoto, J. Nishimura, H. Nakajima, M. Morikado, K. Inoh, T. Hamamoto, A. Nitayama: “Floating Body RAM Technology and its Scalability to 32nm Node and Beyond,” IEEE IEDM ( 2006).

[Non-Patent Document 10] E. Yoshida: "A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory," IEEE IEDM (2006).

[Non-Patent Document 11] E. Yoshida, and T. Tanaka: “A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory,” IEEE Transactions on Electron Devices, Vol. 53, No. 4, pp. 692-697, Apr. 2006.

[Non-Patent Document 12] A. Veloso, et al.: "Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits" IEDM19 Digest Papers, pp.230 -233, 2019.

In a transistor-type DRAM (gain unit) that uses an SGT memory device and has no capacitance, the capacitive coupling between the word line and the floating SGT substrate is large, and the word line is used when reading and writing data. When the potential of the SGT oscillates, there is a problem that is regarded as noise transmitted to the SGT substrate. Therefore, it will cause the problem of misreading and miswriting memory data, and it is difficult to realize the practical application of a transistor-type DRAM (gain unit) without capacitance. Therefore, it is necessary to solve the above-mentioned problems and increase the density of DRAM memory cells.

In order to solve the above-mentioned problems, in the method of manufacturing a memory device using a columnar semiconductor element of the present invention, it is a method of manufacturing a memory device that performs a data holding operation and a data erasing operation. The data holding operation is controlled and applied to the first gate. The voltage of the conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region keeps the hole groups formed due to the impact free phenomenon or the drain leakage current caused by the gate inside the first semiconductor column, The data erasing operation is controlled and applied to the first gate conductor layer, the second gate conductor layer, and the first impurity region domain and the voltage of the aforementioned second impurity region, the aforementioned hole group is removed from the inside of the aforementioned first semiconductor column, and the manufacturing method has:

A step of forming the aforementioned first semiconductor pillars standing vertically on the substrate;

a step of forming a first gate insulating layer surrounding the sides of the aforementioned first semiconductor pillar;

The step of forming the first gate conductor layer, the first gate conductor layer surrounds the side surface of the first gate insulating layer, and its upper surface is located below the top of the first semiconductor pillar;

A step of selectively forming a first material layer made of conductor or semiconductor on the aforementioned first gate conductor layer;

A step of oxidizing the surface layer or the whole of the aforementioned first material layer to form a first oxide insulating layer;

A step of forming a second gate insulating layer on the side of the first semiconductor pillar above the first oxide insulating layer in the vertical direction;

a step of forming the aforementioned second gate conductor layer in a manner surrounding the side surfaces of the aforementioned second gate insulating layer;

Before forming the first semiconductor pillar or after forming the first semiconductor pillar, a step of forming the first impurity region connected to the bottom of the first semiconductor pillar; and

A step of forming the aforementioned second impurity region on top of the aforementioned semiconductor column before forming the aforementioned first semiconductor column or after forming the aforementioned first semiconductor column (first invention).

In the above-mentioned first invention, there is a step of forming the second gate insulating layer so as to connect the side surface of the first semiconductor pillar and the first oxide insulating layer in the vertical direction (second invention).

In the above-mentioned first invention, there are: after forming the first oxide insulating layer, exposing the side surfaces of the first semiconductor pillars above the first material layer; and oxidizing the exposed side surfaces of the semiconductor pillars. And the step of forming the aforementioned second gate insulating layer (the third invention).

In the above-mentioned first invention, there are: after forming the first material layer, exposing the side surfaces of the first semiconductor pillars above the first material layer; and oxidizing the first material layer to form the A step of first oxidizing the insulating layer, and oxidizing the exposed side surfaces of the semiconductor pillars to form a second insulating oxide layer, and using the second insulating oxide layer as the second gate insulating layer (the fourth invention).

In the above fourth invention, there is a step of forming a first insulating layer after forming the second oxide insulating layer, the first insulating layer surrounds the side surface of the second oxide insulating layer and is connected to the first insulating oxide layer. layer, and the second gate insulating layer is formed by the second oxide insulating layer and the first insulating layer (fifth invention).

In the above-mentioned first invention, there is a step of leaving the first gate insulating layer above the first insulating oxide layer in the vertical direction, and then forming the second gate conductor layer. The first gate insulating layer above the first insulating oxide layer is used as the second gate insulating layer (sixth invention).

In the above-mentioned first invention, there is a step of forming a first conductor layer after forming the second gate insulating layer, the first conductor layer surrounds the second gate insulating layer, and its upper surface is at the position of the first Near the lower end of the second impurity region; a step of selectively forming a second material layer made of a conductor or a semiconductor on the first conductor layer; and oxidizing the surface layer or the entirety of the aforementioned second material layer to form a second oxide insulating layer The steps (the seventh invention).

In the above first invention, the first material layer is formed of silicon germanium (SiGe) (eighth invention).

In the first invention described above, the wiring connected to the first impurity region is a source line, the wiring connected to the second impurity region is a bit line, and the wiring connected to the first gate conductor layer and One of the wirings connected to the second gate conductor layer is a word line, and the other is a first drive control line, and by applying to the source line, the bit line, and the first drive control line and the voltage of the aforementioned word line, and perform the aforementioned data erasing action and the aforementioned data holding action (the ninth invention).

In the above first invention, the first gate capacitor between the first gate conductor layer and the first semiconductor pillar is formed to be larger than the second gate capacitor between the second gate conductor layer and the first semiconductor pillar. The pole capacitance is large (the tenth invention).

1,10,100: Substrate

2, 12a, 12b, 12c, 12d: Si column

3a, 3b, 11a, 13, 13a, 13b, 13c, 13d: N ⁺ layers

4a: The first gate insulating layer

4b: The second gate insulating layer

5a: The first gate conductor layer

5b: The second gate conductor layer

6: Insulation layer

7: Channel area

7a: The first channel area

7b:Second channel area

9: Dynamic flash memory unit

11: Electric hole group

12: P layer

12a, 12b: Inversion layer

13: pinch point

14a, 14b, 14c, 14d: mask material layer

17, 17a, 17b, 44: HfO ₂ layers

18, 26a, 26b: TiN layer

23, 23c, 25: SiGe layer

23a, 25a, 25b, 33, 40a, 40b, 40c, 40d, 42a, 42b, 42c, 42d, 43: SiO ₂ layers

27a, 27b: SiN layer

30a, 30b, 30c, 30d: contact holes

32a: conductor layer of bit line BL1

32b: conductor layer of bit line BL2

31aa, 31ab, 31ac, 31ba, 31bb, 31bc, 31ca, 31cb, 31cc, 34a, 34b, 34c: empty holes

102: floating body

103: Source N ⁺ layer

104: drain N ⁺ layer

105: Gate conductive layer

106: electric hole

107: channel

108: pinch point

109:Gate oxide film

110a: MOS transistor, memory unit

BL, BL1, BL2: bit lines

PL: plate line

SL: source line

WL,WL1,WL2: word line

FIG. 1 is a structural diagram of a memory device with SGT in the first embodiment.

FIG. 2 is a diagram illustrating the erase operation mechanism of the memory device with SGT in the first embodiment.

FIG. 3 is a diagram for explaining the write operation mechanism of the memory device with SGT in the first embodiment.

FIG. 4A is a diagram for explaining the read operation mechanism of the memory device with SGT in the first embodiment.

FIG. 4B is a diagram for explaining the read operation mechanism of the memory device having the SGT of the first embodiment.

FIG. 5A is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5B is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5C is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5D is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5E is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5F is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5G is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5H is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5I is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5J is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5K is a schematic structural diagram of a memory device with SGT in the first embodiment.

FIG. 6 is a diagram illustrating a method of manufacturing a memory device having an SGT according to the second embodiment.

FIG. 7A is a diagram illustrating a method of manufacturing a memory device having an SGT according to the third embodiment.

FIG. 7B is a diagram illustrating a method of manufacturing a memory device having an SGT according to the third embodiment.

FIG. 7C is a diagram illustrating a method of manufacturing a memory device with SGT in the third embodiment.

FIG. 8A is a diagram illustrating a method of manufacturing a memory device with SGT in the fourth embodiment.

FIG. 8B is a diagram illustrating a method of manufacturing a memory device with SGT in the fourth embodiment.

FIG. 9 is a diagram for explaining problems in the operation of a conventional DRAM memory cell without capacitance.

FIG. 10 is a diagram for explaining problems in the operation of a conventional DRAM memory cell without capacitance.

FIG. 11 is a diagram showing a read operation of a conventional DRAM memory cell without capacitance.

A method of manufacturing a memory device (hereinafter referred to as a dynamic flash memory) using a semiconductor device according to the present invention will be described below with reference to the drawings.

(first implementation type)

1 to 5, the structure, operation mechanism and manufacturing method of the dynamic flash memory unit of the first embodiment of the present invention will be described. Use Fig. 1 to illustrate the structure of the dynamic flash memory unit. In addition, FIG. 2 is used to illustrate the data erasing mechanism, FIG. 3 is used to illustrate the data writing mechanism, FIG. 4 is used to illustrate the data writing mechanism, and FIG. 5 is used to illustrate the manufacturing method of the dynamic flash memory.

FIG. 1 shows the structure of the dynamic flash memory unit of the first embodiment of the present invention. N ⁺ layer 3a is formed at the upper and lower positions inside the p-type or i-type (intrinsic) conductivity type silicon semiconductor column 2 (hereinafter referred to as "Si column") formed on the substrate 1 , 3b, when one of the N ⁺ layers 3a, 3b is the source, the other is the drain. The portion of the Si column 2 between the N ⁺ layer 3 a and the N ⁺ layer 3 b serving as the source and the drain serves as the channel region 7 . A first gate insulating layer 4 a and a second gate insulating layer 4 b are formed to surround the channel region 7 . The first gate insulating layer 4a and the second gate insulating layer 4b are respectively in contact with or close to the N ⁺ layer 3a and N ⁺ layer 3b which become the source and drain. A first gate conductor layer 5 a and a second gate conductor layer 5 b are respectively formed to surround the first gate insulating layer 4 a and the second gate insulating layer 4 b. Moreover, the first gate conductor layer 5 a and the second gate conductor layer 5 b are separated by an insulating layer 6 . Moreover, the channel region 7 of the part of the Si column 2 between the N ⁺ layer 3a and the N ⁺ layer 3b includes the first channel region 7a surrounded by the first gate insulating layer 4a and the channel region 7a surrounded by the second gate insulating layer 4b. Second passage area 7b. Thereby, the N ⁺ layer 3a, N ⁺ layer 3b, channel region 7, first gate insulating layer 4a, second gate insulating layer 4b, first gate conductor layer 5a and The dynamic flash memory unit 9 formed by the second gate conductor layer 5b. And, the N ⁺ layer 3a that becomes the source is connected to the source line SL, the N ⁺ layer 3b that becomes the drain is connected to the bit line BL, the first gate conductor layer 5a is connected to the plate line PL, and the second gate conductor layer 5a is connected to the plate line PL. The gate conductor layer 5b is connected to the word line WL. Preferably, the gate capacitance of the first gate conductor layer 5a connected to the plate line PL is larger than the gate capacitance of the second gate conductor layer 5b connected to the word line WL.

Here, in FIG. 1, the gate length of the first gate conductor layer 5a is greater than the gate length of the second gate conductor layer 5b, so that the first gate conductor layer 5a connected to the plate line PL is connected to the channel region 7 The capacitance between them is greater than the capacitance between the second gate conductor layer 5 b connected to the word line WL and the channel region 7 . However, in addition to this, the film thickness of each gate insulating layer may be changed so that the film thickness of the gate insulating film of the first gate insulating layer 4a is smaller than that of the gate insulating film of the second gate insulating layer 4b. thick, instead of making the gate length of the first gate conductor layer 5a larger than the gate length of the second gate conductor layer 5b. In addition, the dielectric constant of the material of each gate insulating layer can also be changed, so that the dielectric constant of the gate insulating film of the first gate insulating layer 4a is greater than that of the gate insulating film of the second gate insulating layer 4b. constant. Furthermore, the lengths of the gate conductor layers 5a, 5b, the film thicknesses of the gate insulating layers 4a, 4b, and the dielectric constants can be combined arbitrarily so that the gate of the first gate conductor layer 5a connected to the plate line PL The capacitance is greater than the gate capacitance of the second gate conductor layer 5b connected to the word line WL

Referring to FIG. 2, the erasing action mechanism will be described. The channel region 7 between the N ⁺ layer 3a and the N ⁺ layer 3b is electrically separated from the substrate to form a floating body. FIG. 2( a ) shows the state in which the hole groups 11 generated by impact dissociation in the previous cycle accumulate in the channel region 7 before the erasing operation. Furthermore, as shown in FIG. 2( b ), during the erasing operation, the voltage of the source line SL is set to the negative voltage _VERA . Here, V _ERA is -3V, for example. As a result, the PN junction between the source N ⁺ layer 3 a connected to the source line SL and the channel region 7 becomes forward biased regardless of the value of the initial potential of the channel region 7 . As a result, the hole group 11 accumulated in the channel region 7 generated by impact ionization in the previous cycle is attracted to the N ⁺ layer 3a of the source portion, and the potential V _FB of the channel region 7 becomes V _FB =V _ERA +Vb. Here, Vb is the built-in voltage of the PN junction, about 0.7V. Therefore, when V _ERA =-3V, the potential of the channel region 7 becomes -2.3V. This value is the potential state of the channel region 7 in the erased state. Therefore, if the potential of the channel region 7 of the floating body becomes a negative voltage, the threshold voltage of the N-channel MOS transistor of the dynamic flash memory cell will become higher due to the substrate bias effect. Thereby, as shown in FIG. 2( c ), the threshold voltage of the second gate conductor layer 5 b connected to the word line WL becomes higher. The erase state of the channel area 7 is logical memory data "0". Here, the above-mentioned voltage conditions applied to the bit line BL, the source line SL, the word line WL, and the plate line PL are an example for performing the erasing operation. If the erasing operation can be performed, other operations can also be used. condition.

FIG. 3 shows the writing operation of the dynamic flash memory unit of the first embodiment of the present invention. As shown in Figure 3(a), for example 0V is input to the N ⁺ layer 3a connected to the source line SL, for example 3V is input to the N ⁺ layer 3b connected to the bit line BL, and for the first layer connected to the plate line PL The gate conductor layer 5 a receives, for example, 2 V, and the second gate conductor layer 5 b connected to the word line WL receives, for example, 5 V. As a result, as shown in FIG. 3(a), an inversion layer 12a is formed on the inner periphery of the channel region 7 inside the first gate conductor layer 5a connected to the plate line PL, and the first gate conductor layer 5a having the first gate conductor layer 5a is formed. An N-channel MOS transistor region operates in the saturation region. As a result, pinch points 13 exist in the inversion layer 12a inside the first gate conductor layer 5a connected to the plate line PL. On the other hand, the second N-channel MOS transistor region having the second gate conductor layer 5b connected to the word line WL operates in the linear region. As a result, there is no pinch point inside the second gate conductor layer 5b connected to the word line WL, and the inversion layer 12b is formed on the entire surface. The inversion layer 12b formed on the entire inner surface of the second gate conductor layer 5b connected to the word line WL serves as the substantial drain of the first N-channel MOS transistor region having the first gate conductor layer 5a. to act. As a result, the electric field is in the channel region 7 between the first N-channel MOS transistor region having the first gate conductor layer 5a and the second N-channel MOS transistor region having the second gate conductor layer 5b connected in series. The first junction area becomes the largest, and the phenomenon of impact dissociation occurs in this area. Therefore, the region is the region on the source side when viewed from the second N-channel MOS transistor region having the second gate conductor layer 5b connected to the word line WL, so this phenomenon is called the source side impact free phenomenon . Due to this source-side impact ionization phenomenon, electrons flow from the N ⁺ layer 3 a connected to the source line SL toward the N ⁺ layer 3 b connected to the bit line. The accelerated electrons collide with the Si atoms of the crystal lattice to generate electron-hole pairs through their kinetic energy. Part of the generated electrons will flow to the first gate conductor layer 5 a and the second gate conductor layer 5 b, but most of them will flow to the N ⁺ layer 3 b connected to the bit line BL. In addition, when writing "1", the gate-induced drain leakage (GIDL: Gate Induced Drain Leakage) can be used to generate electron-hole pairs (refer to Non-Patent Document 11), and the generated hole groups can be used To be filled in the floating body FB.

And, as shown in FIG. 3( b ), the generated hole group 11 is the majority carrier of the channel region 7 , and charges the channel region 7 to a positive bias. Since the N ⁺ layer 3a connected to the source line SL is 0V, ^the channel region 7 is charged to the built-in voltage Vb (approximately 0.7V). When the channel region 7 is charged to be positively biased, the threshold voltages of the first N-channel MOS transistor region and the second N-channel MOS transistor region will become lower due to the substrate bias effect. Accordingly, as shown in FIG. 3( c ), the threshold voltage of the N-channel MOS transistor region of the second channel region 7 b connected to the word line WL becomes lower. Assign the write state of the channel area 7 to the logical memory data "1".

Here, during the writing operation, the above-mentioned first boundary region can also be replaced by the boundary region between the N ⁺ layer 3a and the channel region 7, or the boundary region between the N ⁺ layer 3b and the channel region 7, so as to impact Electron and hole pairs are generated by dissociation phenomenon or GIDL current, and the channel region 7 is charged by the generated hole group 11 . Here, the voltage conditions applied to the bit line BL, the source line SL, the word line WL, and the plate line PL are an example for performing the write operation, and other operations may be used if the write operation is possible. condition.

The reading operation of the dynamic flash memory unit and the related memory unit structure of the first embodiment of the present invention are described by using FIG. 4A. The readout operation of the dynamic flash memory unit is described with reference to FIG. 4A(a) to FIG. 4A(c). As shown in FIG. 4A(a), when the channel region 7 is charged to the built-in voltage Vb (about 0.7V), the threshold voltage of the N-channel MOS transistor will decrease due to the substrate bias effect. Assign this state to logical memory data "1". As shown in FIG. 4A(b), when the memory block selected before writing is in the erase state “0”, the floating body voltage V _FB in the channel region 7 becomes V _ERA +Vb. The write state "1" is randomly memorized by the write operation. As a result, logical memory data of logic "0" and "1" are created for the word line WL. As shown in FIG. 4A(c), by using the difference between the two threshold voltages of the word line WL, the sense amplifier can be used for reading.

4B(a) to 4B(d) are used to illustrate the readout operation of the dynamic flash memory cell of the first embodiment of the present invention, the first gate conductor layer 5a and the gate of the second gate conductor layer 5b The relationship between the size of the pole capacitance and the related actions. The gate capacitance of the second gate conductor layer 5b connected to the word line WL is preferably designed to be smaller than the gate capacitance of the first gate conductor layer 5a connected to the plate line PL. As shown in FIG. 4B(a), the length in the vertical direction of the first gate conductor layer 5a connected to the plate line PL is greater than the length in the vertical direction of the second gate conductor layer 5b connected to the word line WL, and The gate capacitance of the second gate conductor layer 5b connected to the word line WL is made smaller than the gate capacitance of the first gate conductor layer 5a connected to the plate line PL. FIG. 4B(b) shows an equivalent circuit of a cell of the dynamic flash memory of FIG. 4B(a). Moreover, FIG. 4B(c) shows the coupling capacitance relationship of the dynamic flash memory. Among them, C _WL is the capacitance of the second gate conductor layer 5b, C _PL is the capacitance of the first gate conductor layer 5a, and C _BL is the PN junction between the N ⁺ layer 3b that becomes the drain and the second channel region 7b. The capacitance of the surface, C _SL is the capacitance of the PN junction between the N ⁺ layer 3a of the source and the first channel region 7a. As shown in FIG. 4B(d), when the voltage of the word line WL oscillates, its operation becomes noise and affects the channel region 7 . The potential variation ΔV _FB of the channel region 7 at this time is ΔV _FB =C _WL /(C _PL +C _WL +C _BL +C _SL )×V _ReadWL . Here, V _ReadWL is the amplitude potential at the time of reading the word line WL. It can be seen from formula (1) that if the contribution of C _WL is reduced compared to the overall capacitance C _PL +C _WL +C _BL +C _SL of the channel region 7 , then ΔV _FB will become smaller. C _BL +C _SL is the junction capacitance of the PN junction. To increase this capacitance, for example, the diameter of the Si column 2 can be increased. However, this is not favorable for miniaturization of memory cells. In this regard, by making the length in the vertical direction of the first gate conductor layer 5a connected to the plate line PL larger than the length in the vertical direction of the second gate conductor layer 5b connected to the word line WL, ΔV _FB can be made Smaller without reducing the volume of the memory unit viewed from above. Here, the voltage conditions applied to the bit line BL, the source line SL, the word line WL, and the plate line PL are an example for performing the read operation. If the read operation is possible, other operations may also be used. condition.

5A to 5J are used to disclose the manufacturing method of the dynamic flash memory of this embodiment. In each figure, (a) shows a plan view, (b) shows a cross-sectional view along the XX' line in (a), and (c) shows a sectional view along the Y-Y' line in (a). Sectional view. In an actual dynamic flash memory, a plurality of memory cells are formed into a two-dimensional matrix.

As shown in FIG. 5A , on a substrate 10 (an example of a "substrate" in the scope of the patent application), an N ⁺ layer 11 (an example of the "first impurity region" in the scope of the patent application) is sequentially formed from the bottom. P layer 12 and N ⁺ layer 13 made of silicon. Then, the mask material layers 14a, 14b, 14c, and 14d that are circular in plan view are formed. Here, the substrate 10 may be formed of SOI (Silicon On Insulator, silicon-on-insulator), single or multiple layers of silicon, or other semiconductor materials. In addition, the substrate may be a well layer composed of a single layer or multiple layers of N layer or P layer.

Next, as shown in FIG. 5B, using the mask material layers 14a, 14b, 14c, and 14d as masks, the upper parts of the N ⁺ layer 13, the P layer 12, and the N ⁺ layer 11 are etched to form a layer on the N+ layer 11a. Si columns 12a, 12b, 12c, 12d (not shown) (an example of "first semiconductor column" in the scope of the patent application), and N+ layers 13a, 13b, 13c, 13d (not shown) (respectively patent application An example of the "second impurity region" in the range).

Next, as shown in FIG. 5C , a hafnium oxide (HfO ₂ ) layer 17 covering the entire gate insulating layer is formed by, for example, ALD (Atomic Layer Deposition; atomic layer deposition) method. In addition, a TiN layer (not shown) covering the entire gate conductor layer is formed, and is polished to the upper surface position and the upper surface of the mask material layers 14a to 14d by CMP (Chemical Mechanical Polishing) method. flush. Then, the TiN layer is etched by RIE (Reactive Ion Etching; Reactive Ion Etching) method until the upper surface position in the vertical direction becomes near the middle position of the Si pillars 12a-12d to form the TiN layer 18 ("first" in the scope of the patent application) An example of gate conductor layer). Here, the HfO ₂ layer 17 can also be formed by first oxidation at low temperature or by the double-layer structure of the SiO ₂ layer and the HfO ₂ film formed by the ALD method, and if it can function as a gate insulating layer , it can also be other insulating layers composed of a single layer or a plurality of layers. In addition, if it has the function of a gate conductor layer, the TiN layer 18 may also use other conductor layers composed of a single layer or a plurality of layers. In addition, the position of the upper surface of the TiN layer in the vertical direction is preferably etched higher than the middle position of the Si pillars 12 a to 12 d. Here, the TiN layer 18 outside the memory cell region is removed.

Next, as shown in FIG. 5D , on the TiN layer 18 , for example, a SiGe layer 23 (an example of the “first material layer” in the scope of the patent application) is formed by a selective epitaxial growth method. At this time, the SiGe layer 23 is formed only on the TiN layer 18, but not on the HfO ₂ layer 17 surrounding the exposed Si pillars 12a-12d.

Next, as shown in FIG. 5E, the SiGe layer 23 is oxidized to form a SiO ₂ layer 23a (an example of the "first oxide insulating layer" in the scope of the patent application).

Next, as shown in FIG. 5F, the HfO ₂ layer 17 above the SiO ₂ layer 23a is removed by etching to form an HfO ₂ layer 17a (an example of the "first gate insulating layer" in the scope of the patent application). Then, an HfO ₂ layer 17b (an example of the "second gate insulating layer" in the scope of the patent application) is formed on the whole. The whole body is coated with a TiN layer (not shown) by CVD (Chemical Vapor Deposition; chemical vapor deposition) method. Then, the TiN layer is etched by the RIE method until the upper surface becomes near the lower ends of the N ⁺ layers 13 a to 13 d. Then, a SiGe layer 25 is formed on the TiN layer 26 by a selective growth method.

Then, as shown in FIG. 5G, a SiN layer 27a is formed to surround and connect the side surfaces of the N ⁺ layers 13a, 13b and the mask material layers 14a, 14b. Similarly, SiN layer 27b is formed to surround and connect the side surfaces of N ⁺ layers 13c, 13d and mask material layers 14c, 14d. Then, the TiN layer 26 is etched using the SiN layer 27a27b as a mask to form TiN layers 26a and 26b (an example of the "second gate conductor layer" in the scope of the patent application). Here, the length L1 between the intersection of the outer peripheral line of the HfO _layer 17b surrounding the Si columns 12a, 12b and the XX' line is less than twice the width L2 of the SiN layer 27a, 27b on the YY' line, and Make the length L3 between the intersection of the outer peripheral line of the HfO ₂ layer 17b surrounding the Si columns 12a, 12c and the YY' line greater than twice the length of L2, whereby the SiN layer 27a can be formed between the Si columns 12a, 12b connected and separated between the Si columns 12a and 12c. Similarly, SiN layer 27b may be formed so as to connect between Si pillars 12c and 12d and separate between Si pillars 12a and 12c. Here, the HfO ₂ layer 17b can also be formed by first oxidation at low temperature or by the double-layer structure of the SiO ₂ layer and the HfO ₂ film formed by the ALD method, and if it can function as a gate insulating layer , it can also be other insulating layers composed of a single layer or a plurality of layers. In addition, if it has the function of a gate conductor layer, the TiN layer 18 may also use other conductor layers composed of a single layer or a plurality of layers.

Next, as shown in FIG. 5H, a SiO _layer 29 including holes 31aa, 31ab, 31ac, 31ba, 31bb, 31bc, 31ca, 31cb, and 31cc is formed between and around the side surfaces of the TiN layer 26a26b and the SiN layer 27a27b. In FIG. 5H, (d) is a cross-sectional view along line X1-X1' in (a) (the same is true in FIG. 5I). Here, the upper end positions of the holes 31aa, 31ab, 31ac, 31ba, 31bb, 31bc, 31ca, 31cb, and 31cc are formed lower than the upper end positions of the TiN layers 26a, 26b indicated by dotted lines in FIG. 5H(d).

Next, as shown in FIG. 5I, the mask material layers 14a to 14d are etched to form contact holes 30a, 30b, 30c, and 30d.

Next, as shown in FIG. 5J, a conductor layer (32a) connected to the bit line BL1 of the N ⁺ layers 13a, 13c via the contact holes 30a, 30c, and a conductor layer (32a) connected to the N ⁺ layer 13b via the contact holes 30b, 30d are formed. , Conductor layer (32b) of bit line BL2 of 13d. Then, between and on both sides of the conductor layer (32a) of the bit line BL1 and the conductor layer (32b) of the bit line BL2, a _SiO2 layer 33 including holes 34a, 34b, and 34c is formed. Thereby, a dynamic flash memory is formed on the substrate 10 . The TiN layers 26a, 26b are the conductor layers of the word lines WL1, WL2, the TiN layer 18 is the conductor layer of the plate line PL serving as the gate conductor layer, and the N ⁺ layer 11a is the source line serving as the source impurity layer Conductor layer of SL.

FIG. 5K is a schematic structural view showing the dynamic flash memory shown in FIG. 5J . The N ⁺ layer 11a of the conductor layer of the source line SL is formed by connecting the entire surface. The conductor layer of the plate line PL is also formed by connecting the whole. The gate conductor TiN layer 26a connected to the conductor layer of the word line WL1 is formed by connecting the adjacent Si pillars 12a and 12b along the X direction. Similarly, the gate conductor TiN layer 26b connected to the conductor layer of the word line WL2 is formed between the adjacent Si pillars 12c and 12d along the X direction. Also, the conductor layer of the bit line BL1 connected to the N ⁺ layers 13a and 13c and the conductor layer of the bit line BL2 connected to the N ⁺ layers 13b and 13d are formed along the Y direction perpendicular to the X direction.

Here, in FIGS. 5D and 5E , for example, a SiGe layer 23 is formed on the TiN layer 18 by a selective growth method, and then the SiGe layer 23 is oxidized to form a SiO ₂ layer 23 a. In contrast, if it is a material that can grow only on the TiN layer 18 without being formed on the _HfO2 layer surrounding the exposed Si pillars 12a-12d, and can then form an oxide layer by oxidation, the SiGe layer 23 may also be other material layers made of metal or semiconductor. In addition, if the SiGe layer 23 can be selectively formed on the TiN layer 18 as described above, the HfO ₂ layer 17 may be another material layer. If the material layer corresponding to the SiGe layer 23 can be selectively deposited thereon and function as a gate conductor layer, the TiN layer 18 can also be other conductor material layers. The same applies to the formation of the TiN layer 26, the SiGe layer 25, and the SiO ₂ layers 25a and 25b described with reference to FIGS. 5F and 5G.

In the above description, SiO ₂ layers 23a, 25a, 25b are formed by oxidizing the entire SiGe layers 23, 25, but only the surface layers may be oxidized to form SiO ₂ layers 23a, 25a, 25b. In addition, the SiGe layers 23 and 25 can also be replaced by other material layers that can be oxidized. In addition, the SiO ₂ layers 25 a and 25 b can also be formed by depositing an SiO ₂ layer on the whole by CVD, and then performing CMP polishing and recess RIE etching (recess RIE).

Here, in FIG. 1 , the length in the vertical direction of the first gate conductor layer 5 a connected to the plate line PL is greater than the length in the vertical direction of the second gate conductor layer 5 b connected to the word line WL so that C _PL >C _WL . However, the coupling ratio (C _WL /(C _PL +C _WL +C _BL +C _SL )) of the word line WL to the capacitive coupling of the channel region 7 is still reduced by only adding the plate line PL. As a result, the potential variation ΔV _FB of the channel region 7 of the floating body becomes smaller.

In addition, the voltage V _ErasePL of the plate line PL can be applied with a fixed voltage of, for example, 2V regardless of each operation mode. In addition, the voltage V _ErasePL of the plate line PL may be applied, for example, 0 V only during erasing. Also, if a voltage that satisfies the conditions for dynamic flash memory operation is available, a fixed voltage or a time-varying voltage may be applied to the voltage V _ErasePL of the plate line PL.

In addition, in FIG. 1, no matter the horizontal cross-sectional shape of the Si column 2 is circular, elliptical, or rectangular, the dynamic flash memory operation described in this embodiment can be performed. Moreover, circular, oval, and rectangular dynamic flash memory cells can also coexist on the same chip.

In addition, in FIG. 1, in the vertical direction, the channel region 7 surrounded by the insulating layer 6 is formed by connecting the potential distribution of the first channel region 7a and the second channel region 7b. Thereby, the first channel region 7a and the second channel region 7b of the channel region 7 are connected by the region surrounded by the insulating layer 6 in the vertical direction.

In addition, any one or all of the first gate conductor layer 5a, the second gate conductor layer 5b, and the third gate conductor layer 5c may be divided into two or more parts when viewed from above, as plate lines, The conductor electrodes of the word lines operate synchronously or asynchronously. Even so, dynamic flash memory operation can also be achieved.

In addition, in the vertical direction, one or both of the first gate conductor layer 5 a and the second gate conductor layer 5 b can be divided in the vertical direction and operate synchronously or asynchronously. Even so, dynamic flash memory operation can also be achieved. At this time, the insulating layer between the divided gate conductor layers can be formed by the method described in FIG. 5 .

This embodiment has the following characteristics.

(Feature 1)

When the dynamic flash memory cell performs writing and reading operations, the voltage of the word line WL will oscillate up and down. At this time, the plate line PL plays the role of reducing the capacitive coupling ratio between the word line WL and the channel region 7 . As a result, the influence on the voltage change of the channel region 7 when the voltage of the word line WL oscillates up and down can be significantly suppressed. Thereby, the threshold voltage difference of the SGT transistor of the word line WL displaying logic "0" and "1" can be increased. This leads to the enlargement of the action difference of the dynamic flash memory unit.

(Feature 2)

In FIGS. 5D and 5E, for example, a SiGe layer 23 is formed on the TiN layer 18 by a selective growth method, and then the SiGe layer 23 is oxidized to form a SiO ₂ layer 23a. This SiO ₂ layer 23a serves as an insulating layer for electrically separating the gate TiN layer 18 connected to the plate line PL from the gate TiN layers 26a, 26b connected to the word line WL. The known method is to first deposit a SiO ₂ layer by CVD, and then perform CMP grinding and RIE etching to form the SiO ₂ layer 23a. In this method, the SiO ₂ film is initially deposited on the whole by the CVD method. Then, the upper surface of the SiO ₂ film is polished by CMP until it is flush with the upper surface of the mask material layers 14 a - 14 d. Then, the TiN layer 18 is etched by the RIE method to leave a SiO ₂ film with a predetermined thickness. However, if this etching is performed excessively, the SiO ₂ film will be completely removed from the upper surface of the TiN layer 18, and an electrical short circuit will occur between the TiN layer 18 and the TiN layers 26a and 26b. Therefore, there is a requirement for high controllability and high uniformity across the wafer for RIE etching. On the other hand, the method of this embodiment is to grow the SiGe layer 23 uniformly on the TiN layer 18, and oxidize the SiGe layer 23 to form the _SiO2 layer 23a, so it is difficult to cause the excessive RIE method in the known method. Etching causes an undesirable situation of an electrical short between the TiN layer 18 and the TiN layers 26a, 26b.

(Feature 3)

5E oxidizes the entire SiGe layer 23 to form the SiO ₂ layer 23a, but even if the entire SiO ₂ layer 23a is not formed, the insulation between the TiN layer 18 and the TiN layers 26a and 26b can be achieved. Therefore, insulation of the TiN layer 18 and the TiN layers 26a, 26b can be easily achieved.

(Feature 4)

The oxidation rate of the SiGe layer 23 is faster than that of Si (see, for example, Non-Patent Document 12). Therefore, for example, in FIG. 5E , the entire SiGe layer 23 is not oxidized, but the SiGe layer 23 can be oxidized while forming a thin SiO ₂ layer on the side surfaces of the Si pillars 12 a to 12 d before forming the HfO ₂ layer 17 b in FIG. 5F . And the SiO ₂ layer 23a is formed. This facilitates the design of the formation process of the SiO ₂ layer 23a that insulates the TiN layer 18 from the TiN layers 26a, 26b.

(Feature 5)

As shown in FIG. 5F and FIG. 5G, the _SiO2 layer 25a formed by oxidizing the SiGe layer 25 selectively grown on the TiN layer 26 becomes an etching stopper layer for protecting the TiN layer 26 when forming the SiN layers 27a and 27b. In this way, the formation of the TiN layers 26a, 26b of the word line WL becomes easy, and since the N ⁺ layers 13a~13d and the conductor layer (32a) of the bit line BL1 and the conductor layer (32b) of the bit line BL2 are reduced ) connection resistance, so when the contact holes 30a~30d are expanded to surround the side surfaces of the N ⁺ layers 13a~13d, it will not only serve as an etching stopper when forming the contact holes 30a~30d, but also become a TiN Layers 26a, 26b are insulating layers electrically separated from the conductor layer (32a) of bit line BL1 and the conductor layer (32b) of bit line BL1BL2.

(Second Implementation Type)

The manufacturing method of the dynamic flash memory of the second embodiment is disclosed by using FIG. 6 . In Fig. 6, (a) is a plan view, (b) is a section view along the XX' line in (a), and (c) is a section view along the Y-Y' line in (a). Sectional view.

Perform the same steps as those shown in Figures 5A to 5E. Next, as shown in FIG. 6, the HfO ₂ layer 17 above the SiO ₂ layer 23a in the vertical direction is left, and then, in the same manner as in the step shown in FIG. 5G, SiN layers 27a, 27b, TiN layers 26a, 26b. Then, the steps shown in FIG. 5H to FIG. 5J are performed to form a dynamic flash memory on the substrate 10 .

This embodiment has the following features.

In this embodiment, the same HfO ₂ layer 17 is used to form the gate insulating layer surrounded by the TiN layers 26a and 26b and the lower gate insulating layer surrounded by the TiN layer 18 . Therefore, there is no need to separately form the HfO ₂ layer 17b as the gate insulating layer of the SGT connected to the word line WL and the lower HfO ₂ layer as the gate insulating layer of the SGT connected to the plate line PL as in the first embodiment. 17a. Thereby, the manufacturing steps can be simplified.

(Third implementation type)

The manufacturing method of the dynamic flash memory of the third embodiment is disclosed by using FIGS. 7A to 7C. In each figure, (a) shows a plan view, (b) shows a section view along the XX' line in (a), and (c) shows a section view along the Y-Y' line in (a). Sectional view.

Perform the same steps as those shown in Figures 5A to 5E. Then, as shown in FIG. 7A , the HfO ₂ layer 17 on the upper portion in the vertical direction of the SiO ₂ layer 23 a is etched to form the HfO ₂ layer 17 a.

Next, as shown in FIG. 7B , the exposed side surfaces of the Si pillars 12 a - 12 d are oxidized at low temperature to form SiO ₂ layers 40 a , 40 b , 40 c , and 40 d. Then, the steps shown in Fig. 5F are performed.

Next, as shown in FIG. 7C , form the TiN layer 26a surrounding the sides of the _SiO2 layers 40a, 40b and the mask material layers 14a and 14b and connect them, and form the _SiO2 layers 40c, 40d, mask material layers 14c, 14d The side and connected TiN layer 26b. Then, the steps of FIG. 5H to FIG. 5J are performed to form a dynamic flash memory on the substrate 10 .

This embodiment has the following features.

In this embodiment, SiO ₂ layers 40a-40d are formed as gate insulating layers connected to the word line WL. In contrast, the _HfO2 layer 17a of high dielectric constant material is used as the gate insulating layer connected to the plate line PL, whereby the gate capacitance of the SGT of the plate line can be easily made larger than that connected to the word line WL. SGT gate capacitance. Thereby, the dynamic flash memory operation can be performed more stably.

(Fourth Implementation Type)

The manufacturing method of the dynamic flash memory of the fourth embodiment is disclosed by using FIG. 8A and FIG. 8B. In each figure, (a) shows a plan view, (b) shows a section view along the XX' line in (a), and (c) shows a section view along the Y-Y' line in (a). Sectional view.

On the TiN layer 18, a SiGe layer 23 is formed as shown in FIG. 5D. Then, as shown in FIG. 8A , the HfO ₂ layer 17 above the SiGe layer 23 in the vertical direction is removed to form an HfO ₂ layer 17 a.

Next, as shown in FIG. 8B , the exposed side surfaces of Si pillars 12a-12d are oxidized to form thin _SiO2 layers 42a, 42b, 42c, 42d (an example of "second oxide insulating layer" in the scope of the patent application). Simultaneously, SiGe layer 23 is oxidized to form SiO ₂ layer 43 (an example of "first insulating layer" in the scope of the patent application). In this oxidation, when only the upper layer of the SiGe layer 23 is oxidized, the lower layer remains the SiGe layer 23c. Then, an HfO ₂ layer 44 is deposited on the whole. Afterwards, the steps of FIG. 5F to FIG. 5J are performed to form a dynamic flash memory on the substrate 10 . Wherein, the SiO ₂ layers 42 a - 42 d and the HfO ₂ layer 44 surrounding the Si pillars 12 a - 12 d are gate insulating layers.

This embodiment has the following features.

(Feature 1)

The third embodiment is to separately perform the formation of the SiO ₂ layer 23a and the formation of the SiO ₂ layers 40a-40d. In contrast, in this embodiment, the SiO ₂ layers 42 a to 42 d and the SiO ₂ layer 23 c are formed simultaneously. For example, when the SiO ₂ layers 42 a - 42 d are formed after the SiO ₂ layer 23 c is formed in the third embodiment, the cleaning step must be performed after the SiO ₂ layer 23 c is formed, and the SiO ₂ layer 23 c will be etched accordingly. At this time, there is a demand for uniform etching of the entire wafer. In contrast, this implementation type does not have such a problem.

(Feature 2)

In this embodiment, even if the SiGe layer 23c remains as shown in FIG. 8B, there will be no problem in the electrical insulation between the TiN layer 18 and the TiN layers 26a, 26b in this embodiment. Thereby, the present embodiment can easily realize the insulation of the TiN layer 18 and the TiN layers 26a, 26b.

(other implementation types)

Here, in the present invention, the Si columns 2, 12a to 12d are formed, but semiconductor columns made of other semiconductor materials may also be used. The same applies to other embodiments of the present invention.

In addition, the N ⁺ layers 3 a , 3 b , 11 , and 13 in the first embodiment can also be formed of Si or other semiconductor material layers containing donor impurities. In addition, the N ⁺ layers 3a, 3b, 11, 13 can also be formed of different semiconductor material layers. In addition, these formation methods can be used to form the N ⁺ layer by epitaxial growth method or other methods. The same applies to other embodiments of the present invention.

Furthermore, if the masking material layers 14a-14d shown in FIG. 5A are SiO ₂ layers, aluminum oxide (Al ₂ O ₃ , also called AlO) layers, SiO ₂ layers and other materials that meet the purpose of the present invention, then they are also Other material layers including organic materials or inorganic materials may be used in a single layer or a plurality of layers. The same applies to other embodiments of the present invention.

Furthermore, the thickness and shape of the mask material layers 14 a - 14 d shown in the first embodiment vary according to the subsequent polishing by CMP method, etching by RIE method, and cleaning. This change is not limited as long as it meets the purpose of the present invention. The same applies to other embodiments of the present invention.

Moreover, in FIG. 5G , the upper end positions of the mask material layers 27a, 27b are flush with the upper end positions of the mask material layers 14a-14d. In contrast, in the RIE step, if the condition of covering the side surfaces of the N ⁺ layers 13a-13d is satisfied, the upper ends of the mask material layers 27a, 27b in the vertical direction may also be located on the side surfaces of the mask material layers 14a-14d. The same applies to other embodiments of the present invention.

Furthermore, in the first embodiment, the TiN layer 18 is used as the plate line PL and the gate conductor layer 5 a connected to the plate line PL. In contrast, a single layer or a plurality of conductive material layers may be used in combination to replace the TiN layer 18 . Similarly, in the first embodiment, the TiN layers 26a, 26b are used as the word line WL and the gate conductor layer 5b connected to the word line WL. In contrast, a single layer or a plurality of conductor materials can also be used in combination. layer to replace the TiN layers 18, 26a, 26b. In addition, the gate TiN layer can also be connected to a wiring metal layer such as W (tungsten) on its outside. The same applies to other embodiments of the present invention.

Furthermore, the SiN layers 27a, 27b shown in FIG. 5G are used to form etching mask layers for the TiN layers 26a, 26b. As long as the function of the etching mask in this embodiment can be obtained, the SiN layer 27a, 27b can also adopt single layer or multiple layers of other material layers. The same applies to other embodiments of the present invention.

In the description of the first embodiment, it was stated that the oxidation rate of the SiGe layer 23 is higher than that of Si (see, for example, Non-Patent Document 12). Thereby, for example, instead of oxidizing the entire SiGe layer 23 in FIG. 5E , before forming the HfO ₂ layer 17 b in FIG. 5F , the oxidation of the SiGe layer 23 can be promoted while forming a thin SiO ₂ layer on the side surfaces of the Si pillars 12 a to 12 d. And the SiO ₂ layer 23a is formed. This facilitates the design of the formation process of the SiO ₂ layer 23a that insulates the TiN layer 18 from the TiN layers 26a, 26b. The same applies to other embodiments of the present invention.

In the description of FIG. 5J, the conductor layer 32a of the bit line BL1 and the conductor layer 32b of the bit line BL2 are formed in one step, but the first conductor layer may be formed in the contact holes 30a~30d first, and then formed with this conductor layer. The layers are connected to form the conductor layer of the bit line BL1 and the conductor layer of the bit line BL2.

Furthermore, in the first embodiment, the shape of the Si pillars 12 a - 12 d is circular in plan view. However, the shape of the Si pillars 12 a to 12 d in plan view may be circular, elliptical, elongated in one direction, or the like. In addition, even in the logic circuit region formed separately from the dynamic flash memory cell region, Si pillars having different shapes when viewed from the top can be mixedly formed in the logic circuit region according to the design of the logic circuit. The same applies to other embodiments of the present invention.

Furthermore, in the first and fifth embodiments, the source line SL is negatively biased during the erasing operation, and the hole group belonging to the channel region 7 of the floating body FB is drawn out, but it can also be The bit line BL is negatively biased instead of the source line SL, or both the source line SL and the bit line BL are negatively biased to perform the erase operation. Alternatively, other voltage conditions can be used to perform the erase operation. The same applies to other embodiments of the present invention.

Various embodiments and changes can be made to the present invention without departing from the broad spirit and scope of the present invention. The above-mentioned implementation forms are used to illustrate an embodiment of the present invention, and are not intended to limit the scope of the present invention. The above-mentioned embodiments and variations can be combined arbitrarily. In addition, even if a part of the constituent requirements of the above-described embodiment is removed as necessary, it is still included in the scope of the technical idea of the present invention.

[industrial availability]

According to the memory device using the columnar semiconductor element of the present invention, a high-density and high-performance dynamic flash memory can be obtained.

12a, 12b, 12c: Si column

11a, 13a, 13b, 13c: N ⁺ layers

10: Substrate

17a, 17b: HfO ₂ layers

18,26a: TiN layer

23a, 25a, 25b: SiO ₂ layers

27a, 27b: SiN layer

30a, 30b, 30c: contact holes

31aa, 31ab, 31ac, 31ba, 31bb, 31bc, 31ca, 31cb, 31cc: empty hole

Claims (12)

A manufacturing method of a memory device using a columnar semiconductor element. The memory device performs a data retention operation and a data erasing operation. The data retention operation is controlled and applied to the first gate conductor layer, the second gate conductor layer, and the second gate conductor layer. The voltage of the first impurity region and the second impurity region keeps the group of holes formed due to the impact ion phenomenon or the drain leakage current caused by the gate inside the first semiconductor column. The data erasing operation is controlled and applied to the aforementioned first semiconductor column The voltage of a gate conductor layer, the aforementioned second gate conductor layer, the aforementioned first impurity region, and the aforementioned second impurity region removes the aforementioned hole group from the inside of the aforementioned first semiconductor pillar, and the manufacturing method has: The step of forming the aforementioned first semiconductor column standing in the vertical direction on the substrate; the step of forming the first gate insulating layer surrounding the side surface of the aforementioned first semiconductor column; the step of forming the aforementioned first gate conductor layer, the aforementioned first The gate conductor layer surrounds the side of the aforementioned first gate insulating layer, and its upper surface is located below the top of the aforementioned first semiconductor column; the gate conductor layer is selectively formed on the aforementioned first gate conductor layer. Or the step of the first material layer composed of semiconductor; the step of forming the first oxide insulating layer by oxidizing the surface layer or the whole of the aforementioned first material layer; the aforementioned second insulating layer above the aforementioned first oxide insulating layer in the vertical direction A step of forming a second gate insulating layer on the side of a semiconductor pillar; a step of forming the aforementioned second gate conductor layer in a manner surrounding the side of the aforementioned second gate insulating layer; before forming the aforementioned first semiconductor pillar or forming the aforementioned After the first semiconductor pillar, a step of forming the aforementioned first impurity region connected to the bottom of the aforementioned first semiconductor pillar; and Before forming the first semiconductor pillar or after forming the first semiconductor pillar, a step of forming the second impurity region on the top of the first semiconductor pillar. The manufacturing method of a memory device using a columnar semiconductor element as described in Claim 1 comprises: forming the aforementioned first semiconductor column in a vertical direction in such a way that the side surface of the aforementioned first semiconductor column and the aforementioned first oxide insulating layer are connected. The step of the second gate insulating layer. The method of manufacturing a memory device using a columnar semiconductor element according to claim 1, comprising: after forming the first oxide insulating layer, exposing the side surface of the first semiconductor column above the first material layer and a step of forming the second gate insulating layer by oxidizing the exposed side surfaces of the first semiconductor pillars. The method of manufacturing a memory device using a columnar semiconductor element according to claim 1, comprising: after forming the first material layer, exposing the side surface of the first semiconductor column above the first material layer steps; and a step of oxidizing the first material layer to form the first insulating oxide layer, and oxidizing the exposed side surfaces of the first semiconductor pillars to form the second insulating oxide layer, and using the second insulating oxide layer As the aforementioned second gate insulating layer. The method for manufacturing a memory device using a columnar semiconductor element as described in Claim 4, comprising: After forming the aforementioned second oxide insulating layer, a step of forming a first insulating layer, the aforementioned first insulating layer surrounds the side surfaces of the aforementioned second oxide insulating layer and is connected to the aforementioned first oxide insulating layer, and, by means of the aforementioned The second insulating oxide layer and the first insulating layer form the second gate insulating layer. The method of manufacturing a memory device using a columnar semiconductor element according to claim 1, comprising: leaving the first gate insulating layer above the first oxide insulating layer in the vertical direction, and then forming the first gate insulating layer In the step of two gate conductor layers, the first gate insulating layer remaining above the first oxide insulating layer is used as the second gate insulating layer. The manufacturing method of a memory device using a columnar semiconductor element as described in Claim 1 includes: after forming the second gate insulating layer, a step of forming a first conductor layer, the step of the first conductor layer surrounding the aforementioned a second gate insulating layer, and its upper surface is positioned near the lower end of the aforementioned second impurity region; a step of selectively forming a second material layer made of a conductor or a semiconductor on the aforementioned first conductive layer; and making the aforementioned A step of forming a second oxidized insulating layer by oxidizing the surface layer or the whole of the second material layer. The method of manufacturing a memory device using a columnar semiconductor element as described in claim 1, wherein the first material layer is formed of silicon germanium (SiGe). The method of manufacturing a memory device using a columnar semiconductor element according to claim 1, wherein the wiring connected to the first impurity region is a source line, and the wiring connected to the second impurity region is a bit line, one of the wiring connected to the first gate conductor layer and the wiring connected to the second gate conductor layer is a word line, and the other is a first drive control line, and by applying to the aforementioned source The voltages of the pole line, the bit line, the first driving control line and the word line are used to perform the data erasing operation and the data holding operation. The method of manufacturing a memory device using a columnar semiconductor element according to Claim 1, wherein the first gate capacitance between the first gate conductor layer and the first semiconductor column is formed to be larger than the second gate The second gate capacitance between the pole conductor layer and the aforementioned first semiconductor pillar is large. The method for manufacturing a memory device using a columnar semiconductor element according to claim 1, wherein, when viewed from above, one or both of the first gate conductor layer and the second gate conductor layer are divided by Formed in two ways. The method for manufacturing a memory device using a columnar semiconductor element according to claim 1, wherein, in the vertical direction, one or both of the first gate conductor layer and the second gate conductor layer are divided into Formed in at least two ways.

Images