TWI809745B - Semiconductor device with integrated decoupling and alignment features - Google Patents

Abstract

The present application discloses a semiconductor device with integrated decoupling alignment features. The semiconductor device includes a first wafer comprising a first substrate having a dielectric stack, a decoupling feature positioned in the dielectric stack under one of the plurality of first alignment marks, a plurality of first alignment marks positioned on the first substrate and parallel to each other; and a second wafer positioned on the first wafer and comprising a plurality of second alignment marks positioned above the plurality of first alignment marks. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks in a top-view perspective. The plurality of first alignment marks and the plurality of second alignment marks comprise a fluorescence material. The decoupling feature has a bottle-shaped cross-sectional profile, and the decoupling feature comprises a porous low-k material.

Description

Semiconductor device with integrated decoupling and alignment features

This application claims priority to US Patent Application Nos. 17/556,149 and 17/555,712 (ie, the priority date is "December 20, 2021"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device. More particularly, it relates to a semiconductor device having integrated decoupling feature alignment features.

Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually reduced to meet the increasing demand for computing power. However, during the process of shrinking dimensions, different problems are added, and such problems continue to increase in number and complexity. Therefore, challenges remain in achieving improved quality, yield, performance and reliability, and reduced complexity.

The above "prior art" description only provides background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" is It should not be part of this case.

An embodiment of the present disclosure provides a semiconductor device, including a first wafer, including a first substrate; and a plurality of first alignment marks, disposed on the substrate and parallel to each other; and a second wafer, disposed It is on the first wafer and includes a plurality of second alignment marks arranged on the plurality of first alignment marks. In a top view, the plurality of second alignment marks is disposed parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks. The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material. The plurality of first alignment marks and the plurality of second alignment marks are configured together to form a first group of alignment marks.

Another embodiment of the present disclosure provides a semiconductor device including a substrate; a dielectric stack disposed on the substrate; two conductive features disposed in the dielectric stack; a decoupling feature disposed on the dielectric stack In, between the two second conductive features, and including a bottle-shaped profile; and an alignment mark, disposed on the decoupling feature. The alignment mark includes a fluorescent material.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a first substrate; forming a plurality of first alignment marks on the first substrate parallel to each other, wherein the first substrate and the plurality of The first alignment marks are configured together according to the first wafer; a second wafer is provided, and the second wafer includes a plurality of second alignment marks parallel to each other; and the second wafer is bonded to the first wafer. on the wafer. In a top view, the plurality of second alignment marks is disposed parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks. The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material.

Still another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming a first dielectric layer on the substrate; forming a second dielectric layer on the first dielectric layer; forming Two second conductive features are on the second dielectric layer; forming an intermediate dielectric layer on the second dielectric layer and surrounding the two second conductive features; performing an extended etching process to form an extended opening in the intermediate dielectric layer forming an electrical layer; forming a decoupling feature in the extended opening; and forming an alignment mark on the decoupling feature. The alignment mark includes a fluorescent material.

Due to the design of the semiconductor device of the present disclosure, the plurality of alignment marks including fluorescent material can improve optical recognition during the wafer bonding process. Furthermore, the complementary design enables the first alignment marks and the second alignment marks to become mutually referenced during bonding. Therefore, the yield and reliability of the semiconductor device can be improved.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Certainly, these embodiments are only for illustration, and are not intended to limit the scope of the present disclosure. For example, where a first component is formed on a second component, it may include embodiments where the first and second components are in direct contact, or may include an additional component formed between the first and second components, An embodiment such that the first and second parts do not come into direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in many instances. These repetitions are for the purpose of simplicity and clarity and, unless otherwise indicated in the context, do not in themselves imply a specific relationship between the various embodiments and/or configurations discussed.

Additionally, for ease of description, spaces such as "beneath", "below", "lower", "above", "upper" may be used herein Relative relationship terms are used to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of elements in use or operation in addition to the orientation depicted in the figures. The device may be at other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be understood that when forming a component on, connected to, and/or coupled to another component, it may include implementations where these components are formed in direct contact. Examples, and may also include embodiments in which additional components are formed between these components such that the components do not come into direct contact.

It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not constrained by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the presently advanced concepts.

Unless the context indicates otherwise, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, Then terms such as "same", "equal", "planar", or "coplanar" as used herein are not necessarily Means an exact identical orientation, arrangement, position, shape, size, quantity, or other measurement, but it is meant to include, within acceptable variance, nearly identical orientation, arrangement, position, shape, size , quantity, or other measure, and for example, the acceptable variance may occur due to manufacturing processes (manufacturing processes). The term "substantially" may be used herein to express this meaning. For example, as substantially the same, substantially equal, or substantially planar, as being exactly the same, equal, or planar, or Yes, they may be the same, equal, or flat within acceptable variances that may occur, for example, due to manufacturing processes.

In this disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a Both a semiconductor circuit and an electronic device are included in the category of semiconductor devices.

It should be understood that in the description of the present disclosure, above (or above (up)) corresponds to the direction of the Z-direction arrow, and below (or below (down)) corresponds to the relative direction of the Z-direction arrow .

It should be understood that the terms "forming", "formed" and "form" may denote and include any creating, building, patterning, planting A method of implanting or depositing an element, a dopant, or a material. Examples of formation methods may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion (diffusing), deposition (depositing), growth (growing), implantation (implantation), photolithography (photolithography), dry etching and wet etching, but not limited thereto.

It should be understood that, in the description of the present disclosure, functions or steps mentioned herein may occur out of the order shown in the accompanying drawings. For example, two figures shown in succession may, in fact, be executed substantially concurrently, or may sometimes be executed in the reverse order, depending upon the functions or steps involved.

FIG. 1 is a schematic flowchart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. 2 to 5 are schematic cross-sectional views illustrating part of a process for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. FIG. 6 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 7 and 8 are schematic cross-sectional views, illustrating a part of a process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure along the section line A-A' in FIG. 6 . It should be understood that some elements of the semiconductor element 1A are omitted in the top view for clarity.

Referring to FIG. 1 to FIG. 3 , in step S11 , a first substrate 101 may be provided, and a plurality of first conductive features 103 may be formed on the first substrate 101 .

Please refer to FIG. 2, the first substrate 101 may include a monolithic semiconductor substrate, which is completely composed of at least one semiconductor material, a plurality of device elements (not shown for clarity), a plurality of dielectric layers (for clarity) See, not shown) and a plurality of conductive features (not shown for clarity). For example, a bulk semiconductor substrate may comprise an elemental semiconductor, a compound semiconductor, or a combination thereof; an elemental semiconductor such as silicon or germanium; a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, InAs, InSb or other III-V compound semiconductors or II-VI compound semiconductors.

In some embodiments, the first substrate 101 may include a semiconductor-on-insulator structure, which is composed of a handle substrate, an isolation layer, and an uppermost semiconductor material layer from bottom to top. The handle substrate and the uppermost layer of semiconductor material may comprise the same materials as previously described for the bulk semiconductor substrate. The isolation layer can be a crystalline or amorphous dielectric material, such as an oxide and/or nitride. For example, the isolation layer can be a dielectric oxide such as silicon oxide. As another example, the isolation layer can be a dielectric nitride such as silicon nitride or boron nitride. As another example, the isolation layer may include a stack of a dielectric oxide and a dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The isolation layer may have a thickness between about 10 nm and about 200 nm.

It should be understood that the term "about" modifies a quantity of an ingredient, a component, or a reactant of the present disclosure, and represents a numerical variation that may occur, for example In general, it goes through typical measurements and liquid handling procedures used to make concentrates or solutions. Furthermore, variations may arise from inadvertent errors in measurement procedures applied to the manufacture of compositions or in the implementation of the methods or the like, differences in manufacture, source (source), or the purity of ingredients (purity). In one aspect, the term "about" means within 10% of the reported value. On the other hand, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

Referring to FIG. 2, a plurality of device elements may be formed on a bulk semiconductor substrate or on the uppermost semiconductor material layer. Portions of the plurality of device elements may be formed in the bulk semiconductor substrate or in the uppermost layer of semiconductor material. The plurality of device elements may be transistors, such as CMOS transistors, MOSFETs, FinFETs, the like, or combinations thereof.

Referring to FIG. 2, a plurality of dielectric layers may be formed on a bulk semiconductor substrate or on the uppermost semiconductor material layer, and cover a plurality of device elements. In some embodiments, the plurality of dielectric layers may include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, analogues or combinations thereof. A low dielectric constant material may have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low dielectric constant material may have a dielectric constant less than 2.0. The fabrication techniques for the plurality of dielectric layers may include multiple deposition processes, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, or the like. Multiple planarization processes may be performed after the deposition processes to remove excess material and provide a substantially planar surface for subsequent processing steps.

Referring to FIG. 2 , the plurality of conductive features may include a plurality of interconnection layers and a plurality of conductive vias. The interconnection layers can be separated from each other and can be horizontally disposed in the plurality of dielectric layers along the direction Z. The conductive vias can connect adjacent interconnection layers along the direction Z, and connect adjacent device elements and interconnection layers. In some embodiments, the conductive vias improve heat dissipation and provide structural support. In some embodiments, for example, the plurality of conductive features may comprise tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal Nitrides (such as titanium nitride), transition metal aluminides, or combinations thereof. During formation of the plurality of dielectric layers, the plurality of conductive features may be formed.

In some embodiments, the plurality of device elements and the plurality of conductive features can be configured together as a plurality of functional units in the first substrate 101 . In the description of the present disclosure, a functional unit generally refers to functionally related circuits, which have been separated into a single unit according to the functional purpose. In some embodiments, these functional units are usually highly complex circuits, such as processor cores, memory controllers or accelerator units. In some embodiments, the complexity and functionality of a functional circuit can be more or less complex.

Referring to FIG. 2 , a layer of first material 501 may be formed on the first substrate 101 . In some embodiments, for example, the first material 501 can be tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (such as tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrogen compounds (such as titanium nitride), transition metal aluminides, or combinations thereof. For example, the fabrication technique of the layer of first material 501 may include physical vapor deposition, sputtering, chemical vapor deposition or other applicable deposition processes.

Please refer to FIG. 2 , a first mask layer 601 can be formed on the layer of first material 501 . The first mask layer 601 can be a photoresist layer and can include a plurality of patterns of the first conductive features 103 .

Referring to FIG. 3 , an etching process such as an anisotropic dry etching process may be performed to remove some portions of the first material 501 and simultaneously form a plurality of first conductive features 103 on the first substrate 101 . During the etching process, the etch rate ratio of the first material 501 to the first substrate 101 may be between about 100:1 to about 1.05:1, between about 15:1 to about 2:1, or between about 10:1. 1 to about 2:1. After the etching process, the first mask layer 601 can be removed. In some embodiments, the plurality of first conductive features 103 can be electrically coupled to the plurality of device elements, but not limited thereto. In some embodiments, the plurality of first conductive features 103 can be configured as a test circuit.

Referring to FIG. 1 and FIG. 4 , in step S13 , a first lower liner 107 may be formed to cover the first substrate 101 and the plurality of first conductive features 103 .

Referring to FIG. 4 , the first lower pad 107 may be conformally formed to cover the first substrate 101 and the plurality of first conductive features 103 . In some embodiments, for example, the fabrication technique of the first lower liner 107 may include atomic layer deposition. Usually, an atomic layer deposition supplies two (or more) different source gases alternately one by one to a processing object (for example, the first substrate 101 and a plurality of first conductive electrodes) under a plurality of predetermined manufacturing conditions. feature 103), so that a plurality of chemical substances are adsorbed on the processing object at a single atomic level and deposited on the processing object through multiple surface reactions. For example, first and second source gases are alternately supplied to a processing object to flow along its surface, whereby molecules contained in the first source gas are adsorbed to the surface, and molecules contained in the second source gas are The contained molecules react with the adsorbed molecules from the first source gas to form a thin film with a thickness on the order of a single molecule. The above process steps are repeated to form a high-quality film on the processed object.

In some embodiments, for example, the first lower liner 107 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, the like, or combinations thereof. It should be understood that in the description of the present disclosure, silicon oxynitride refers to a substance including silicon, nitrogen and oxygen, and a proportion of oxygen is greater than a proportion of nitrogen. Silicon oxynitride refers to a substance that includes silicon, oxygen and nitrogen, and a proportion of nitrogen is greater than a proportion of oxygen.

It should be understood that the first lower pad 107 completely covers the plurality of first conductive features 103, and the first substrate 101 in FIG. element.

Referring to FIG. 1 and FIGS. 5 to 7 , in step S15 , a plurality of first alignment marks 105 may be formed between the first lower pad 107 and the plurality of first conductive features 103 .

Referring to FIG. 5 , an isolation layer 511 may be formed on the first lower liner 107 and completely fill up the space between the phosphorous first conductive features 103 . The isolation layer 511 may include a fluorescent material. In some embodiments, the fluorescent material may be azobenzene. In some embodiments, for example, the fabrication technique of the isolation layer 511 may include chemical vapor deposition.

6 and 7, a planarization process such as chemical mechanical polishing can be performed until the first lower liner 107 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps, and at the same time The isolation layer 511 is converted into a plurality of first alignment marks 105 . In a cross-sectional view, the plurality of first conductive features 103 can horizontally surround the plurality of first alignment marks 105 , and the plurality of first alignment marks 105 can be parallel to each other. In a top view, the plurality of first alignment marks 105 located at the upper left area may extend along the direction Y and be parallel to each other. The plurality of first alignment marks 105 located in the upper right area may extend along the direction X and be parallel to each other. The plurality of first alignment marks 105 located in the lower right area may extend along the direction Y and be parallel to each other.

During the subsequent wafer bonding process, the plurality of first alignment marks 105 including fluorescent material can improve optical identification.

Referring to FIG. 1 and FIG. 8 , in step S17 , a first upper pad 109 may be formed on the first lower pad 107 and the plurality of first alignment marks 105 .

Referring to FIG. 8 , the first upper liner 109 may be conformally formed on the first lower liner 107 and the plurality of first alignment marks 105 . In some embodiments, for example, the first upper pad 109 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, the like, or a combination thereof. In some embodiments, for example, the fabrication technique of the first upper pad 109 may include atomic layer deposition. The first upper liner 109 can be used as a protective layer to prevent the fluorescent material in the plurality of first alignment marks 105 from being damaged in subsequent semiconductor manufacturing processes. In addition, the first upper liner 109 can be used as a barrier layer to prevent the fluorescent material in the plurality of first alignment marks 105 from diffusing out to contaminate adjacent devices.

The first substrate 101 , the plurality of first conductive features 103 , the plurality of first alignment marks 105 , the first lower pad 107 and the first upper pad 109 are configured together to form a first wafer 100 . The first wafer 100 can be configured as a logic chip or a memory chip.

FIG. 9 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. FIG. 10 is a schematic cross-sectional view illustrating a part of a process for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure along the section line A-A' in FIG. 9 . FIG. 11 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. FIG. 12 is a schematic cross-sectional view illustrating a part of a process for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure along the section line A-A' in FIG. 11 .

Referring to FIG. 1 and FIGS. 9 to 12 , in step S19 , a second wafer 200 may be provided, and the second wafer 200 may be bonded to the first upper pad 109 to form the semiconductor device 1A.

9 and 10, the second wafer 200 may include a second substrate 201, a plurality of second conductive features 203, a plurality of second alignment marks 205, a second lower pad 207 and a second upper Liner 209 . The second substrate 201, the plurality of second conductive features 203, the plurality of second alignment marks 205, the second lower pad 207, and the second upper pad 209 may respectively include corresponding structures similar to those described in FIGS. The procedures of the first substrate 101 , the plurality of first conductive features 103 , the plurality of first alignment marks 105 , the first lower pad 107 and the first upper pad 109 will not be described here again.

In some embodiments, the plurality of second alignment marks 205 may include a fluorescent material. For example, the fluorescent material can be azobenzene. During the subsequent wafer bonding process, the plurality of second alignment marks 205 including fluorescent material can improve optical identification.

In some embodiments, in a cross-sectional view, the plurality of second conductive features 203 can horizontally surround the plurality of second alignment marks 205 , and the plurality of second alignment marks 205 can be parallel to each other. In the top view, the plurality of second alignment marks 205 located in the upper left area may extend along the direction Y and be parallel to each other. The plurality of second alignment marks 205 located in the upper right area may extend along the direction X and be parallel to each other. The plurality of second alignment marks 205 located in the lower left area can extend along the direction X and be parallel to each other. The plurality of second alignment marks 205 located in the lower right area may extend along the direction Y and be parallel to each other.

In some embodiments, the second wafer 200 may be configured as a memory chip.

Referring to FIG. 11 and FIG. 12 , the second wafer 200 can be turned over and bonded to the first wafer 100 . In some embodiments, for example, the bonding of the second wafer 200 to the first wafer 100 may be via an oxide-containing first upper pad 109 including an oxide and a second upper pad 209 including an oxide. join.

In a top view, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 may be complementary to each other. That is, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 do not overlap with each other. The complementary design makes the plurality of first alignment marks 105 and the plurality of second alignment marks 205 become mutual references during the bonding process. Therefore, the yield and reliability of the semiconductor device 1A can be improved.

In some embodiments, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 located in the upper left area may be represented as a first group of alignment marks 1S. The alignment marks of the first set of alignment marks 1S (eg, the first alignment marks 105 and the second alignment marks 205 ) may extend along the direction X and be parallel to each other.

In some embodiments, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 located in the upper right area can be represented as a second set of alignment marks 2S. The second set of alignment marks 2S may move away from the first set of alignment marks 1S along the direction X. The alignment marks of the second set of alignment marks 2S may extend along the direction X and be parallel to each other.

In some embodiments, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 located in the lower left area can be represented as a third group of alignment marks 3S. The alignment marks 3S of the third group may be away from the alignment marks 1S of the first group in the direction Y. The alignment marks of the third set of alignment marks 3S may extend along the direction X and be parallel to each other.

In some embodiments, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 located in the lower right area can be represented as a fourth group of alignment marks 4S. The fourth set of alignment marks 4S can move away from the first set of alignment marks 1S along a direction S. The direction S can be inclined relative to the direction X and the direction Y. The alignment marks of the fourth set of alignment marks 4S may extend along the direction Y and be parallel to each other.

FIG. 13 is a schematic top view illustrating a semiconductor device 1B according to another embodiment of the present disclosure.

Please refer to FIG. 13 , the semiconductor device 1B may have a structure similar to that described in FIG. 11 . In FIG. 13 , elements that are the same as or similar to those in FIG. 11 have been marked with similar element numbers, and repeated descriptions thereof have been omitted. The semiconductor device 1B may include a fifth set of alignment marks 5S. The fifth set of alignment marks 5S may move away from the first set of alignment marks 1S in a direction S. As shown in FIG. The alignment marks of the fifth set of alignment marks 5S (such as the first alignment marks 105 and the second alignment marks 205 ) may extend along the direction X and be parallel to each other.

FIG. 14 is a schematic flowchart illustrating a method 20 for manufacturing a semiconductor device 1C according to another embodiment of the present disclosure. 15 to 25 are schematic cross-sectional views illustrating part of a process for manufacturing a semiconductor device 1C according to another embodiment of the present disclosure.

Please refer to FIG. 14 to FIG. 18, in step S21, a third substrate 301 can be provided, a first dielectric layer 303 can be formed on the third substrate 301, and a second dielectric layer 305 can be formed on the first dielectric layer. On layer 303 , a plurality of second conductive features 313 may be formed on second dielectric layer 305 .

Referring to FIG. 15 , the third substrate 301 may include a process similar to that of the first substrate 101 described in FIG. 2 , and its description will not be repeated herein.

Please refer to FIG. 15. In some embodiments, for example, the first dielectric layer 303 may include fluorosilicate glass, borophosphosilicate glass, a spin-coated low-k dielectric layer, a chemical Vapor-deposited low-k dielectric layers or combinations thereof. In some embodiments, the first dielectric layer 303 may include a self-planarizing material or a spin-on-k dielectric material, and a self-planarizing material such as a spin-on-glass, and a spin-on low-k dielectric Electrical materials such as SiLK™. The use of a self-planarizing dielectric material avoids the need to perform a subsequent planarization step. In some embodiments, the fabrication technique of the first dielectric layer 303 may include a deposition process, for example, the deposition process includes chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation or spin coating.

Referring to FIG. 15 , in some embodiments, for example, the second dielectric layer 305 may include silicon nitride, silicon nitride oxide, silicon oxynitride, the like, or a combination thereof. For example, the fabrication technique of the second dielectric layer 305 may include chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes. In some embodiments, the second dielectric layer 305 can be used as a barrier layer to prevent moisture from entering the underlying layers (eg, the first dielectric layer 303 and the third substrate 301 ). In some embodiments, the thickness T1 of the first dielectric layer 303 is greater than the thickness T2 of the second dielectric layer 305 .

Referring to FIG. 15 , a layer of second material 503 may be formed on the second dielectric layer 305 . For example, the second material 503 can be titanium, titanium nitride, tantalum, tantalum nitride or the like. For example, the manufacturing technique of the layer of second material 503 may include chemical vapor deposition, physical vapor deposition, sputtering or similar processes. A layer of third material 505 may be formed on the layer of second material 503 . For example, the third material 505 can be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel or the like. For example, the manufacturing technique of the layer of third material 503 may include physical vapor deposition, sputtering or similar processes. A layer of fourth material 507 may be formed on the layer of third material 505 . In some embodiments, the fourth material 507 and the second material 503 may include the same material. In some embodiments, for example, the fourth material 507 can be titanium, titanium nitride, tantalum, tantalum tantalum, or the like. For example, the fabrication technique of the layer of fourth material 507 may include chemical vapor deposition, physical vapor deposition, sputtering or similar processes.

Referring to FIG. 15 , a second mask layer 603 can be formed on the layer of fourth material 507 . The second mask layer 603 can be a photoresist layer and can include a plurality of patterns of the second conductive features 313 .

Referring to FIG. 16 , an etching process such as an anisotropic dry etching process may be performed to remove some portions of the second material 503 , the third material 503 and the fourth material 507 . After the etching process, the remaining second material 503 can be represented as a plurality of lower barrier layers 315, the remaining third material 505 can be represented as a plurality of intermediate conductive layers 317, and the remaining fourth material 507 can be represented as a plurality of upper barrier layers 319 . In some embodiments, the etch process may be a multi-step etch process and may be anisotropic.

For brevity, clarity and ease of description, only one lower barrier layer 315 , one middle conductive layer 317 and one upper barrier layer 319 are described. In some embodiments, the thickness T3 of the lower barrier layer 315 and the thickness T4 of the upper barrier layer 319 may be about the same. In some embodiments, the thickness T3 of the lower barrier layer 315 may be greater than the thickness T4 of the upper barrier layer 319 . In some embodiments, the thickness T5 of the middle conductive layer 317 may be greater than the thickness T3 of the lower barrier layer 315 or the thickness T4 of the upper barrier layer 319 .

Referring to FIG. 17 , a layer of fifth material 509 may be conformally formed on the intermediate semiconductor device as described in FIG. 16 . For example, the fifth material 509 can be titanium, titanium nitride, tantalum, tantalum nitride or the like. For example, the fabrication technique of the layer of fourth material 507 may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering or similar processes. In some embodiments, the fifth material 509 and the upper barrier layer 319 may include the same material.

Referring to FIG. 18 , a process such as an anisotropic dry etching process may be performed to remove some portions of the fifth material 509 . After the etching process, the remaining fifth material 509 can be represented as a plurality of interstitial barrier layers 321 . A plurality of spacer barrier layers 321 can be formed to cover each sidewall 319SW of the upper barrier layer 319 , each sidewall 317SW of the middle conductive layer 317 and each sidewall 315SW of the lower barrier layer 315 .

The plurality of interstitial barrier layers 321 , the plurality of upper barrier layers 319 , the plurality of middle conductive layers 317 and the plurality of lower barrier layers 315 are configured together to form a plurality of second conductive features 313 .

Please refer to FIG. 14 and FIG. 19 to FIG. 22, in step S23, an intermediate dielectric layer 307 can be formed on the second dielectric layer 305 and surround the plurality of second conductive features 313, and the plurality of decoupling features 323 can be formed on in the middle dielectric layer 307 .

Referring to FIG. 19 , an intermediate dielectric layer 307 may be formed on the second dielectric layer 305 and cover the plurality of second conductive features 313 . A planarization process such as chemical mechanical polishing may be performed until the upper surfaces of the plurality of second conductive features 313 are exposed to remove excess material and provide a substantially planar surface for subsequent processing steps. In some embodiments, the intermediate dielectric layer 307 may include a material having a different etch rate than the second dielectric layer 305 . In some embodiments, for example, the interlayer dielectric layer 307 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, fluorosilicate glass, borophosphosilicate glass or combinations thereof. In some embodiments, for example, the fabrication technique of the interlayer dielectric layer 307 may include chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes.

It should be understood that, in the description of the present disclosure, a surface of an element (or feature) located at the highest vertical plane along the direction Z is referred to as an upper surface of the element (or feature). A surface of an element (or feature) located at the lowest vertical plane along the direction Z is called the lower surface of the element (or feature).

Referring to FIG. 19 , a third mask layer 605 may be formed on the intermediate dielectric layer 307 . In some embodiments, the third mask layer 605 may be a photoresist layer and may include a plurality of patterns of decoupling features 323 .

Referring to FIG. 20 , an anisotropic etching process may be performed to remove some portions of the intermediate dielectric layer 307 and simultaneously form a plurality of openings 307O. In some embodiments, the anisotropic etching process may be an anisotropic dry etching process. In some embodiments, the etch ratio of the interlayer dielectric layer 307 to the second dielectric layer 305 may be between about 100:1 and about 1.05:1, between about 15:1 during the anisotropic etch. to about 2:1, or between about 10:1 to about 2:1.

Referring to FIG. 21 , an extended etching process may be performed to expand the plurality of openings 307O into a plurality of extended openings 307E. In some embodiments, the extended etch process may be an isotropic etch process. In some embodiments, the extended etch process may be a wet etch process. In some embodiments, the etch ratio of the interlayer dielectric layer 307 to the second dielectric layer 305 may be between about 100:1 to about 1.05:1, between about 15:1 to about 1.05:1 between the extended etch processes. Between about 2:1, or between about 10:1 and about 2:1. In some embodiments, each sidewall of the plurality of expansion openings 307E may be curved.

Please refer to FIG. 22, the third mask layer 605 can be removed, an isolation material can be deposited to completely fill the plurality of extended openings 307E, and then a planarization process such as chemical mechanical polishing can be performed until the plurality of second conductive The top surfaces of features 313 are exposed to remove excess material, provide a generally flat surface for subsequent processing steps, and simultaneously form a plurality of decoupling features 323 . In some embodiments, plurality of decoupling features 323 may have a bottle-shaped cross-sectional profile.

In some embodiments, for example, the isolation material can be a porous low-k material.

In some embodiments, the isolation layer can be an energy-removable material. The energy-removable material may include a material such as a thermally decomposable material, a photodecomposable material, an electron beam decomposable material, or a combination thereof. For example, an energy-removable material can include a base material and a decomposable porous material that is sacrificially removed when exposed to an energy source. The base material may include a methylsilsesquioxane-based material. The decomposable porous material may include a porous organic compound that provides porosity to the base material of the energy-removable material. After the planarization process, an energy process is performed by providing an energy source. Energy treatments may include heat, light, or combinations thereof. When heat is used as an energy source, a temperature for energy processing may be between about 800°C and about 900°C. When light is used as an energy source, an ultraviolet light can be provided. The energy treatment can remove the decomposable porous material from the energy-removable material to create a plurality of empty spaces (pores), while the base material remains in place. The empty spaces (holes) can reduce the dielectric constant of the plurality of decoupling features 323 .

Referring to FIG. 22 , a plurality of decoupling features 323 may be respectively and correspondingly formed between adjacent pairs of second conductive features 313 . In some embodiments, a plurality of decoupling features 323 having a low dielectric constant may perform the decoupling feature function. In some embodiments, the plurality of decoupling features 323 can reduce the parasitic capacitance of the plurality of second conductive features 313 .

14 and 23 to 25, in step S25, a third dielectric layer 309 can be formed on the intermediate dielectric layer 307, a fourth dielectric layer 311 can be formed on the third dielectric layer 309, A plurality of third alignment marks 325 may be formed on a plurality of decoupling features 232 .

Please refer to FIG. 23. In some embodiments, for example, the third dielectric layer 309 may include fluorosilicate glass, borophosphosilicate glass, a spin-on low-k dielectric layer, a chemical gas Phase deposition of low-k dielectric layers or combinations thereof. In some embodiments, the third dielectric layer 309 may include a self-planarizing material or a spin-on-k dielectric material, and a self-planarizing material such as a spin-on-glass, and a spin-on low-k dielectric Electrical materials such as SiLK™. The use of a self-planarizing dielectric material avoids the need to perform a subsequent planarization step. In some embodiments, for example, the fabrication technique of the third dielectric layer 309 may include a deposition process, for example, the deposition process includes chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation or spin coating. In some embodiments, the third dielectric layer 309 and the first dielectric layer 303 may include the same material.

Referring to FIG. 23 , in some embodiments, for example, the fourth dielectric layer 311 may include silicon nitride, silicon nitride oxide, silicon oxynitride, the like, or a combination thereof. For example, the fabrication technique of the fourth dielectric layer 311 may include chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes. In some embodiments, the fourth dielectric layer 311 can be used as a barrier layer to prevent moisture from entering the underlying layers (eg, the third dielectric layer 309 and the intermediate dielectric layer 307 ). In some embodiments, the thickness T6 of the third dielectric layer 309 is greater than the thickness T7 of the fourth dielectric layer 311 .

Referring to FIG. 23 , the first dielectric layer 303 , the second dielectric layer 305 , the intermediate dielectric layer 307 , the third dielectric layer 309 and the fourth dielectric layer 311 can be configured together into a dielectric stack DS.

Referring to FIG. 23 , a fourth mask layer 607 may be formed on the dielectric stack DS. The fourth mask layer 607 can be a photoresist layer and can include a plurality of patterns of the third alignment marks 325 .

Referring to FIG. 24, an etching process such as an anisotropic dry etching process may be performed to remove some portions of the fourth dielectric layer 311, some portions of the third dielectric layer 309, and a plurality of decoupling features 323. some parts to form a plurality of marking openings 311O. Each sidewall of the plurality of marking openings 311O may be tapered.

Referring to FIG. 25, an isolation layer can be formed to completely fill up the plurality of marking openings 311O. The isolation layer may include a fluorescent material. In some embodiments, the fluorescent material may be azobenzene. In some embodiments, for example, the fabrication technique of the isolation layer may include chemical vapor deposition. A planarization process such as chemical mechanical polishing may be performed until the fourth dielectric layer 311 is exposed to remove excess material, provide a substantially flat surface for subsequent processing steps, and simultaneously convert the isolation layer into a plurality of fourth dielectric layers. Three alignment marks 325 . The contours of the plurality of third alignment marks 325 are determined by the plurality of mark openings 311O. Each sidewall of the plurality of third alignment marks 325 may be tapered.

For brevity, clarity and ease of description, only one decoupling feature 323 and one third alignment mark 325 are described.

In some embodiments, the width W1 between the two recesses 323V of the sidewalls 323SW of the decoupling feature 232 may be greater than the width W2 of the upper surface 325TS of the third alignment mark 325 . In some embodiments, the width W2 of the upper surface 325TS of the third alignment mark 325 may be greater than the width of the third alignment mark 325 at an interface between the intermediate dielectric layer 307 and the third dielectric layer 309 W3. In some embodiments, the width W3 of the third alignment mark 325 at an interface between the intermediate dielectric layer 307 and the third dielectric layer 309 may be greater than the width of the lower surface 325BS of the third alignment mark 325 W4. In some embodiments, the width W3 of the third alignment mark 325 at an interface between the intermediate dielectric layer 307 and the third dielectric layer 309 may be greater than the width W5 of the lower surface 323BS of the decoupling feature 323 . In some embodiments, the width ratio between width W1 and width W5 may be between about 1.5:1 to about 1.1:1 or between about 1.3:1 to about 1.1:1.

The plurality of third alignment marks 325 including fluorescent material can improve optical identification in the subsequent wafer bonding process.

FIG. 26 is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

Please refer to FIG. 26 , the semiconductor device 1D may have a structure similar to that described in FIG. 25 . In FIG. 26, the same or similar elements as in FIG. 25 have been marked with similar element numbers, and their repeated descriptions have been omitted.

In the semiconductor element 1D, the lower surface 325BS of the third alignment mark 325 may be disposed on the decoupling feature 323 instead of extending to the decoupling feature 323 .

An embodiment of the present disclosure provides a semiconductor device, including a first wafer, including a first substrate; and a plurality of first alignment marks, disposed on the substrate and parallel to each other; and a second wafer, disposed It is on the first wafer and includes a plurality of second alignment marks arranged on the plurality of first alignment marks. In a top view, the plurality of second alignment marks is disposed parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks. The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material. The plurality of first alignment marks and the plurality of second alignment marks are configured together to form a first group of alignment marks.

Another embodiment of the present disclosure provides a semiconductor device including a substrate; a dielectric stack disposed on the substrate; two conductive features disposed in the dielectric stack; a decoupling feature disposed on the dielectric stack In, between the two second conductive features, and including a bottle-shaped profile; and an alignment mark, disposed on the decoupling feature. The alignment mark includes a fluorescent material.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a first substrate; forming a plurality of first alignment marks on the first substrate parallel to each other, wherein the first substrate and the plurality of The first alignment marks are configured together according to the first wafer; a second wafer is provided, and the second wafer includes a plurality of second alignment marks parallel to each other; and the second wafer is bonded to the first wafer. on the wafer. In a top view, the plurality of second alignment marks is disposed parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks. The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material.

Still another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming a first dielectric layer on the substrate; forming a second dielectric layer on the first dielectric layer; forming Two second conductive features are on the second dielectric layer; forming an intermediate dielectric layer on the second dielectric layer and surrounding the two second conductive features; performing an extended etching process to form an extended opening in the intermediate dielectric layer forming an electrical layer; forming a decoupling feature in the extended opening; and forming an alignment mark on the decoupling feature. The alignment mark includes a fluorescent material.

Due to the design of the semiconductor device of the present disclosure, the plurality of alignment marks 105, 205, 325 comprising fluorescent material can improve optical recognition during the wafer bonding process. In addition, the complementary design enables the plurality of first alignment marks 105 and the plurality of second alignment marks 205 to become mutually referenced during bonding. Therefore, the yield and reliability of the semiconductor device 1A can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included in the patent scope of this application.

1A: Semiconductor components 1B: Semiconductor components 1C: Semiconductor components 1D: Semiconductor components 1S: The first set of alignment marks 10: Preparation method 100: first wafer 101: First base 103: First conductive feature 105: First alignment mark 107: First underlayment 109: The first upper pad 2S: Second set of alignment marks 20: Preparation method 200: second wafer 201:Second Base 203: Second conductive feature 205: Second alignment mark 207: The second lower pad 209: the second upper pad 3S: The third set of alignment marks 301: third base 303: the first dielectric layer 305: second dielectric layer 307: Intermediate dielectric layer 307E: Expansion opening 307O: opening 309: The third dielectric layer 311: the fourth dielectric layer 311O: marking opening 313: Second conductive feature 315: lower barrier layer 315SW: side wall 317: middle conductive layer 317SW: side wall 319: upper barrier layer 319SW: side wall 321: Interstitial sub-barrier layer 323: Decoupling feature 323BS: Lower surface 323SW: side wall 323V: recess 325: The third alignment mark 325BS: lower surface 325TS: upper surface 4S: Fourth set of alignment marks 5S: Fifth set of alignment marks 501: first material 503: second material 505: The third material 507: The fourth material 509: fifth material 511: isolation layer 601: The first mask layer 603: The second mask layer 605: The third mask layer 607: The fourth mask layer DS: Dielectric stack S: Direction S11: step S13: step S15: step S17: step S19: step S21: step S23: step S25: step T1: Thickness T2: Thickness T3: Thickness T4: Thickness T5: Thickness T6: Thickness T7: Thickness W1: width W2: width W3: width W4: width W5: width X: direction Y: Direction Z: Direction

The disclosure content of the present application can be understood more fully when the drawings are considered together with the embodiments and the patent scope of the application. The same reference numerals in the drawings refer to the same components. FIG. 1 is a schematic flow diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure. 2 to 5 are schematic cross-sectional views illustrating part of a process for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 6 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 7 and 8 are schematic cross-sectional views, illustrating a part of a process of manufacturing a semiconductor device according to an embodiment of the present disclosure along the section line A-A' of FIG. 6 . FIG. 9 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. FIG. 10 is a schematic cross-sectional view illustrating a part of a process for manufacturing a semiconductor device according to an embodiment of the present disclosure along the section line A-A' in FIG. 9 . FIG. 11 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. FIG. 12 is a schematic cross-sectional view illustrating a part of a process for manufacturing a semiconductor device according to an embodiment of the present disclosure along the section line A-A' in FIG. 11 . FIG. 13 is a schematic top view illustrating a semiconductor device according to another embodiment of the present disclosure. FIG. 14 is a schematic flow diagram illustrating a method for fabricating a semiconductor device according to another embodiment of the present disclosure. 15 to 25 are schematic cross-sectional views illustrating part of a process for manufacturing a semiconductor device according to another embodiment of the present disclosure. FIG. 26 is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

1A: Semiconductor components 100: first wafer 101: First base 103: First conductive feature 105: First alignment mark 107: First underlayment 109: The first upper pad 200: second wafer 201:Second Base 203: Second conductive feature 205: Second alignment mark 207: The second lower pad 209: the second upper pad Z: Direction

Claims (36)

A semiconductor element, comprising: a first wafer, including: a first substrate; and a plurality of first alignment marks arranged on the substrate and parallel to each other; and a decoupling feature arranged on one of the first alignment marks in a dielectric stack under an alignment mark and having a bottle-shaped profile, wherein the decoupling feature comprises a porous low-k material; a second wafer disposed on the first wafer, and Including: a plurality of second alignment marks arranged on the plurality of first alignment marks; wherein in a top view, the plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and adjacent to The plurality of first alignment marks are set; wherein the plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material; wherein the plurality of first alignment marks and the plurality of second alignment marks The alignment marks are configured together to form a first set of alignment marks. The semiconductor device as claimed in claim 1, wherein the fluorescent material includes azobenzene. The semiconductor device as claimed in claim 2, further comprising a second group of alignment marks spaced apart from the first group of alignment marks along a first direction; wherein the first group of alignment marks is along a second direction extending, the second direction is perpendicular to the first direction, and the second set of alignment marks is along the first direction extend. The semiconductor device as claimed in claim 3, further comprising a third group of alignment marks spaced apart from the first group of alignment marks along the second direction; wherein the third group of alignment marks is spaced apart from the first group of alignment marks along the first direction extension. The semiconductor device as claimed in claim 4, further comprising a fourth group of alignment marks spaced apart from the first group of alignment marks along a direction that is inclined relative to the first direction and the second direction; wherein The fourth group of alignment marks extends along the second direction. The semiconductor device as claimed in claim 4, further comprising a fifth set of alignment marks spaced apart from the first set of alignment marks along a direction that is inclined relative to the first direction and the second direction ; wherein the fifth group of alignment marks extends along the first direction. The semiconductor device as claimed in claim 2, wherein the first wafer includes a plurality of first conductive features vertically disposed around the plurality of first alignment marks. The semiconductor device as claimed in claim 7, wherein the first wafer includes a first sub-pad disposed between the plurality of first conductive features and the plurality of first alignment marks. The semiconductor device as claimed in claim 8, wherein the first wafer includes a first upper pad disposed on the plurality of first alignment marks and on the first lower pad. The semiconductor device as claimed in claim 9, wherein the second wafer includes a second upper pad disposed between the plurality of second alignment marks and the first upper pad. The semiconductor device as claimed in claim 10, wherein the second wafer includes a plurality of second conductive features vertically surrounding the plurality of second alignment marks and disposed on the second upper pad. The semiconductor device as claimed in claim 11, wherein the second wafer includes a second lower pad disposed between the plurality of second alignment marks and the plurality of second conductive features, and between the plurality of second alignment marks and the plurality of second conductive features. Between the second conductive feature and the second upper pad. The semiconductor device as claimed in claim 2, wherein the first wafer is configured as a plurality of logic chips, and the second wafer is configured as a plurality of memory chips. The semiconductor device according to claim 2, wherein the first wafer is configured as a plurality of memory chips, and the second wafer is configured as a plurality of memory chips. The semiconductor device as claimed in claim 1, wherein the dielectric stack includes a first dielectric layer, a second dielectric layer, an intermediate dielectric layer, a third dielectric layer and a fourth dielectric layer, The first dielectric layer is disposed on the substrate, the second dielectric layer is disposed on the first dielectric layer, the intermediate dielectric layer is disposed on the second dielectric layer, and the third dielectric layer is disposed on On the intermediate dielectric layer, the fourth dielectric layer is disposed on the third dielectric layer, and the two second conductive features and the decoupling feature are disposed in the intermediate dielectric layer. The semiconductor device as claimed in claim 15, wherein the alignment mark is disposed along the fourth dielectric layer and the third dielectric layer, and is disposed on the decoupling feature. The semiconductor device of claim 15, wherein the third alignment mark is disposed along the fourth dielectric layer and the third dielectric layer, and extends to the decoupling feature. The semiconductor device according to claim 15, wherein a width between two recesses of the sidewalls of the decoupling feature is greater than a width of an upper surface of the third alignment mark. A method of manufacturing a semiconductor element, comprising: providing a first substrate with a dielectric stack; forming a decoupling feature in the dielectric stack, and the decoupling feature has a bottle-shaped cross-sectional profile; forming A plurality of first alignment marks are on the first base and are parallel to each other, wherein the first base and the plurality of first alignment marks are configured according to a first wafer; a second wafer is provided, and the second The wafer includes a plurality of second alignment marks parallel to each other; and the second wafer is bonded to the first wafer; wherein in a top view, the plurality of second alignment marks are parallel to the plurality of first alignment marks An alignment mark is disposed adjacent to the plurality of first alignment marks; wherein the plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material. The method for manufacturing a semiconductor element as claimed in claim 19, wherein the fluorescent material includes azobenzene, and the plurality of first alignment marks and the plurality of second alignment marks are arranged together to form a first group of alignment marks . The method of manufacturing a semiconductor device as claimed in claim 20, further comprising a second group of alignment marks spaced apart from the first group of alignment marks along a first direction; wherein the first group of alignment marks is along the A second direction extends, the second direction is perpendicular to the first direction, and the second group of alignment marks extends along the first direction. The method of manufacturing a semiconductor element as claimed in claim 21, further comprising a third group of alignment marks separated from the first group of alignment marks along the second direction; wherein the third group of alignment marks is along the The first direction extends. The method for manufacturing a semiconductor element as claimed in claim 22, further comprising a fourth set of alignment marks spaced apart from the first set of alignment marks along a direction opposite to the first direction and the second direction inclined; wherein the fourth set of alignment marks extends along the second direction. The method for manufacturing a semiconductor device as claimed in claim 22, further comprising a fifth set of alignment marks spaced apart from the first set of alignment marks along a direction that is opposite to the first direction and the second set of alignment marks Two directions are inclined; wherein the fifth set of alignment marks extends along the first direction. The method of manufacturing a semiconductor device as claimed in claim 20, wherein the first wafer includes a plurality of first conductive features vertically disposed around the plurality of first alignment marks. The method of manufacturing a semiconductor device as claimed in claim 25, wherein the first wafer includes a first lower pad disposed between the plurality of first conductive features and the plurality of first alignment marks. The method of manufacturing a semiconductor device as claimed in claim 26, wherein the first wafer includes a first upper pad disposed on the plurality of first alignment marks and on the first lower pad. The method of manufacturing a semiconductor device as claimed in claim 27, wherein the second wafer includes a second upper pad disposed between the plurality of second alignment marks and the first upper pad. The method of manufacturing a semiconductor device as claimed in claim 28, wherein the second wafer includes a plurality of second conductive features vertically surrounding the plurality of second alignment marks and disposed on the second upper pad. The method for preparing a semiconductor element as claimed in claim 29, wherein the second wafer includes a second lower pad disposed between the plurality of second alignment marks and the plurality of second conductive features, and between the plurality of second alignment marks and the plurality of second conductive features. Between the plurality of second conductive features and the second upper pad. The method for manufacturing a semiconductor device as claimed in claim 20, wherein the first wafer is configured as a plurality of logic chips, and the second wafer is configured as a plurality of memory chips. The method for preparing a semiconductor element as claimed in item 20, wherein the first wafer is configured as A plurality of memory chips, and the second wafer is configured as a plurality of memory chips. The method for preparing a semiconductor device as claimed in item 19, wherein the dielectric stack includes a first dielectric layer, a second dielectric layer, an intermediate dielectric layer, a third dielectric layer and a fourth dielectric layer electrical layer, the first dielectric layer is disposed on the substrate, the second dielectric layer is disposed on the first dielectric layer, the intermediate dielectric layer is disposed on the second dielectric layer, the third dielectric layer An electrical layer is disposed on the intermediate dielectric layer, the fourth dielectric layer is disposed on the third dielectric layer, and the two second conductive features and the decoupling feature are disposed in the intermediate dielectric layer. The method of manufacturing a semiconductor device as claimed in claim 33, wherein the alignment mark is disposed along the fourth dielectric layer and the third dielectric layer, and is disposed on the decoupling feature. The method of manufacturing a semiconductor device as claimed in claim 33, wherein the third alignment mark is disposed along the fourth dielectric layer and the third dielectric layer, and extends to the decoupling feature. The method of manufacturing a semiconductor device as claimed in claim 33, wherein a width between two recesses of the plurality of sidewalls of the decoupling feature is greater than a width of an upper surface of the third alignment mark.