TWI804379B - Semiconductor device with charge effect reduction by plasma damage and method for forming the same - Google Patents

Abstract

The present invention discloses a manufacturing method of a dummy gate device for reducing the plasma electrostatic effect of a semiconductor device. The steps include constructing a metal oxide semiconductor device on a substrate, and forming a first transistor having a drain contact hole, a source contact hole and a gate contact hole are formed, and a second transistor is formed, which only has a dummy gate contact hole； an internal insulating layer is formed on the first transistor and the second transistor, and is formed on the first transistor and the second transistor. A drain metal layer, a source metal layer and a gate metal layer are formed above the internal barrier layer, and the gate metal layer is electrically connected through the gate contact hole and the dummy gate contact hole to reduce the electrostatic effect of the semiconductor element.

Description

Manufacturing Method for Reducing Plasma Electrostatic Effect of Semiconductor Components

The present invention (creation) relates to a semiconductor element device and its manufacturing method, in particular to a device with a dummy gate semiconductor and its manufacturing method.

Semiconductor components are often subject to the electrostatic effect generated in the back-stage plasma process. The first thing to bear the brunt is that the static electricity generated by the plasma passes through the conduction of the metal interconnection in the back-end and consumes the gate electrode of the transistor, which causes the critical voltage of the transistor to rise and seriously affects the stability of the transistor. Low-temperature plasma etching technology is often used in the back-end metal interconnection process. However, although the plasma-released ionization etching technology is suitable for low-temperature back-end processes, it also causes a lot of sequelae of electrostatic charge and discharge, which is called plasma-induced charge. damage (PID), such as gate dielectric layer failure, dielectric layer time-dependent breakdown characteristics (time dependent dielectric breakdown, TDDB), negative bias temperature instability (negative bias temperature instability, NBTI), positive bias Pressure-temperature instability (positive bias temperature instability, PBTI) and hot carrier injection (hot carrier injection, HCI) effects, etc.; therefore, the instability of component reliability caused by the plasma process is very sensitive to the production of integrated circuits. Especially more important in the case of High-K gate components and scaling.

There are generally several solutions to the instability caused by PID to semiconductor components. For example, an allowable antenna ratio (Antenna Ratio, AR) will be designed on the circuit to disperse the PID effect [Republic of China Patent GA-3855081, Republic of China Patent GA -I587448] or add protection diode to release charge [Republic of China Patent GA-472357, Republic of China Patent GA-522543, Republic of China Patent GA-569453], or even add an advanced Al Pad structure that resists plasma damage [Republic of China Patent GA-I490987], but the complexity of the manufacturing process is also increased, and the cost of wafer production is also increased.

In order to solve the electrostatic loss, this patent project designs a dummy gate contact that can be used to disperse the influence of plasma electrostatic loss on the transistor through a novel circuit layout method.

The invention provides a method for manufacturing a dummy gate device that reduces the plasma electrostatic effect of a semiconductor element. The steps are as follows: provide a substrate, form a semiconductor layer on the substrate, perform ion implantation on the semiconductor layer, and construct a metal oxide semiconductor The device is installed on the substrate, wherein the construction of the metal oxide semiconductor device includes the following steps: forming a first transistor, forming a drain and a source at both ends of an active region mask area of the first transistor, A drain contact hole is formed above the drain, and a source contact hole is formed above the source; a gate is formed above the active region mask by a gate mask, and a gate is formed above the gate A gate contact hole; a second transistor is formed, a dummy drain and a dummy source are respectively formed at both ends of a dummy active area mask of the second transistor, and a dummy drain and a dummy source are formed above the dummy drain and the dummy No contact hole is formed above the source; a dummy gate is formed above the dummy active region photomask by a dummy gate photomask, and a dummy gate contact hole is formed above the dummy gate; an internal barrier layer is formed, The internal barrier layer is formed above the first transistor and the second transistor.

Furthermore, forming a metal layer group above the internal barrier layer includes the following steps: respectively forming a drain metal layer and a source metal layer above the first transistor and the second transistor along a first transistor. The opposite ends of one direction extend and are electrically connected to the drain metal layer and the source metal layer through the drain contact hole and the source contact hole respectively; formed above the gate and the dummy gate A gate metal layer extends along a second direction, the second direction is substantially perpendicular to the first direction, and is electrically connected to the gate metal layer through the gate contact hole and the dummy gate contact hole respectively.

Preferably, the material of the substrate is a silicon-covered insulating substrate.

Preferably, the substrate is made of glass, quartz, diamond, plastic or other single-layer insulating substrates.

Preferably, the material of the substrate is silicon, germanium or III-V group wafer substrate.

Preferably, the substrate is made of germanium-coated insulating or III-V group-coated insulating substrate.

Further, the method further includes the step of: a buried oxide layer, the buried oxide layer is formed on the substrate.

Furthermore, the method further comprises a step: the buried oxide layer forms a channel, and the channel connects the substrate and the metal oxide semiconductor device.

Specifically, the material of the internal barrier layer is selected from the group consisting of silicon dioxide, silicon nitride, oxygen nitrogen oxide (ONO), air cavity (Air Gap), metal silicide and metal with different doping impurity concentrations. One or a combination of groups.

Preferably, the material of the semiconductor layer is one selected from the group consisting of a single layer or a multilayer of Group IV or III-V materials.

Furthermore, the gate and the dummy gate are made of a metal silicide layer and a polysilicon layer, the metal silicide layer is on the polysilicon layer, the gate and the dummy gate are formed opposite to the On the semiconductor layer where the metal oxide semiconductor device is located.

Preferably, the material of the gate and the dummy gate is a single layer or multiple layers of suitable metal.

Compared with the conventional technology, the present invention has the effects of dispersing the influence of plasma static loss on the transistor and improving the stability of the transistor.

In order to enable those with ordinary knowledge in the technical field to understand the content of the present invention and realize the content of the present invention accordingly, the following descriptions will be made with appropriate embodiments in conjunction with the drawings, and equivalent replacements and modifications based on the content of the present invention will be made. All are included in the scope of rights of the present invention. In addition, it is stated that the quantifier "a" or "an" used throughout the present invention is to express the general meaning of the scope of the present invention, and it should be interpreted as including one or at least one in the present invention. One, and a single concept also includes a plurality of cases, unless it is clearly intended otherwise in the present invention.

As shown in Figure 1, it is a schematic diagram of a conventional semiconductor photomask layout. A first transistor is formed, and a drain and a source are respectively formed at both ends of an active region photomask 101 area of the first transistor, and A drain contact hole 103 is formed above the drain, and a source contact hole 102 is formed above the source; a gate is formed using a gate mask 100 above the active region mask 101, and a gate is formed on the gate A gate contact hole 104 is formed above the pole; no dummy gate contact hole is formed in the conventional second transistor dummy gate mask 200 and no drain contact hole 103 and source contact hole 102 are formed in the dummy active region mask 201 An internal barrier layer is formed above the transistor, and a metal layer group is formed above the internal barrier layer, wherein a drain metal layer 106 and a source metal layer are respectively formed above the first transistor and the second transistor The layer 105 extends along opposite ends of a first direction, and is electrically connected to the drain metal layer 106 and the source metal layer 105 respectively through the drain contact hole 103 and the source contact hole 102; A gate metal layer 107 is formed on the gate photomask 100 and the dummy gate photomask 200, extending along a second direction, the second direction is substantially perpendicular to the first direction, and only the gate contact hole 104 and the gate The pole metal layer 107 is electrically connected.

Please refer to FIG. 3. FIG. 3 is a side view of a conventional semiconductor photomask layout. The gate metal layer 107 is only electrically connected to the gate contact hole 104 formed on the gate photomask 100; No dummy gate contact holes are formed on the aurora mask 200 .

Please refer to FIG. 2. FIG. 2 is a schematic diagram of the photomask layout of a semiconductor dummy gate device according to an embodiment of the present invention. The manufacturing method of the dummy gate device is as follows: provide a substrate, form a semiconductor layer on the substrate, and Ion implantation is performed on the layer, and a metal oxide semiconductor device is constructed on the substrate, including the following steps: forming a first transistor, and forming a drain at both ends of the active region mask 101 area of the first transistor and a source electrode, and form a drain electrode contact hole 103 above the drain electrode, and form a source electrode contact hole 102 above the source electrode; use a gate electrode mask 100 to form a gate above the active region mask 101 pole, and a gate contact hole 104 is formed above the gate; a second transistor is formed, and a dummy drain and a dummy drain are respectively formed at both ends of a dummy active region mask 201 layout diagram 201 of the second transistor. dummy source, and no contact hole is formed above the dummy drain and above the dummy source; a dummy gate is formed using a dummy gate mask 200 above the dummy active region mask 201, and a dummy gate is formed on the dummy gate A dummy gate contact hole 306 is formed above the electrode; an internal barrier layer is formed above the first transistor and the second transistor.

Moreover, forming a metal layer group includes the following steps: respectively forming a drain metal layer 106 and a source metal layer 105 above the first transistor and the second transistor and respectively facing each other along a first direction. Both ends extend and are electrically connected to the drain metal layer 106 and the source metal layer 105 through the drain contact hole 103 and the source contact hole 102 respectively; formed above the gate and the dummy gate A gate metal layer 107 extends along a second direction, the second direction is substantially perpendicular to the first direction, and is electrically connected to the gate metal layer 107 through the gate contact hole 104 and the dummy gate contact hole 306 respectively. sexual connection.

Please refer to FIG. 4 , which is a side view of the photomask layout of the semiconductor dummy gate device of the present invention, the gate metal layer 107 is electrically connected to the gate contact hole 104 formed on the gate photomask 100; A dummy gate contact hole 306 is formed on the dummy gate photomask 200 , and the dummy gate contact hole 306 is electrically connected to the gate metal layer 107 .

Preferably, the material of the substrate is a silicon-covered insulating substrate, but not limited thereto.

Preferably, the material of the substrate is glass, quartz, diamond, plastic or other single-layer insulating substrates, but not limited thereto.

Preferably, the material of the substrate is silicon, germanium or III-V wafer substrate, but not limited thereto.

Preferably, the material of the substrate is a germanium-covered insulating substrate or a III-V group covered insulating substrate, but not limited thereto.

Further, the step of forming a buried oxide layer is further included, and the buried oxide layer is formed on the substrate.

Furthermore, the method further comprises the step of forming a channel in the buried oxide layer, and the channel connects the substrate and the metal oxide semiconductor device.

Specifically, the material of the internal barrier layer is selected from the group consisting of silicon dioxide, silicon nitride, oxygen nitrogen oxide (ONO), air cavity (Air Gap), metal silicide and metal with different doping impurity concentrations. One or a combination of groups.

Preferably, the material of the semiconductor layer is one selected from the group consisting of a single layer or a multilayer of Group IV or III-V materials.

Furthermore, the gate and the dummy gate are made of a metal silicide layer and a polysilicon layer, the metal silicide layer is on the polysilicon layer, the gate and the dummy gate are formed opposite to the On the semiconductor layer where the metal oxide semiconductor device is located.

Preferably, the material of the gate and the dummy gate is a single layer or multiple layers of suitable metal.

Another embodiment of the present invention is a dummy gate device for reducing the plasma electrostatic effect of semiconductor elements, including: a metal oxide semiconductor device, which is formed by a semiconductor layer and located on a substrate, and the metal oxide semiconductor device includes: A first transistor has an active mask 101 and a gate mask 100, wherein a drain and a source are respectively formed at both ends of the active mask 101, and a drain contact is formed above the drain hole 103, and a source contact hole 102 is formed above the source; the gate mask 100 is located above the active region mask 101 to form a gate, and a gate contact hole 104 is formed above the gate; a first Two transistors, with a dummy active mask 201 and a dummy gate mask 200, wherein a dummy drain and a dummy source are respectively formed at both ends of the dummy active mask 201, above the dummy drain and No contact hole is formed above the dummy source; the dummy gate photomask 200 is located above the dummy active region photomask 201 to form a dummy gate, and a dummy gate contact hole 306 is formed above the dummy gate; a metal layer group, including: a drain metal layer 106, a source metal layer 105 and a gate metal layer 107, wherein the drain metal layer 106 and the source metal layer 105 are located in the first transistor and the second transistor respectively The two transistors extend above the opposite ends along a first direction, and are electrically connected to the drain metal layer 106 and the source metal layer 105 through the drain contact hole 103 and the source contact hole 102 respectively. The gate metal layer 107, located above the gate and the dummy gate, extends along a second direction, the second direction is substantially perpendicular to the first direction, passing through the gate contact hole 104 and the dummy gate respectively The contact hole 306 is electrically connected to the gate metal layer 107; and, an internal barrier layer is interposed between the metal layer group and the first transistor and the second transistor.

Preferably, the substrate is a silicon-covered insulating substrate, but not limited thereto.

Preferably, the substrate is glass, quartz, diamond, plastic or other single-layer insulating substrates, but not limited thereto.

Preferably, the substrate is a silicon, germanium or III-V group wafer substrate, but not limited thereto.

Preferably, the substrate is a germanium-coated insulating or III-V group-coated insulating substrate, but not limited thereto.

Further, a buried oxide layer is formed on the substrate, and the buried oxide layer is between the substrate and the metal oxide semiconductor device.

Furthermore, the buried oxide layer has a channel, and the channel connects the substrate and the metal oxide semiconductor device.

Specifically, the material of the internal barrier layer is selected from the group consisting of silicon dioxide, silicon nitride, oxygen nitrogen oxide (ONO), air cavity (Air Gap), metal silicide and metal with different doping impurity concentrations. One or a combination of groups.

Preferably, the semiconductor layer is selected from the group consisting of a single layer or a multilayer of Group IV or III-V materials.

Furthermore, the gate and the dummy gate have a metal silicide layer and a polysilicon layer, the metal silicide layer is on the polysilicon layer, the gate and the dummy gate are formed opposite to the metal oxide semiconductor device location on the semiconductor layer.

Preferably, the material of the gate and the dummy gate is a single layer or multiple layers of suitable metal.

To sum up, the purpose of the present invention is to solve the lack of the aforementioned prior art that affects the stability of the transistor due to the static electricity generated by the plasma process. In order to achieve the above purpose, the present invention provides a device with a pseudo-gate semiconductor and its manufacture The method uses the novel circuit layout method of the present invention to disperse the influence of plasma static loss on the transistor and improve the stability of the transistor.

100: Transistor gate (Poly) mask 101: Transistor active area (OD) mask 102: Transistor source contact hole (Source Contact) mask 103: Transistor drain contact hole (Drain Contact) mask 104: Transistor gate contact hole (Gate Contact) mask 105: Transistor source metal layer (Source M1) mask 106: Transistor drain metal layer (Drain M1) mask 107: Transistor gate metal layer (Gate M1) mask 200: Transistor dummy gate (Dummy Poly) mask 201: Transistor dummy active area (Dummy OD) mask 306:Dummy Gate Contact mask

FIG. 1 is a schematic diagram of a conventional semiconductor photomask layout.

FIG. 2 is a schematic diagram of the mask layout of the semiconductor dummy gate device of the present invention.

Figure 3 is a side view of a conventional semiconductor photomask layout

Fig. 4 is a side view of the photomask layout of the semiconductor dummy gate device of the present invention

100: Transistor gate (Poly) mask

101: Transistor active area (OD) mask

102: Transistor source contact hole (Source Contact) mask

103: Transistor drain contact hole (Drain Contact) mask

104: Transistor gate contact hole (Gate Contact) mask

105: Transistor source metal layer (Source M1) mask

106: Transistor drain metal layer (Drain M1) mask

107: Transistor gate metal layer (Gate M1) mask

200: Transistor dummy gate (Dummy Poly) mask

201: Transistor dummy active area (Dummy OD) mask

306:Dummy Gate Contact mask

Claims (10)

A method of manufacturing a dummy gate device for reducing the plasma electrostatic effect of a semiconductor element, the steps are as follows: A substrate is provided, a semiconductor layer is formed on the substrate, ion implantation is performed on the semiconductor layer, and a metal oxide semiconductor device is constructed on the substrate, comprising the following steps: A first transistor is formed, a drain and a source are respectively formed at both ends of an active region mask area of the first transistor, and a drain contact hole is formed above the drain, and a drain contact hole is formed above the source forming a source contact hole; using a gate photomask to form a gate above the active region photomask, and forming a gate contact hole above the gate; A second transistor is formed, a dummy drain and a dummy source are respectively formed at both ends of a dummy active region mask of the second transistor, and no dummy source is formed above the dummy drain and above the dummy source. a contact hole; a dummy gate is formed by using a dummy gate photomask above the dummy active area mask, and a dummy gate contact hole is formed above the dummy gate; forming an internal barrier layer, forming the internal barrier layer over the first transistor and the second transistor; and, Forming a metal layer group includes the following steps: A drain metal layer and a source metal layer are respectively formed above the first transistor and the second transistor and extend along opposite ends of a first direction respectively, and respectively pass through the drain contact hole and the source a pole contact hole is electrically connected with the drain metal layer and the source metal layer; and A gate metal layer is formed above the gate and the dummy gate, extending along a second direction, the second direction is substantially perpendicular to the first direction, and passing through the gate contact hole and the dummy gate contact hole respectively It is electrically connected with the gate metal layer. The method of manufacturing a dummy gate device for reducing the plasma electrostatic effect of a semiconductor element as described in claim 1, wherein the material of the substrate is a silicon-coated insulating substrate. The method of manufacturing a dummy gate device for reducing the plasma electrostatic effect of a semiconductor element as described in claim 1, wherein the substrate is made of glass, quartz, diamond, plastic or other single-layer insulating substrates. The method of manufacturing a dummy gate device for reducing the plasma electrostatic effect of a semiconductor device as described in claim 1, wherein the substrate is made of silicon, germanium or a III-V wafer substrate. The method of manufacturing a dummy gate device for reducing the plasma electrostatic effect of a semiconductor device as described in Claim 1, wherein the material of the substrate is a germanium-coated insulating or III-V group-coated insulating substrate. The method of manufacturing a dummy gate device for reducing the plasma electrostatic effect of a semiconductor element as described in Claim 1 further includes forming a buried oxide layer, and the buried oxide layer is formed on the substrate. The manufacturing method of the dummy gate device for reducing the plasma electrostatic effect of the semiconductor device according to claim 6, wherein the buried oxide layer forms a channel, and the channel connects the substrate and the metal oxide semiconductor device. The method of manufacturing a dummy gate device for reducing the plasma electrostatic effect of a semiconductor element as described in Claim 1, wherein the material of the internal barrier layer is selected from silicon dioxide, silicon nitride, oxygen nitrogen oxide (ONO), air Cavities (Air Gap), metal silicides and metals with different doping impurity concentrations, one or a combination thereof. The method of manufacturing a dummy gate device for reducing the plasma electrostatic effect of a semiconductor element as described in Claim 1, wherein the material of the semiconductor layer is selected from a single-layer or multi-layer group consisting of Group IV or III-V materials One of. The method of manufacturing a dummy gate device for reducing the plasma electrostatic effect of a semiconductor element as described in claim 1, wherein the gate and the dummy gate are made of a metal silicide layer and a polysilicon layer, and the metal silicide The material layer is on the polysilicon layer, and the gate and the dummy gate are formed on the semiconductor layer relative to the position of the metal oxide semiconductor device.

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