TWI870765B - Component manufacturing method of new circuit layout effect - Google Patents

Abstract

The present invention discloses a new type of circuit layout effect component manufacturing method, the steps include the stage of forming an integrated circuit, the stage of parameter definition and the stage of circuit module design. The present invention includes four sets of parameters such as LOD, OSE, WPE, and PSE. A systematic LDE (Layout dependence effect) pattern is designed based on the gate element (Multi-finger device), and a complete inspection is provided for the non-symmetrical SA/SB variation, in order to greatly improve the accuracy of element modeling.

Description

New circuit layout effect component manufacturing method

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a device with a novel circuit layout effect.

Layout dependence effect (LDE) is an important parameter in semiconductor device modeling, which makes the overall SPICE model more accurate. Unfortunately, the current industry's review of LDE still focuses on the variation of the transistor itself. There are two serious problems that have been ignored for a long time: (1) Model fitting does not take into account the accuracy of standard cells (such as inverter, NOR, NAND, SRAM, ring oscillator, multi-finger device, etc.), which will seriously affect the performance of the entire circuit. However, as the size of transistors continues to shrink, the tolerance for errors decreases, resulting in a decrease in yield. Therefore, foundries need more and more accurate LDE patterns to correct the errors of standard cells; (2) Nowadays, chips for automotive, gaming, biomedical, power, sensor, IoT, etc. are flourishing and becoming more popular. The technical difficulty of these mature components does not lie in the pursuit of the performance of small-line width, high-speed/high-power basic logic components, but in chip integration that exceeds Moore's Law. In recent years, "More than Moore's Law" has occupied an extremely important research position in world-class semiconductor component conferences. Under Moore's Law, the reduction of transistor size will face the test of physical limits. For example, the integrated performance chip with HV, BCD, and eFlash on the logic component at the same time has a huge market in the industry, and more and more IC design houses are working on it. The customer's request for a combined chip not only increased the difficulty of the integrated chip manufacturing process, but also caused the logic components themselves to be subject to additional process conditions and had to be adjusted. However, the key point is that LDE was not re-examined. If this factor is not taken into account, the integrated chip circuit will have serious consequences.

Therefore, in view of the above-mentioned shortcomings of LDE, Multi-finger TKs are more often seen in actual standard cell layout environments, such as NOR, NAND, Ring Oscillator and other circuits. In order to fully realize the effect of circuit-level device layout patterns (LDE), the present invention proposes a LDE pattern for multi-gate devices (Multi-finger devices). This pattern TK design includes asymmetric SA/SB variables. Based on this as a reference point, splits are made for LOD, OSE, WPE, and PSE layout variables, which can greatly improve the accuracy of device modeling.

LDE is used in a series of transistor layout parameters and is also an important bridge that connects integrated circuit characteristics from the component level to the circuit level. SPICE model uses layout parameter extraction (LPE) and circuit netlist to describe basic standard cell characteristics during post-layout simulation. Previous patents only reported similar layout improvements [Republic of China Patent Certificate No.: TW I688874 B Integrated circuit and layout design method thereof] and [Republic of China Patent Certificate No.: TW 202009598 A Integrated circuit including standard cells], without any specific description or proposal for LDE. However, previous papers have shown that the STI process will form an environment surrounded by oxide stress around the OD active area. This stress presents an uneven state to the MOSFET gate channel and significantly affects the transistor Vth, peak gm, and Idsat/Idlin.

For LOD, it changes according to the distance SA/SB from the left and right gates to the OD edge. For OSE, it changes with the changes in the front, back, left, and right STI oxide space. LOD needs to take into account the gate channel constant length (L), and its relationship model with stress has been previously studied and discussed, for example: Vladimír Stejskal, et al., "LOD Effect: Modeling and Implementation," ON Semiconductor (2016), Ke-Wei Su, et al., "A Scaleable Model for STI Mechanical Stress Effect on Layout Dependence of MOS Electrical Characterization," 2003 IEEE Custom Integrated Circuits Conference (CICC), pp.245-248 (2003) and G. Scott, et al., "NMOS Drive Current Reduction Caused by Transistor Layout and Trench, and applied to the existing SPICE model; the present invention uses a multi-finger device as the basis to design a systematic LDE pattern, including LOD, OSE, WPE, PSE, provides a complete check for non-correlated SA/SB changes, as described below:

The present invention provides a novel circuit layout effect device manufacturing method for LOD circuit module design, the steps are as follows: an integrated circuit formation stage, including: an active region (OD) mask, formed on a substrate, a rectangular active region mask area is formed by the mask; and a multi-gate transistor is formed on the active region (OD) mask by the transistor mask, including: a gate (Poly) mask, a plurality of dummy gate (Dummy Poly) masks and a plurality of source and drain contact holes (Source Contact) masks, wherein the gate (Poly) mask and the plurality of dummy gates (Dummy Poly) masks are respectively parallel to a first direction of the substrate and have a spacing along a second direction orthogonal to the first direction, the plurality of source and drain contact holes (Source Contact) masks are respectively placed on the left and right sides of the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks, a gate contact hole (Gate A contact) mask is formed on the gate (Poly) mask; a LOD parameter definition stage, including: an SA parameter and an SB parameter, wherein the SA parameter is the distance from the left edge of the gate (Poly) mask to the left edge of the active region (OD) mask, and the SB parameter is the distance from the right edge of the gate (Poly) mask to the right edge of the active region (OD) mask; and, a LOD circuit module design stage: the SA parameter and the SB parameter are subjected to circuit simulation analysis.

The present invention provides a second novel circuit layout effect device manufacturing method for OSE circuit module design, the steps are as follows: an integrated circuit formation stage, including: an active area (OD) mask, formed on a substrate, the mask forms a rectangular active area mask area; a plurality of dummy active area (Dummy OD) masks, formed on a substrate, the masks form a plurality of rectangular areas, wherein the plurality of dummy active area (Dummy OD) masks are respectively spaced on both sides of the first direction of the active area (OD) mask and on both sides of the second direction orthogonal to the first direction, the active area (OD) mask and the plurality of dummy active areas (Dummy OD) masks are spaced on both sides of the first direction of the active area (OD) mask. The active region (OD) mask is separated by a non-mask; a multi-gate transistor is formed by a transistor mask on the active region (OD) mask, comprising: a gate (Poly) mask, a plurality of dummy gate (Dummy Poly) masks, and a plurality of source and drain contact holes (Source Contact) masks, wherein the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks are respectively parallel to a first direction of the substrate and have a spacing along a second direction orthogonal to the first direction, the plurality of source and drain contact holes (Source Contact) masks are respectively placed on the left and right sides of the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks, and a gate contact hole (Gate Contact) mask is provided on the left and right sides of the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks. A poly contact mask is formed on the gate mask; and a plurality of dummy gate transistors are formed on the dummy active region (Dummy OD) mask by a transistor mask, wherein a plurality of dummy gate masks are respectively parallel to a first direction of the substrate and have a spacing along a second direction orthogonal to the first direction; an OSE parameter definition stage, comprising: an OSE_X1 parameter, an OSE_X2 parameter, an OSE_Y1 parameter and an OSE_Y2 parameter, wherein the OSE_X1 parameter is the distance from the left side of the active region (OD) mask to the left side of the plurality of dummy active regions (Dummy OD) masks, and the OSE_X2 parameter is the distance from the right side of the active region (OD) mask to the right side of the plurality of dummy active regions (Dummy The OSE_Y1 parameter is the distance from the upper edge of the active area (OD) mask to the plurality of dummy active area (Dummy OD) masks above, and the OSE_Y2 parameter is the distance from the lower edge of the active area (OD) mask to the plurality of dummy active area (Dummy OD) masks below; and, an OSE circuit module design stage: performing circuit simulation analysis on the OSE_X1 parameter, the OSE_X2 parameter, the OSE_Y1 parameter and the OSE_Y2 parameter.

The present invention provides a third novel circuit layout effect device manufacturing method for PSE circuit module design, the steps are as follows: an integrated circuit formation stage, including: an active region (OD) mask, formed on a substrate, a rectangular active region mask area is formed by the mask; and a multi-gate transistor is formed on the active region (OD) mask by the transistor mask, including: a gate (Poly) mask, a plurality of dummy gate (Dummy Poly) masks and a plurality of source and drain contact holes (Source Contact) masks, wherein the gate (Poly) mask and the plurality of dummy gates (Dummy Poly) masks are respectively parallel to a first direction of the substrate and have a spacing along a second direction orthogonal to the first direction, the plurality of source and drain contact holes (Source Contact) masks are respectively placed on the left and right sides of the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks, a gate contact hole (Gate A contact mask is formed on the gate (Poly) mask; a PSE parameter definition stage, including: a PS1 parameter and a PS2 parameter, wherein the PS1 parameter is the distance from the left side of the gate (Poly) mask to the first dummy gate on the left side, and the PS2 parameter is the distance from the right side of the gate (Poly) mask to the first dummy gate on the right side; and a PSE circuit module design stage: the PS1 parameter and the PS2 parameter are subjected to circuit simulation analysis.

The present invention provides a fourth novel circuit layout effect device manufacturing method for WPE circuit module design, the steps are as follows: an integrated circuit formation stage, including: an active region (OD) mask, formed on a substrate, a rectangular active region mask area is formed by the mask; a multi-gate transistor is formed on the active region (OD) mask by the transistor mask, including: a gate (Poly) mask, a plurality of dummy gate (Dummy Poly) masks and a plurality of source and drain contact holes (Source Contact) masks, wherein the gate (Poly) mask and the plurality of dummy gates (Dummy Poly) masks are respectively parallel to a first direction of the substrate and have a spacing along a second direction orthogonal to the first direction, the plurality of source and drain contact holes (Source Contact) masks are respectively placed on the left and right sides of the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks, a gate contact hole (Gate A contact) mask is formed on the gate (Poly) mask; and a transistor well (Well) mask is formed on a substrate, formed by the mask and larger than and surrounding the rectangular active area mask area; a WPE parameter definition stage, including: a WPE_X1 parameter, a WPE_X2 parameter, a WPE_Y1 parameter and a WPE_Y2 parameter, wherein the WPE_X1 parameter is the distance from the left side of the active area (OD) mask to the left transistor well (Well) mask, and the WPE_X2 parameter is the distance from the left side of the active area (OD) mask to the left transistor well (Well) mask. is the distance from the right side of the active area (OD) mask to the right transistor well (Well) mask, the WPE_Y1 parameter is the distance from the upper edge of the active area (OD) mask to the upper transistor well (Well) mask, and the WPE_Y2 parameter is the distance from the lower edge of the active area (OD) mask to the lower transistor well (Well) mask; and, a WPE circuit module design stage: the WPE_X1 parameter, the WPE_X2 parameter, the WPE_Y1 parameter and the WPE_Y2 parameter are subjected to circuit simulation analysis.

Specifically, the substrate in the present invention is a silicon-coated insulating substrate, glass, quartz, diamond, plastic or other single-layer insulating substrate.

Furthermore, the substrate in the present invention can be a silicon, germanium or III-V group wafer substrate.

Furthermore, in the present invention, the substrate is a germanium-clad insulating substrate or a III-V-clad insulating substrate.

Furthermore, the substrate in the present invention further comprises a base and a buried oxide layer, the buried oxide layer is formed on the base, and an active region is formed between the buried oxide layer and the base.

Specifically, the buried oxide layer described in the present invention is an internal barrier layer, and the material of the buried oxide layer is selected from the group consisting of silicon dioxide, silicon nitride, oxygen-nitrogen-oxygen (ONO), air gap, metal silicide with different doping concentrations, and metal.

Furthermore, the substrate is selected from the group consisting of a single layer and a multi-layer consisting of Group IV or Group III-V semiconductor materials.

Specifically, the gate formed by the gate (Poly) mask includes a metal silicide layer and a polysilicon layer, and the metal silicide layer is on the polysilicon layer.

Furthermore, the gate (Poly) mask forms a gate, the gate can be a single layer or multiple layers of metal and the substrate further includes a buried gate oxide layer, the buried gate oxide layer is between the gate and the substrate.

Specifically, the number of the plurality of dummy gate (Dummy Poly) masks can be 1 to 32, the width of the active area (OD) mask increases with the increase in the number of the plurality of dummy gate (Dummy Poly) masks, and the gate contact hole (Gate Contact) mask position can be independently connected to any gate (Poly).

As mentioned above, the device manufacturing method based on the novel circuit layout effect of the present invention can achieve the following effects: (1) Reduce the error of standard cells and improve the transistor yield (2) Reduce the difficulty of the integrated chip manufacturing process

In order to enable those with ordinary knowledge in the relevant technical field to understand the content of the present invention and to implement the content of the present invention accordingly, the following is explained with appropriate embodiments in conjunction with diagrams. Equivalent replacements and modifications based on the content of the present invention are all included in the scope of rights of the present invention. In addition, it is stated that the quantifiers "one" or "an" used throughout the present invention are used to express the usual meaning of the scope of the present invention, and should be interpreted in the present invention as including one or at least one, and a single concept also includes plural situations, unless other meanings are clearly intended in the present invention.

The first embodiment of the present invention is a method for designing and manufacturing a LOD circuit module. Please refer to FIG1, which is a schematic diagram of a known multi-gate MOSFET mask layout. The present invention provides a method for manufacturing a component with a novel circuit layout effect for designing a LOD circuit module. Please refer to FIG7, which is a schematic diagram of the steps of the method for manufacturing a component with a novel circuit layout effect of the present invention. The steps are as follows: (1) An integrated circuit formation stage S10 includes: an active region (OD) mask 101 formed on a substrate 001, and a rectangular active region mask area is formed by the mask; and a multi-gate transistor is formed on the active region (OD) mask 101 by a transistor mask, including: a gate (Poly) mask 100, a plurality of dummy gate (Dummy Poly) masks 104 and a plurality of source and drain contact holes (Source Contact) masks 102, wherein the gate (Poly) mask 100 and the plurality of dummy gate (Dummy Poly) masks 104 are respectively parallel to a first direction of the substrate 001 and have a spacing along a second direction orthogonal to the first direction, and the plurality of source and drain contact holes (Source Contact) masks 102 are parallel to the ... A gate contact mask 102 is placed on the left and right sides of the gate (Poly) mask 100 and the plurality of dummy gate (Dummy Poly) masks 104, respectively, and a gate contact hole (Gate Contact) mask 103 is formed on the gate (Poly) mask 100; (2) A LOD parameter definition stage S20, please refer to FIG. 2, FIG. 2 is a schematic diagram of the LOD (Length Of Diffusion) mask layout of the multi-gate MOSFET design of the present invention; the LOD parameter definition stage includes: an SA 200 parameter and an SB 201 parameter, wherein the SA The SA 200 parameter is the distance from the left edge of the gate (Poly) mask 100 to the left edge of the active region (OD) mask 101, and the SB 201 parameter is the distance from the right edge of the gate (Poly) mask 100 to the right edge of the active region (OD) mask 101; and, (3) A LOD circuit module design stage S30: the SA 200 parameter and the SB 201 parameter are subjected to circuit simulation analysis.

The second embodiment of the present invention is a method for designing and manufacturing an OSE circuit module. Please refer to FIG. 1 and FIG. 3. FIG. 1 is a schematic diagram of a known multi-gate MOSFET mask layout. FIG. 3 is a schematic diagram of an OSE (OD Space Effect) mask layout designed using a multi-gate MOSFET in the present invention. The present invention provides a novel circuit layout effect component manufacturing method for OSE circuit module design. Please refer to FIG. 7. FIG. 7 is a schematic diagram of the steps of the novel circuit layout effect component manufacturing method of the present invention. The steps are as follows: (1) An integrated circuit formation stage S10, comprising: an active region (OD) mask 101, formed on a substrate 001, a rectangular active region mask area is formed by the mask; a plurality of dummy active regions (Dummy A plurality of dummy active region (Dummy OD) masks 301 are formed on a substrate 001, wherein the plurality of dummy active region (Dummy OD) masks 301 are respectively spaced apart on both sides of the active region (OD) mask 101 in a first direction and on both sides of a second direction orthogonal to the first direction, and the active region (OD) mask 101 and the plurality of dummy active region (Dummy OD) masks 301 are respectively separated by non-masks; a multi-gate transistor is formed on the active region (OD) mask 101 by a transistor mask, comprising: a gate (Poly) mask 100, a plurality of dummy gate (Dummy Poly) masks 104 and a plurality of source and drain contact holes (Source A gate contact mask 103 is formed on the gate (Poly) mask 100; and a plurality of dummy gate (Dummy Poly) masks 104 are respectively parallel to a first direction of the substrate 001 and have a spacing along a second direction orthogonal to the first direction. The plurality of source and drain contact holes (Source Contact) masks 102 are respectively disposed on the left and right sides of the gate (Poly) mask 100 and the plurality of dummy gate (Dummy Poly) masks 104. A gate contact hole (Gate Contact) mask 103 is formed on the gate (Poly) mask 100; and a plurality of dummy gate transistors are formed in the dummy active region (Dummy Poly) by a transistor mask. OD) mask 301, having a plurality of dummy gate anode masks 300 respectively parallel to a first direction of the substrate 001 and having a spacing along a second direction orthogonal to the first direction; (2) an OSE parameter definition stage S20, comprising: an OSE_X1 302 parameter, an OSE_X2 303 parameter, an OSE_Y1 304 parameter and an OSE_Y2 305 parameter, wherein the OSE_X1 302 parameter is the distance from the left side of the active area (OD) mask 101 to the left side of the plurality of dummy active areas (Dummy OD) masks 301, and the OSE_X2 303 parameter is the distance from the right side of the active area (OD) mask 101 to the right side of the plurality of dummy active areas (Dummy OD) mask 301, the OSE_Y1 304 parameter is the distance from the upper edge of the active area (OD) mask 101 to the multiple dummy active area (Dummy OD) masks 301 above, and the OSE_Y2 305 parameter is the distance from the lower edge of the active area (OD) mask 101 to the multiple dummy active area (Dummy OD) masks 301 below; and, (3) an OSE circuit module design stage S30: the OSE_X1 302 parameter, the OSE_X2 303 parameter, the OSE_Y1 304 parameter and the OSE_Y2 305 parameter are subjected to circuit simulation analysis.

The third embodiment of the present invention is a method for designing and manufacturing a PSE circuit module. Please refer to FIG1, which is a schematic diagram of a known multi-gate MOSFET mask layout. The present invention provides a method for manufacturing a component with a novel circuit layout effect for designing a PSE circuit module. Please refer to FIG7, which is a schematic diagram of the steps of the method for manufacturing a component with a novel circuit layout effect of the present invention. The steps are as follows: (1) An integrated circuit formation stage S10 includes: an active region (OD) mask 101 formed on a substrate 001, and a rectangular active region mask area is formed by the mask; and a multi-gate transistor is formed on the active region (OD) mask 101 by a transistor mask, including: a gate (Poly) mask 100, a plurality of dummy gate (Dummy Poly) masks 104 and a plurality of source and drain contact holes (Source Contact) masks 102, wherein the gate (Poly) mask 100 and the plurality of dummy gate (Dummy Poly) masks 104 are respectively parallel to a first direction of the substrate 001 and have a spacing along a second direction orthogonal to the first direction, and the plurality of source and drain contact holes (Source Contact) masks 102 are parallel to the ... A gate contact mask 102 is placed on the left and right sides of the gate (Poly) mask 100 and the plurality of dummy gate (Dummy Poly) masks 104, respectively, and a gate contact hole (Gate Contact) mask 103 is formed on the gate (Poly) mask 100; (2) A PSE parameter definition stage S20, please refer to FIG. 4, FIG. 4 is a schematic diagram of the PSE (Poly Space Effect) mask layout of the multi-gate MOSFET design of the present invention; the PSE parameter definition stage includes: a PS1 400 parameter and a PS2 401 parameter, wherein the PS1 The PS1 400 parameter is the distance from the left side of the gate (Poly) mask 100 to the first dummy gate on the left side, and the PS2 401 parameter is the distance from the right side of the gate (Poly) mask 100 to the first dummy gate on the right side; and, (3) A PSE circuit module design stage S30: Perform circuit simulation analysis on the PS1 400 parameter and the PS2 401 parameter.

The fourth embodiment of the present invention is a method for designing and manufacturing a WPE circuit module. Please refer to Figures 1 and 5. Figure 1 is a schematic diagram of a known multi-gate MOSFET mask layout. Figure 5 is a schematic diagram of a WPE (Well Proximity Effect) mask layout designed using a multi-gate MOSFET in the present invention. The present invention provides a method for manufacturing a component with a novel circuit layout effect for designing a WPE circuit module. Please refer to Figure 7. Figure 7 is a schematic diagram of the steps of the method for manufacturing a component with a novel circuit layout effect in the present invention. The steps are as follows: (1) An integrated circuit formation stage S10 includes: an active region (OD) mask 101, formed on a substrate 001, and a rectangular active region mask area is formed by the mask; a multi-gate transistor is formed on the active region (OD) mask 101 by a transistor mask, including: a gate (Poly) mask 100, a plurality of dummy gate (Dummy Poly) masks 104 and a plurality of source and drain contact holes (Source Contact) masks 102, wherein the gate (Poly) mask 100 and the plurality of dummy gate (Dummy Poly) masks 104 are respectively parallel to a first direction of the substrate 001 and have a spacing along a second direction orthogonal to the first direction, and the plurality of source and drain contact holes (Source Contact) masks 102 are respectively parallel to the ... A gate contact mask 102 is placed on the left and right sides of the gate (Poly) mask 100 and the plurality of dummy gate (Dummy Poly) masks 104, a gate contact hole (Gate Contact) mask 103 is formed on the gate (Poly) mask 100; and a transistor well (Well) mask 500 is formed on a substrate 001, formed by a mask and larger than and surrounding the rectangular active area mask area; (2) A WPE parameter definition stage S20, including: a WPE_X1 501 parameter, a WPE_X2 502 parameter, a WPE_Y1 503 parameter and a WPE_Y2 504 parameter, wherein the WPE_X1 The parameter 501 is the distance from the left side of the active region (OD) mask 101 to the left transistor well (Well) mask 500, the parameter WPE_X2 502 is the distance from the right side of the active region (OD) mask 101 to the right transistor well (Well) mask 500, the parameter WPE_Y1 503 is the distance from the upper edge of the active region (OD) mask 101 to the upper transistor well (Well) mask 500, the parameter WPE_Y2 504 is the distance from the lower edge of the active region (OD) mask 101 to the lower transistor well (Well) mask 500, the transistor well (Well) mask 500 is a photoresist pattern defined by a mask, the purpose of which is to open the well region for ion implantation (well implant); and, (3) A WPE circuit module design stage S30: the WPE_X1 501 parameters, the WPE_X2 502 parameters, the WPE_Y1 503 parameters and the WPE_Y2 504 parameters are subjected to circuit simulation analysis.

Please refer to FIG. 6 , which is a side view of the polysilicon gate MOSFET substrate of the present invention. In the first to fourth embodiments of the present invention, the substrate 001 may be (1) a silicon-coated insulating substrate; (2) glass, quartz, diamond, plastic or other single-layer insulating substrate; (3) silicon, germanium or III-V wafer substrate; (4) germanium-coated insulating or III-V-coated insulating substrate.

Furthermore, in the first to fourth embodiments of the present invention, the substrate 001 further includes a base 600 and a buried oxide layer 601, the buried oxide layer 601 is formed on the base 600, the buried oxide layer 601 is formed on the base 600, and an active region is formed between the buried oxide layer 601 and the base 600; specifically, the buried oxide layer 601 is an internal barrier layer, and the material of the buried oxide layer 601 is selected from silicon dioxide, silicon nitride, oxygen-nitrogen-oxygen (ONO), air cavity (Air Gap), metal silicides with different doping concentrations and metals; the substrate 600 is selected from a group consisting of a single layer and a multi-layer consisting of Group IV or Group III-V semiconductor materials.

Specifically, in the first to fourth embodiments described in the present invention, a gate 603 is formed by the gate (Poly) mask 100, and the gate 603 has a metal silicide layer and a polysilicon layer, and the metal silicide layer is on the polysilicon layer. The gate 603 can also be a single layer or multiple layers of metal; the substrate 001 further includes a buried gate oxide layer 602, and the buried gate oxide layer 602 is between the gate 603 and the substrate 600.

Furthermore, in the first to fourth embodiments described in the present invention, the number of the plurality of dummy gate (Dummy Poly) masks 104 can be 1 to 32, and the width of the active region (OD) mask 101 increases as the number of the plurality of dummy gate (Dummy Poly) masks 104 increases; and the position of the gate contact hole (Gate Contact) mask 103 can be independently connected to any gate (Poly); the buried oxide layer 601 of the polysilicon gate MOSFET forms an active region with the substrate 600, and the width of the active region increases as the number of gates 603 increases.

In summary, the present invention uses a multi-finger device as the basis to design a systematic LDE pattern, including LOD, OSE, WPE, and PSE, to provide a complete check for non-correlated SA/SB changes, in order to significantly improve the accuracy of device modeling.

The embodiments disclosed above are only for illustrative purposes to illustrate the principles, features and effects of the present invention, and are not intended to limit the scope of the present invention. Any person skilled in the art or familiar with the art may modify and alter the above embodiments without departing from the spirit and scope of the present invention. Any equivalent changes and modifications made using the contents disclosed in the present invention shall still be included in the scope of the patent application described below.

001     Substrate 100     Gate (Poly) mask 101     Active region (OD) mask 102     Source and drain contact holes (Source Contact) mask 103     Gate contact holes (Gate Contact) mask 104     Dummy gate (Dummy Poly) mask 200     SA 201     SB 300     Dummy gate mask 301     Dummy active region (Dummy OD) mask 302     OSE_X1 303     OSE_X2 304     OSE_Y1 305     OSE_Y2 400     PS1 401     PS2 500     Transistor well (Well) mask 501    WPE_X1 502     WPE_X2 503     WPE_Y1 504     WPE_Y2 600     Substrate 601     Buried oxide layer 602     Buried gate oxide layer 603     Gate S10     Integrated circuit formation stage S20     Parameter definition stage (LOD/OSE/PSE/WPE) S30     Circuit module design stage (LOD/OSE/PSE/WPE)

FIG1 is a schematic diagram of a known multi-gate MOSFET mask layout FIG2 is a schematic diagram of a LOD (Length Of Diffusion) mask layout designed using a multi-gate MOSFET in the present invention FIG3 is a schematic diagram of an OSE (OD Space Effect) mask layout designed using a multi-gate MOSFET in the present invention FIG4 is a schematic diagram of a PSE (Poly Space Effect) mask layout designed using a multi-gate MOSFET in the present invention FIG5 is a schematic diagram of a WPE (Well Proximity Effect) mask layout designed using a multi-gate MOSFET in the present invention FIG6 is a side view of a polysilicon gate MOSFET substrate in the present invention FIG7 is a schematic diagram of the steps of a component manufacturing method for the novel circuit layout effect in the present invention

001 Substrate 100 Gate (Poly) mask 101 Active area (OD) mask 102 Source and drain contact holes (Source Contact) mask 103 Gate contact holes (Gate Contact) mask 104 Dummy gate (Dummy Poly) mask

Claims (9)

A novel circuit layout effect device manufacturing method, the steps are as follows: an integrated circuit formation stage, including: an active region (OD) mask, formed on a substrate, the mask forms a rectangular active region mask area; and a multi-gate transistor, formed on the active region (OD) mask by the transistor mask, including: a gate (Poly) mask, a plurality of dummy gate (Dummy Poly) masks and a plurality of source and drain contact holes (Source Contact) masks, wherein the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks are parallel to a first direction of the substrate and have a spacing along a second direction orthogonal to the first direction, and the plurality of source and drain contact holes (Source Contact) are respectively parallel to the ... The gate contact mask is formed on the gate (Poly) mask, wherein the number of the plurality of dummy gate (Dummy Poly) masks can be 1 to 32, and the width of the active region (OD) mask increases with the increase in the number of the plurality of dummy gate (Dummy Poly) masks. The contact mask position can be independently connected to any gate (Poly) mask; a LOD parameter definition stage, including: an SA parameter and an SB parameter, wherein the SA parameter is the distance from the left edge of the gate (Poly) mask to the left edge of the active region (OD) mask, and the SB parameter is the distance from the right edge of the gate (Poly) mask to the right edge of the active region (OD) mask; and, a LOD circuit module design stage: the SA parameter and the SB parameter are subjected to circuit simulation analysis. A novel circuit layout effect device manufacturing method, the steps are as follows: An integrated circuit formation stage, including: an active area (OD) mask, formed on a substrate, a rectangular active area mask area is formed by the mask; a plurality of dummy active area (Dummy OD) masks, formed on a substrate, a plurality of rectangular areas are formed by the masks, wherein the plurality of dummy active area (Dummy OD) masks are respectively spaced on both sides of the first direction of the active area (OD) mask and on both sides of the second direction orthogonal to the first direction, and the active area (OD) mask and the plurality of dummy active areas (Dummy OD) masks are spaced on both sides of the first direction of the active area (OD) mask. The active region (OD) mask is separated by a non-mask; a multi-gate transistor is formed by a transistor mask on the active region (OD) mask, comprising: a gate (Poly) mask, a plurality of dummy gate (Dummy Poly) masks and a plurality of source and drain contact holes (Source Contact) masks, wherein the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks are respectively parallel to a first direction of the substrate and have a spacing along a second direction orthogonal to the first direction, the plurality of source and drain contact holes (Source Contact) masks are respectively placed on the left and right sides of the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks, a gate contact hole (Gate Contact) mask is provided on the left and right sides of the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks, and a gate contact hole (Gate Contact) mask is provided on the right and left sides of the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks. A gate contact mask is formed on the gate (Poly) mask, wherein the number of the plurality of dummy gate (Dummy Poly) masks can be 1 to 32, the width of the active region (OD) mask increases with the increase in the number of the plurality of dummy gate (Dummy Poly) masks, and the gate contact hole (Gate Contact) mask position can be independently connected to any gate (Poly) mask; and a plurality of dummy gate transistors are formed on the dummy active region (Dummy) by the transistor mask. An OD mask having a plurality of dummy gates parallel to a first direction of the substrate and having a spacing along a second direction orthogonal to the first direction; an OSE parameter definition stage, comprising: an OSE_X1 parameter, an OSE_X2 parameter, an OSE_Y1 parameter and an OSE_Y2 parameter, wherein the OSE_X1 parameter is the distance from the left side of the active region (OD) mask to the plurality of dummy active region (Dummy OD) masks on the left side, the OSE_X2 parameter is the distance from the right side of the active region (OD) mask to the plurality of dummy active region (Dummy OD) masks on the right side, and the OSE_Y1 parameter is the distance from the upper edge of the active region (OD) mask to the plurality of dummy active regions (Dummy OD) masks on the upper side. OD) mask, the OSE_Y2 parameter is the distance from the lower edge of the active area (OD) mask to the multiple dummy active area (Dummy OD) masks below; and, an OSE circuit module design stage: the OSE_X1 parameter, the OSE_X2 parameter, the OSE_Y1 parameter and the OSE_Y2 parameter are subjected to circuit simulation analysis. A novel circuit layout effect device manufacturing method, the steps are as follows: an integrated circuit formation stage, including: an active region (OD) mask, formed on a substrate, the mask forms a rectangular active region mask area; and a multi-gate transistor, formed on the active region (OD) mask by the transistor mask, including: a gate (Poly) mask, a plurality of dummy gate (Dummy Poly) masks and a plurality of source and drain contact holes (Source Contact) masks, wherein the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks are parallel to a first direction of the substrate and have a spacing along a second direction orthogonal to the first direction, and the plurality of source and drain contact holes (Source Contact) are respectively parallel to the ... The gate contact mask is formed on the gate (Poly) mask, wherein the number of the plurality of dummy gate (Dummy Poly) masks can be 1 to 32, and the width of the active area (OD) mask increases with the increase in the number of the plurality of dummy gate (Dummy Poly) masks. The contact mask position can be independently connected to any gate (Poly) mask; a PSE parameter definition stage, including: a PS1 parameter and a PS2 parameter, wherein the PS1 parameter is the distance from the left side of the gate (Poly) mask to the first dummy gate on the left side, and the PS2 parameter is the distance from the right side of the gate (Poly) mask to the first dummy gate on the right side; and a PSE circuit module design stage: the PS1 parameter and the PS2 parameter are subjected to circuit simulation analysis. A novel circuit layout effect device manufacturing method, the steps are as follows: an integrated circuit formation stage, including: an active region (OD) mask, formed on a substrate, the mask forms a rectangular active region mask area; a multi-gate transistor, formed on the active region (OD) mask by the transistor mask, including: a gate (Poly) mask, a plurality of dummy gate (Dummy Poly) masks and a plurality of source and drain contact holes (Source Contact) masks, wherein the gate (Poly) mask and the plurality of dummy gate (Dummy Poly) masks are parallel to a first direction of the substrate and have a spacing along a second direction orthogonal to the first direction, and the plurality of source and drain contact holes (Source Contact) are arranged in parallel. The gate contact mask is formed on the gate (Poly) mask, wherein the number of the plurality of dummy gate (Dummy Poly) masks can be 1 to 32, and the width of the active region (OD) mask increases with the increase in the number of the plurality of dummy gate (Dummy Poly) masks. The contact) mask position can be independently connected to any gate (Poly) mask; and, a transistor well (Well) mask, formed on a substrate, formed by a mask and larger than and surrounding the rectangular active area mask area; a WPE parameter definition stage, including: a WPE_X1 parameter, a WPE_X2 parameter, a WPE_Y1 parameter and a WPE_Y2 parameter, wherein the WPE_X1 parameter is the distance from the left side of the active area (OD) mask to the left transistor well (Well) mask, and the WPE_ The X2 parameter is the distance from the right side of the active area (OD) mask to the right transistor well (Well) mask, the WPE_Y1 parameter is the distance from the upper edge of the active area (OD) mask to the upper transistor well (Well) mask, and the WPE_Y2 parameter is the distance from the lower edge of the active area (OD) mask to the lower transistor well (Well) mask; and, a WPE circuit module design stage: the WPE_X1 parameter, the WPE_X2 parameter, the WPE_Y1 parameter and the WPE_Y2 parameter are subjected to circuit simulation analysis. A method for manufacturing a device with a novel circuit layout effect as described in claims 1 to 4, wherein the substrate is glass, quartz, diamond, plastic, silicon, germanium, III-V wafer substrate, silicon-coated insulating substrate, germanium-coated insulating substrate or III-V-coated insulating substrate or other single-layer insulating substrate. A method for manufacturing a device with a novel circuit layout effect as described in claims 1 to 4, wherein the substrate further comprises a base and a buried oxide layer, the buried oxide layer is formed on the base, and an active region is formed between the buried oxide layer and the base. A method for manufacturing a device with a novel circuit layout effect as described in claims 1 to 4, wherein the material of the buried oxide layer is selected from a group consisting of silicon dioxide, silicon nitride, oxynitride (ONO), air gap, metal silicides with different doping concentrations, and metals; and the substrate is selected from a group consisting of a single layer and multiple layers of Group IV or Group III-V semiconductor materials. A method for manufacturing a device with a novel circuit layout effect as described in claims 1 to 4, wherein a gate formed by the gate (Poly) mask can be a single-layer or multi-layer metal. A method for manufacturing a device with a novel circuit layout effect as described in claims 1 to 4, wherein the gate is formed by a gate (Poly) mask, and the gate includes: a metal silicide layer and a polysilicon layer, and the metal silicide layer is formed on the polysilicon layer.

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