TWI803381B - Method of manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device includes: depositing a spacer layer on a semiconductor structure, in which the semiconductor structure includes a first dielectric layer, a first conductive layer in the first dielectric layer, a second dielectric layer on the first dielectric layer, a second conductive layer in the second dielectric layer, and a third conductive layer on the second conductive layer and elevated relative to the second dielectric layer, in which the second conductive layer is in contact with the first conductive layer, and a void is included between the second conductive layer and the second dielectric layer; depositing an oxide layer on the spacer layer; depositing a nitride layer on the oxide layer and filling the void; and removing a portion of the nitride layer such that resting portion of the nitride layer only fills the void.

Description

Manufacturing method of semiconductor element

The present disclosure relates to a method for manufacturing a semiconductor device.

In the middle stage of manufacturing semiconductor components, when the wire is connected to the bottom contact (for example: via column, interconnection structure), the width of the wire will be defined by the width of the bottom contact. In order to form a wire with a width that meets the requirements, some The bottom contacts are removed to form voids, and then a dielectric material is filled into the voids to prevent the voids from affecting the electrical properties of the entire semiconductor device.

However, in the current process of filling the pores of the contacts, the problem of excessively filling the pores with dielectric materials or insufficiently filling the pores with dielectric materials often occurs, which will further lead to unsatisfactory electrical properties of semiconductor devices, and may even A leakage problem has occurred.

Therefore, how to propose a method for manufacturing a semiconductor element, especially a method for manufacturing a semiconductor element suitable for filling contact pores, is one of the problems that the industry is eager to devote research and development resources to solve.

In view of this, one purpose of the present disclosure is to propose a method for manufacturing a semiconductor device that can solve the above-mentioned problems.

In order to achieve the above object, according to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: depositing a spacer layer on a semiconductor structure, wherein the semiconductor structure includes a first dielectric layer, a layer located in the first dielectric layer The first conductive layer, the second dielectric layer located on the first dielectric layer, the second conductive layer located in the second dielectric layer, and the second conductive layer located on the second dielectric layer and raised relative to the second dielectric layer High third conductive layer, wherein the second conductive layer is in contact with the first conductive layer, and there is a gap between the second conductive layer and the second dielectric layer; depositing an oxide layer on the spacer layer; depositing a nitride layer on the oxide layer and filling the pores; and removing portions of the nitride layer such that the remaining portions of the nitride layer only fill the pores.

In one or more embodiments of the present disclosure, the step of depositing the spacer layer on the semiconductor structure utilizes a blanket deposition process.

In one or more embodiments of the present disclosure, the step of depositing an oxide layer on the spacer layer utilizes a blanket deposition process.

In one or more embodiments of the present disclosure, in the step of depositing an oxide layer on the spacer layer, the thickness of the oxide layer is less than 2 nm.

In one or more embodiments of the present disclosure, the step of depositing an oxide layer on the spacer layer is performed by plasma treatment using a process gas mixed with oxygen, hydrogen, and nitrogen.

In one or more embodiments of the present disclosure, the step of depositing the nitride layer on the oxide layer and filling the pores utilizes a blanket deposition process.

In one or more embodiments of the present disclosure, in the step of depositing a nitride layer on the oxide layer and filling the pores, the material of the nitride layer is the same as that of the second dielectric layer.

In one or more embodiments of the present disclosure, the step of removing portions of the nitride layer such that the remaining portion of the nitride layer only fills the voids utilizes an etching process.

In one or more embodiments of the present disclosure, after performing the step of removing portions of the nitride layer such that the remainder of the nitride layer only fills voids, the top surface of the remainder of the nitride layer is in contact with the second dielectric layer. The top surface of the oxide layer above the layer is flush.

In one or more embodiments of the present disclosure, the step of removing portions of the nitride layer so that the remaining portion of the nitride layer only fills pores is to remove the oxide using phosphoric acid having high etch selectivity to the nitride layer and the oxide layer layer parts.

To sum up, in the method for manufacturing a semiconductor device of the present disclosure, by forming an oxide layer on the spacer layer formed on the upper surface of the semiconductor structure, the oxide layer can be used as an etch stop layer for the spacer Layers form protection. In addition, in the manufacturing method of the semiconductor device of the present disclosure, by using hot phosphoric acid etching when removing the nitride layer located on the oxide layer, since phosphoric acid has high etching selectivity for oxide and nitride , so that the spacer layer can be further etched without etching the oxide layer in the step of removing the portion of the nitride layer. In the manufacturing method of the semiconductor device of the present disclosure, since the thickness of the oxide layer is less than 2 nm, the finally formed semiconductor device has low resistance. In the manufacturing method of the peninsula bulk device of the present disclosure, since the nitride layer is deposited first to overfill the pores and then the etch-back process is performed, the problem that the pores are overfilled or underfilled by the nitride layer can be more effectively avoided. By implementing the method for manufacturing a semiconductor device of the present disclosure, a semiconductor device with better quality and low impedance can be manufactured.

The above description is only used to explain the problems to be solved by the present disclosure, the technical means to solve the problems, and the effects thereof, etc. The specific details of the present disclosure will be introduced in detail in the following implementation methods and related drawings.

The following will disclose multiple implementations of the present disclosure with diagrams, and for the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. That is to say, in some implementations of the present disclosure, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings. The same reference numbers will be used throughout the drawings to refer to the same or similar elements.

Spatially relative terms (eg, relative terms such as "below", "beneath", "beneath", "above", "above", etc.) are used herein to describe simply how an element or feature shown in the figures differs from another A relationship between components or features. These spatially relative terms encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, these devices may be rotatable (by 90 degrees or otherwise) and the spatially relative descriptors used herein may be construed accordingly. Additionally, the term "consisting of" can mean "comprising" or "consisting of".

Please refer to FIG. 1 , which is a flowchart of a manufacturing method M of a semiconductor device 200 according to an embodiment of the present disclosure. As shown in FIG. 1 , the manufacturing method M of the semiconductor element 200 includes step S101 , step S102 , step S103 and step S104 . Please refer to FIG. 2 to FIG. 5 when describing step S101 , step S102 , step S103 and step S104 in FIG. 1 in detail.

Before describing the manufacturing method M of the semiconductor device 200 in detail, please refer to FIG. 2 . FIG. 2 provides a semiconductor structure 100 . In this embodiment, the semiconductor structure 100 includes a first dielectric layer 110 , a first conductive layer 110A, a second dielectric layer 120 , a second conductive layer 120A and a third conductive layer 130 . The first conductive layer 110A is located in the first dielectric layer 110 . The second dielectric layer 120 is located on the first dielectric layer 110 . The second conductive layer 120A is located in the second dielectric layer 120 . The third conductive layer 130 is located on the second conductive layer 120A, and the third conductive layer 130 is elevated relative to the second dielectric layer 120 . As shown in FIG. 2 , the second conductive layer 120A is in contact with the first conductive layer 110A, and the second conductive layer 120A is in contact with the third conductive layer 130 . In this embodiment, as shown in FIG. 2 , the width of the second conductive layer 120A in the horizontal direction is smaller than the width of the first conductive layer 110A in the horizontal direction, so that the second conductive layer 120A and the second dielectric The layers 120 have voids V between them.

In this embodiment, as shown in FIG. 2 , the upper surface of the first conductive layer 110A is flush with the upper surface of the first dielectric layer 110 .

In this embodiment, as shown in FIG. 2 , the upper surface of the second conductive layer 120A is flush with the upper surface of the second dielectric layer 120 .

In this embodiment, as shown in FIG. 2 , the upper surface of the third conductive layer 130 is higher than the upper surface of the second dielectric layer 120 .

In this embodiment, as shown in FIG. 2 , the width of the third conductive layer 130 in the horizontal direction is equal to the width of the second conductive layer 120A in the horizontal direction.

In some embodiments, the semiconductor structure 100 may be, for example, a semiconductor structure for forming a dynamic random access memory (DRAM), but the present disclosure is not limited thereto. In some embodiments, the semiconductor structure 100 may be any semiconductor stack structure including one or more conductive materials, one or more dielectric materials, or a combination thereof.

In some embodiments, the material of the first dielectric layer 110 may be oxide, nitride or any other suitable material. The present disclosure is not intended to limit the material of the first dielectric layer 110 .

In some embodiments, the first dielectric layer 110 can be formed by any suitable method, such as CVD (Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), ECP (Electrochemical Plating), Electroless Plating, etc. The present disclosure is not intended to limit the method of forming the first dielectric layer 110 .

In some embodiments, the material of the first conductive layer 110A may be polysilicon (poly-silicon) or any other suitable material. The present disclosure is not intended to limit the material of the first conductive layer 110A.

In some embodiments, the first conductive layer 110A can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD ( Atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, etc. The present disclosure is not intended to limit the method of forming the first conductive layer 110A.

In some embodiments, the material of the second dielectric layer 120 may be oxide, nitride or any other suitable material. The present disclosure is not intended to limit the material of the second dielectric layer 120 .

In some embodiments, the second dielectric layer 120 can be formed by any suitable method, such as CVD (Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), ECP (Electrochemical Plating), Electroless Plating, etc. The present disclosure is not intended to limit the method of forming the second dielectric layer 120 .

In some embodiments, the dielectric constant of the second dielectric layer 120 is different from that of the first dielectric layer 110 .

In some embodiments, the material of the second conductive layer 120A may be tungsten, titanium nitride (TiN), tungsten nitride (WN) or any other suitable material. The present disclosure is not intended to limit the material of the second conductive layer 120A.

In some embodiments, the second conductive layer 120A can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD ( Atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, etc. The disclosure is not intended to limit the method of forming the second conductive layer 120A.

In some embodiments, the material of the third conductive layer 130 may be oxide, low-k material or any other suitable material. The present disclosure is not intended to limit the material of the third conductive layer 130 .

In some embodiments, the third conductive layer 130 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD ( Atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, etc. The present disclosure is not intended to limit the method of forming the third conductive layer 130 .

The operations of step S101 , step S102 , step S103 and step S104 are described in detail below.

First, step S101 is performed: depositing a spacer layer 140 on the semiconductor structure 100 .

Please refer to FIG. 2 , the spacer layer 140 is formed on the semiconductor structure 100 . For example, the spacer layer 140 is formed on the semiconductor structure 100 using a deposition process. As shown in FIG. 2 , the spacer layer 140 is formed on the upper surface of the semiconductor structure 100 . More specifically, the spacer layer 140 at least covers the second dielectric layer 120 , a part of the first conductive layer 110A, a part of the second conductive layer 120A and the third conductive layer 130 . In other words, the spacer layer 140 is formed on the inner surface of the hole V at least.

In some embodiments, the spacer layer 140 may be _a material such as silicon nitride ( _SixNy ). The disclosure is not intended to limit the material of the spacer layer 140 .

In some embodiments, the spacer layer 140 can be formed by any suitable method, such as ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Physical Vapor Deposition) phase deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, etc. The present disclosure is not intended to limit the method of forming the spacer layer 140 .

In some embodiments, the spacer layer 140 may be formed using a blanket deposition process, but the present disclosure is not intended to limit the method of forming the spacer layer 140 .

Next, step S102 is performed: depositing an oxide layer 150 on the spacer layer 140 .

Referring to FIG. 3 , the oxide layer 150 is formed on the spacer layer 140 . For example, the oxide layer 150 is formed on the spacer layer 140 using a deposition process. In some embodiments, the oxide layer 150 is substantially conformal with the spacer layer 140 , and the oxide layer 150 is formed on at least the inner surface of the pore V. As shown in FIG.

In some embodiments, the oxide layer 150 completely covers the spacer layer 140 . Since the oxide layer 150 completely covers the spacer layer 140, the oxide layer 150 may serve as an etch stop layer in subsequent operations to protect the spacer layer 140 from being etched.

In some embodiments, the oxide layer 150 may be a material such as silicon dioxide (SiO ₂ ). The present disclosure is not intended to limit the material of the oxide layer 150 .

In some embodiments, the oxide layer 150 may serve as a resist oxide film. In some embodiments, the thickness of the oxide layer 150 is less than about 2 nanometers. However, the present disclosure is not intended to limit the thickness of the oxide layer 150 .

In some embodiments, the oxide layer 150 can be formed by any suitable method, such as PEALD (Plasma Enhanced Atomic Layer Deposition), ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), PECVD (Plasma Enhanced Atomic Layer Deposition), Chemical vapor deposition), PVD (physical vapor deposition), ECP (electrochemical plating), chemical plating, etc. The present disclosure is not intended to limit the method of forming the oxide layer 150 .

In some embodiments, the oxide layer 150 may be formed using a blanket deposition process, but the present disclosure is not intended to limit the method of forming the oxide layer 150 .

In some embodiments, depositing the oxide layer 150 on the spacer layer 140 is performed by plasma processing using a process gas mixed with oxygen (O ₂ ), hydrogen (H ₂ ), and nitrogen (N ₂ ). In some embodiments, oxygen gas, hydrogen gas and nitrogen gas are used as precursors of the chemical reaction for depositing the oxide layer 150 on the spacer layer 140 in step S102 .

Next, step S103 is performed: depositing a nitride layer 160 on the oxide layer 150 to fill the void V.

Referring to FIG. 4 , the nitride layer 160 is formed on the oxide layer 150 . For example, the nitride layer 160 is formed on the oxide layer 150 using a deposition process. As shown in FIG. 4 , the nitride layer 160 completely covers the oxide layer 150 and fills the voids V .

In some embodiments, the nitride layer 160 may be _a material such as silicon nitride ( _SixNy ). The present disclosure is not intended to limit the material of the nitride layer 160 .

In some embodiments, the nitride layer 160 can be formed by any suitable method, such as ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Physical Vapor Deposition) phase deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, etc. The present disclosure is not intended to limit the method of forming the nitride layer 160 .

In some embodiments, the nitride layer 160 can be formed by a blanket deposition process, but the present disclosure is not intended to limit the method of forming the nitride layer 160 .

In some embodiments, the nitride layer 160 overfills the void V, as shown in FIG. 4 .

In some embodiments, the material of the nitride layer 160 is the same as that of the second dielectric layer 120 .

Next, step S104 is performed: removing a portion of the nitride layer 160 so that the remaining portion of the nitride layer 160 only fills the void V.

Referring to FIG. 5, the nitride layer 160 is removed. In more detail, as shown in FIG. 5, only one portion of the nitride layer 160 is actually removed. As shown in FIG. 5 , the remainder of the nitride layer 160 fills the void V, and the nitride layer 160 does not exist on the oxide layer 150 above the second dielectric layer 120 .

In some embodiments, portions of the nitride layer 160 may be removed using an etching process. In some embodiments, the etching process may be, for example, isotropic etching, but the disclosure is not limited thereto.

In some embodiments, the portion of the nitride layer 160 can be removed by an etching process such as wet etching or dry etching. For example, portions of the nitride layer 160 may be removed by wet etching such as hot phosphoric acid.

In embodiments of the present disclosure, it may be advantageous to use hot phosphoric acid (H ₃ PO ₄ ) to etch to remove portions of the nitride layer 160 . Since phosphoric acid has high etching selectivity for oxides and nitrides, specifically, phosphoric acid can etch the nitride layer 160 but hardly etches the oxide layer 150 . Thereby, the portion of the nitride layer 160 can be removed by wet etching such as hot phosphoric acid, so that the remaining portion of the nitride layer 160 only fills the void V. Referring to FIG. However, the present disclosure is not intended to limit the method for removing the portion of the nitride layer 160 .

In some embodiments, as shown in FIG. 5 , the above etching process makes the nitride layer 160 in the void V not removed but remains intact.

In some embodiments, in order to make the nitride layer 160 only exist in the hole V finally, and because the nitride layer 160 in the step S103 is excessively filling the hole V, the etching process in the step S104 is also called back. etch-back process. Therefore, the oxide layer 150 is also called an etch-back stop layer.

Please continue to refer to Figure 5. In some embodiments, after performing step S104, the top surface 160a of the remaining part of the nitride layer 160 is flush with the top surface 150a of the oxide layer 150 above the second dielectric layer 120, so that the nitride layer The remainder of 160 fills void V completely.

By performing the above step S101 , step S102 , step S103 and step S104 , the manufacturer can use the manufacturing method M of the semiconductor device 200 to manufacture the semiconductor device 200 of the present disclosure having the void V completely filled with a dielectric material.

In some embodiments, it is advantageous to form the oxide layer 150 in step S102 using plasma treatment of a process gas mixed with oxygen, hydrogen and nitrogen. In a hot phosphoric acid reaction, the oxide layer 150 formed by plasma treatment using a process gas mixed with oxygen, hydrogen, and nitrogen of the present disclosure is compared to the oxide layer 150 formed by, for example, plasma treatment using a process gas composed of oxygen or The oxide layer 150 formed by atomic layer deposition may have a lower etching loss rate.

In some embodiments, it is advantageous that the thickness of the oxide layer 150 formed in step S102 is less than about 2 nm. Since the thickness of the oxide layer 150 is very thin, the finally formed semiconductor device 200 may have lower resistance.

In some embodiments, it may be advantageous to use a wet etch such as hot phosphoric acid to remove the portion of the nitride layer 160 in step S104 . Since the phosphoric acid hardly etches the oxide layer 150 , phosphoric acid does not penetrate the oxide layer 150 to etch the spacer layer 140 when performing step S104 , thus causing leakage problems.

In some embodiments, it is advantageous to overfill the voids V with the nitride layer 160 and then etch back the portion of the nitride layer 160 so that the nitride layer 160 only fills the voids V in step S103 and step S104 . Compared with directly depositing the nitride layer 160 in the hole V, the present disclosure firstly deposits the nitride layer 160 to overfill the hole V and then performs the etch-back process, which can more effectively prevent the hole V from being overfilled by the nitride layer 160 or The underfill problem.

From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that in the method of manufacturing a semiconductor device of the present disclosure, by forming an oxide layer on the spacer layer formed on the upper surface of the semiconductor structure , so that the oxide layer can serve as an etch stop layer to protect the spacer layer. In addition, in the manufacturing method of the semiconductor device of the present disclosure, by using hot phosphoric acid etching when removing the nitride layer located on the oxide layer, since phosphoric acid has high etching selectivity for oxide and nitride , so that the spacer layer can be further etched without etching the oxide layer in the step of removing the portion of the nitride layer. In the manufacturing method of the semiconductor device of the present disclosure, since the thickness of the oxide layer is less than 2 nm, the finally formed semiconductor device has low resistance. In the manufacturing method of the peninsula bulk device of the present disclosure, since the nitride layer is deposited first to overfill the pores and then the etch-back process is performed, the problem that the pores are overfilled or underfilled by the nitride layer can be more effectively avoided. By implementing the method for manufacturing a semiconductor device of the present disclosure, a semiconductor device with better quality and low impedance can be manufactured.

The above content summarizes the features of several implementations, so that those skilled in the art can better understand the aspects of this case. Those skilled in the art should understand that without departing from the spirit and scope of the present application, the above content can be easily used as a basis for designing or modifying other changes, so as to achieve the same purpose and/or realize the embodiments described herein. Same advantage. The above contents should be understood as examples of the present disclosure, and the scope of protection thereof should be subject to the scope of the patent application.

100: Semiconductor Structures 110: the first dielectric layer 110A: first conductive layer 120: second dielectric layer 120A: second conductive layer 130: the third conductive layer 140: spacer layer 150: oxide layer 150a: top surface 160: Nitride layer 160a: top surface 200: Semiconductor components M: Method S101, S102, S103, S104: steps V: porosity

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more comprehensible, the accompanying drawings are described as follows: FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram illustrating a manufacturing stage of a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram illustrating a manufacturing stage of a semiconductor device manufacturing method according to an embodiment of the present disclosure. FIG. 4 is a schematic diagram illustrating a manufacturing stage of a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. FIG. 5 is a schematic diagram illustrating a manufacturing stage of a manufacturing method of a semiconductor device according to an embodiment of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

M: Method

S101, S102, S103, S104: steps

Claims (10)

A method for manufacturing a semiconductor element, comprising: depositing a spacer layer on a semiconductor structure, wherein the semiconductor structure includes a first dielectric layer, a first conductive layer located in the first dielectric layer, a A second dielectric layer on the first dielectric layer, a second conductive layer located in the second dielectric layer, and a second conductive layer located on the second conductive layer and raised relative to the second dielectric layer a third conductive layer, wherein the second conductive layer is in contact with the first conductive layer, and there is a gap between the second conductive layer and the second dielectric layer; depositing an oxide layer on the spacer layer; depositing a nitride layer on the oxide layer and filling the pores; and Removing a portion of the nitride layer causes the remaining portion of the nitride layer to fill only the void. The method of claim 1, wherein the step of depositing the spacer layer on the semiconductor structure utilizes a blanket deposition process. The method of claim 1, wherein the step of depositing the oxide layer on the spacer layer utilizes a blanket deposition process. The method of claim 1, wherein in the step of depositing the oxide layer on the spacer layer, a thickness of the oxide layer is less than 2 nm. The method of claim 1, wherein the step of depositing the oxide layer on the spacer layer is performed by a plasma treatment using a process gas mixed with oxygen, hydrogen and nitrogen. The method of claim 1, wherein the step of depositing the nitride layer on the oxide layer and filling the pores utilizes a blanket deposition process. The method according to claim 1, wherein in the step of depositing the nitride layer on the oxide layer and filling the pores, the material of the nitride layer is the same as that of the second dielectric layer. The method of claim 1, wherein the step of removing the portion of the nitride layer such that the remaining portion of the nitride layer only fills the void is using an etching process. The method as claimed in claim 1, wherein after performing the step of removing the portion of the nitride layer so that the remaining portion of the nitride layer only fills the void, a top surface of the remaining portion of the nitride layer is located at the top surface of the nitride layer A top surface of the oxide layer above the second dielectric layer is flush. The method as claimed in claim 1, wherein the step of removing the portion of the nitride layer such that the remaining portion of the nitride layer only fills the void utilizes high etch selectivity to the nitride layer and the oxide layer A phosphoric acid removes the portion of the oxide layer.

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