TWI802590B - Inductor and its manufacturing method - Google Patents

Abstract

The inductor of the present invention includes: a wiring having a width W; and a first electrode and a second electrode continuous with each of both ends of the wiring. The wiring, the first electrode, and the second electrode are located on the same plane. The planar area S1 of the first electrode and the planar area S2 of the second electrode are each equal to or greater than the square value of the width W (W ² ). The area where wiring is arranged is located between the first electrode and the second electrode. The region has: a length X in the longitudinal direction equal to the length L between the first electrode and the second electrode along the opposing direction of the first electrode and the second electrode, and a short length X in a direction perpendicular to the longitudinal direction. Length Y in the side direction. The length X in the long side direction is at least 1.5 times the length Y in the short side direction.

Description

Inductor and its manufacturing method

The present invention relates to an inductor and its manufacturing method.

It is known that an inductor is mounted on an electronic device or the like and used as a passive element such as a voltage converting member.

For example, a multilayer chip inductor is proposed, which is provided with internal electrodes formed in a meandering shape on each of the multilayer substrates overlapping in the thickness direction. An upper external electrode is formed at one end of the internal electrode, and a lower external electrode is formed at the other end of the lowermost internal electrode (for example, refer to Patent Document 1).

prior art literature patent documents

Patent Document 1: Japanese Patent Laid-Open No. 7-86039

In recent years, the miniaturization of electronic equipment is being promoted, and therefore, the miniaturization of the inductors mounted thereon is also required. However, since the multilayer chip inductor described in Patent Document 1 includes a multilayer substrate, there is a disadvantage that it cannot satisfy the above-mentioned requirements.

On the other hand, low resistance of inductors is also required, but the multilayer chip inductor described in Patent Document 1 has a disadvantage that it cannot satisfy the above-mentioned requirements.

The present invention provides an inductor which realizes miniaturization and low resistance and a manufacturing method thereof.

The present invention (1) includes an inductor comprising: a wiring having a width W; and a first electrode and a second electrode continuous with each of both ends of the wiring; and the wiring, the first electrode and the second electrode are located on the same plane, the planar area S1 of the first electrode and the planar area S2 of the second electrode are each equal to or greater than the square value of the width W (W ² ), and the region where the wiring is arranged is located in the first electrode. Between the first electrode and the second electrode, the region has a length X in the longitudinal direction equal to the length L between the first electrode and the second electrode along the opposing direction of the first electrode and the second electrode. , and the short-side length Y in a direction perpendicular to the above-mentioned long-side direction, wherein the above-mentioned long-side length X is 1.5 times or more of the above-mentioned short-side length Y.

In this inductor, since the wiring, the first electrode, and the second electrode are located on the same plane, miniaturization in the thickness direction can be achieved. Furthermore, since the length X of the region in the longitudinal direction is at least 1.5 times the length Y in the shorter direction, further miniaturization of the region in the shorter direction can be achieved.

As a result, miniaturization of the inductor can be realized.

In addition, in this inductor, since the planar area S1 of the first electrode and the planar area S2 of the second electrode are each equal to or greater than the square value (W ² ) of the width W of the wiring, the resistance of the inductor can be reduced.

As a result, this inductor achieves both miniaturization and low resistance.

The present invention (2) includes the inductor according to claim 1, further comprising a magnetic layer covering one side in the thickness direction of the wiring.

Since this inductor further includes a magnetic layer covering one side in the thickness direction of the wiring, high inductance can be ensured.

The present invention (3) includes the inductor according to (2), wherein the above-mentioned magnetic layer has a thickness of 500 μm or less.

In this inductor, the thickness of the magnetic layer is 500 μm or less. Therefore, high inductance of the inductor can be ensured, and miniaturization of the inductor can be achieved.

The present invention (4) includes the inductor according to (2) or (3), which further includes: a first bump arranged on one side in the thickness direction of the first electrode; and a second bump arranged on the first electrode above. 2 One side of the electrode in the thickness direction.

Since the inductor includes the first bump and the second bump, electrical connection between the electronic device on which the inductor is mounted and the first electrode and the second electrode can be easily realized.

The present invention (5) includes the inductor as in (4), wherein the ratio of the planar area BS1 of the first bump to the planar area S1 of the first electrode is 70% or more, and the planar area BS2 of the second bump is The ratio to the planar area S2 of the second electrode is 70% or more.

In this inductor, since the ratio of the plane area of the first bump to the plane area of the first electrode is 70% or more, and the ratio of the plane area of the second bump to the plane area of the second electrode is 70% or more Therefore, the low resistance of the inductor can be realized, and the reduction in the reliability of the electrical connection between the electronic device and the first electrode and the reduction in the reliability of the electrical connection between the electronic device and the second electrode can be suppressed.

The present invention (6) includes the inductor according to (4) or (5), wherein the length in the thickness direction of the first bump and the second bump is longer than the thickness of the magnetic layer.

In this inductor, since the length in the thickness direction of the first bump and the second bump is longer than the thickness of the magnetic layer, it is possible to make the electrical connection between the electronic device and the first electrode and the second electrode Improved connection reliability.

The present invention (7) includes the inductor according to any one of (4) to (6), wherein the first bump and the second bump are separated from the magnetic layer by an interval of 0.1 μm or more in the plane direction. configuration.

In this inductor, since the first bump and the second bump and the magnetic layer are arranged at a distance of 0.1 μm or more in the plane direction, it is possible to effectively prevent the first bump and the second bump from contacting the magnetic layer. short circuit. Therefore, the electrical connection reliability between the electronic device and the first electrode and the second electrode can be improved.

The present invention (8) includes the inductor according to any one of (4) to (7), which further includes an insulating cover layer covering the surroundings of the first bump and the second bump, and is arranged On one side in the thickness direction of the wiring, the first electrode, and the second electrode.

Since the inductor is provided with a cover insulating layer, the first electrode, the second electrode, and the wiring can be covered (protected) by the cover insulating layer, so that the electrical connection reliability can be improved.

The present invention (9) includes the inductor according to any one of (1) to (8), further comprising: an insulating base layer disposed on the other side of the wiring in the thickness direction; and a second magnetic layer disposed on on the other side in the thickness direction of the insulating base layer.

Since this inductor further includes a second magnetic layer, high inductance can be secured.

The present invention (10) includes a manufacturing method of an inductor, which is a manufacturing method for manufacturing an inductor according to any one of (2) to 9, and has the following steps: making a plurality of A unit including one of the above-mentioned wiring, one of the above-mentioned first electrode, and one of the above-mentioned second electrode; in the manner of collectively covering one side of the thickness direction of the above-mentioned plurality of wiring in the above-mentioned plurality of units, it will be compared in the above-mentioned one direction Long strips of magnetic thin sheets are arranged in the plurality of units, and the magnetic layer is formed from the magnetic thin sheet; Cutting in the direction where the directions intersect each other separates the plurality of units.

In this manufacturing method, one side of the thickness direction of a plurality of wires covering a plurality of units is combined, and a long magnetic sheet that is longer in one direction is arranged in a plurality of units, and the unit is singulated to form a magnetic field from the magnetic sheet. layers, it is possible to efficiently manufacture a plurality of inductors.

The inductor of the present invention can achieve both miniaturization and low resistance.

The method for manufacturing an inductor of the present invention can efficiently manufacture a plurality of inductors.

1: Inductor

2: Base layer

3: Conductor pattern

4: 1st bump

5: The second bump

6: Cover the insulating layer

7: The second magnetic layer

8: base insulating layer

9: Wiring

10: Magnetic layer

11: 1st electrode

12: 2nd electrode

13: Straight line

14: Connecting part

15:Wiring area

16: Conductor layer

17: Support flakes

18: unit

19: Magnetic sheet

20: laminated body

21: Connecting components

22: Inductor aggregate

24: 1st opening

25: The second opening

BS1: Plane area of the first bump

BS2: Plane area of the second bump

IL0: Imaginary shortest line segment

IL1: The first imaginary line segment

IL2: The second imaginary line segment

IL3: The 3rd imaginary line segment

IL4: The 4th imaginary line segment

IN: Space between the magnetic layer and the first and second bumps

L: Length between the first electrode and the second electrode along the long side direction (shortest direction)

LS1: Long side of the first electrode

LS2: Long side of the second electrode

S1: Plane area of the first electrode

S2: Plane area of the second electrode

SP: Interval

SS1: The short side of the first electrode

SS2: The short side of the second electrode

T1: Thickness of the first bump and the second bump

T2: The thickness of the magnetic layer

W: width

W ² : the square value of the width

W3: width

W4: width

X: Length in the direction of the long side

Y: length in the front and back directions

1A and 1B show an embodiment of the inductor of the present invention. FIG. 1A is a plan view omitting the covering insulating layer, and FIG. 1B is a plan view omitting the first bump, the second bump and the covering insulating layer.

Fig. 2 shows a cross-sectional view along line C-C of Figs. 1A and 1B.

3A to 3E are cross-sectional views of the manufacturing steps of the inductor shown in FIG. 2. FIG. 3A shows the steps of preparing the base insulating layer and the conductor layer. FIG. 3B shows the steps of setting wiring, the first electrode and the second electrode, and FIG. 3C It shows the step of providing the magnetic layer and the second magnetic layer, FIG. 3D shows the step of providing the first bump and the second bump, and FIG. 3E shows the step of providing the cover insulating layer.

4A to 4D are perspective views of the manufacturing steps of the inductor shown in FIG. 2. FIG. 4A shows the steps of preparing the base insulating layer and the conductor layer. FIG. 4B shows the steps of setting wiring, the first electrode and the second electrode, and FIG. 4C It shows the step of providing the magnetic layer and the second magnetic layer, and FIG. 4D shows the step of providing the first bump and the second bump, the step of providing the covering insulating layer, and the step of singulating the inductor assembly.

FIG. 5 shows a top view of a first modification example of the inductor shown in FIG. 1B.

6 and 7 show top views of a third modification example of the inductor shown in FIG. 1B.

FIG. 7 shows a top view of a third modification example of the inductor shown in FIG. 1B.

FIG. 8 shows a plan view of a fourth modification example of the inductor shown in FIG. 1B.

Fig. 9 is a sectional view showing a fifth modification of the inductor shown in Fig. 2 .

FIG. 10 shows a cross-sectional view of a sixth modification example of the inductor shown in FIG. 2 .

FIG. 11 shows a cross-sectional view of a seventh modification example of the inductor shown in FIG. 2 .

Fig. 12 is a cross-sectional view showing an eighth modification of the inductor shown in Fig. 2 .

Fig. 13 is a cross-sectional view showing a ninth modification of the inductor shown in Fig. 2 .

Fig. 14 is a cross-sectional view showing a tenth modification of the inductor shown in Fig. 2 .

15 is a plan view of the inductor of Comparative Example 1, which shows a plan view in which the first bump, the second bump and the insulating cover layer are omitted.

FIG. 16 shows a plan view of a further modification of the fourth modification of the inductor shown in FIG. 8 .

<An embodiment>

One embodiment of the inductor of the present invention will be described with reference to FIGS. 1A to 2 .

In FIG. 1A and FIG. 1B , the left-right direction on the paper surface represents the long-side direction of the inductor. The left side in FIG. 1A and FIG. 1B is one side in the longitudinal direction, and the right side in FIG. 1A and FIG. 1B is the other side in the longitudinal direction.

In FIG. 1A and FIG. 1B , the up-down direction represents the front-back direction (the short-side direction of the inductor). The lower side in FIGS. 1A and 1B is the front side (one side in the short-side direction), and the upper side in FIGS. 1A and 1B is the rear side (the other side in the short-side direction).

In FIG. 1A and FIG. 1B , the paper thickness direction represents the thickness direction of the inductor. The front side of the paper in Fig. 1A and Fig. 1B is the upper side (one side in the thickness direction), and the back side of the paper in Fig. 1A and Fig. 1B is the lower side (the other side in the thickness direction).

In the top view of FIG. 1A , in order to clearly show the relative arrangement of the first electrode 11, the second electrode 12, and the wiring 9 (wiring region 15) (described below) in the top view (the same meaning as when projected in the thickness direction), omit Covering insulating layer 6 (described below).

In the top view of FIG. 1B , in order to clearly show the relative arrangement of the first electrode 11, the second electrode 12, and the wiring 9 (wiring region 15) (described below) in a top view (the same meaning as when projected in the thickness direction), omit The first bump 4 , the second bump 5 , and the insulating cover layer 6 (described below), and the magnetic layer 10 (described below) are indicated by dotted lines.

The inductor 1 has a substantially rectangular sheet shape extending in the longitudinal direction. Inductor 1 includes base layer 2 , conductive pattern 3 , first bump 4 and second bump 5 , magnetic layer 10 , and cover insulating layer 6 .

The base layer 2 has a sheet shape having the same external shape as the inductor 1 . The base layer 2 includes a second magnetic layer 7 and an insulating base layer 8 in this order toward the upper side in the thickness direction.

The second magnetic layer 7 is a layer that imparts high inductance to the inductor 1 . The second magnetic layer 7 has a sheet shape having flat upper and lower surfaces along the longitudinal direction and the front-rear direction. The second magnetic layer 7 is the lowest layer of the inductor 1 . In addition, the second magnetic layer 7 is also a layer under the base layer 2 . The material of the second magnetic layer 7 can be, for example, a magnetic composition (specifically, a hardened magnetic composition) disclosed in JP-A-2014-189015 and the like. The thickness of the second magnetic layer 7 is, for example, 10 μm or more, preferably 50 μm or more, and, for example, 500 μm or less, preferably 300 μm or less.

The insulating base layer 8 is disposed on the entire upper surface of the second magnetic layer 7 . base insulation Layer 8 is a layer on top of base layer 2 . The insulating base layer 8 has flat upper and lower surfaces along the longitudinal direction and the front-back direction. The upper surface of the insulating base layer 8 forms the upper surface of the base layer 2 . In addition, the upper surface of the insulating base layer 8 is also a plane for arranging the conductor pattern 3 described below on the same plane. The material of the insulating base layer 8 includes, for example, inorganic materials such as glass and ceramics, organic materials such as polyimide and fluororesin, and insulating materials such as composite materials thereof (glass epoxy resin). The thickness of insulating base layer 8 is, for example, 0.1 μm or more, preferably 0.5 μm or more, and, for example, 15 μm or less, preferably 10 μm or less.

The thickness of the base layer 2 is the sum of the thickness of the second magnetic layer 7 and the base insulating layer 8, and is, for example, 10.1 μm or more, preferably 50.5 μm or more, and for example, 515 μm or less, preferably 310 μm or less.

The conductive pattern 3 is disposed on the upper surface of the base layer 2 . The conductive pattern 3 is an electrode pattern provided with the first electrode 11, the second electrode 12, and the wiring 9 consecutively.

The first electrode 11 is arranged on the upper surface of the insulating base layer 8 . Specifically, the first electrode 11 is located at one end in the longitudinal direction of the upper surface of the insulating base layer 8 (the left end in FIGS. 1A and 1B ). Also, the first electrode 11 is one end in the longitudinal direction of the conductor pattern 3 .

The first electrode 11 has a substantially rectangular shape in plan view extending in the short-side direction (front-rear direction).

The second electrode 12 is arranged on the upper surface of the insulating base layer 8 . Specifically, the second electrode 12 is disposed opposite to the first electrode 11 on the upper surface of the insulating base layer 8 on the other side in the longitudinal direction (the right side in FIGS. 1A and 1B ). Specifically, the second electrode 12 is located at the other end in the longitudinal direction of the upper surface of the insulating base layer 8 (the right end in FIGS. 1A and 1B ). Also, the second electrode 12 is the other end in the longitudinal direction of the conductive pattern 3 .

The second electrode 12 has the same shape as the first electrode 11 . That is, the second electrode 12 has a substantially rectangular shape in plan view extending in the short-side direction (front-rear direction). Formation of the first electrode 11 and the second electrode 12 1 pair of electrodes.

The opposing direction of the first electrode 11 and the second electrode 12 is a direction (shortest direction) along the imaginary shortest line segment IL0 (see FIG. 1A ) connecting the first electrode 11 and the second electrode 12 at the shortest distance. The shortest direction is the same as the long side direction of the inductor 1 . The length of the imaginary shortest line IL0 is the shortest distance (length L) between the first electrode 11 and the second electrode 12 .

The wiring 9 is arranged in a wiring area 15 as an example of the area.

The wiring region 15 is a region located between the first electrode 11 and the second electrode 12, specifically, has a length equal to the length L between the first electrode 11 and the second electrode 12 along the long side direction of the inductor 1. The length X in the longitudinal direction, and the length Y in the front-rear direction as an example of the length in the short-side direction in a direction perpendicular to the long-side direction. "The length L between the first electrode 11 and the second electrode 12" will be described in detail below.

The wiring region 15 is the first imaginary line segment IL1 along the other end edge (the right end edge, the end edge on the side close to the second electrode 12 ) of the inductor 1 along the longitudinal direction of the first electrode 11 , and along the The area between the second imaginary line segment IL2 of one end in the longitudinal direction of the second electrode 12 (the left end edge, the end edge on the side close to the first electrode 11 ), and the third imaginary line segment along the front edge of the wiring 9 The region between IL3 and the fourth imaginary line segment IL4 along the rear edge of the wiring 9 . Furthermore, in this embodiment, the third imaginary line segment IL3 is along the respective front edges of the first electrode 11 and the second electrode 12, and the fourth imaginary line segment IL4 is along the respective rear ends of the first electrode 11 and the second electrode 12. edge. The first imaginary line segment IL1 and the second imaginary line segment IL2 are parallel, and the third imaginary line segment IL3 and the fourth imaginary line segment IL4 are parallel. The substantially rectangular area in plan view partitioned by the line segment IL4 is the wiring area 15 . In this way, the planar area of the wiring region 15 is represented by the product (XY) of the length X in the longitudinal direction and the length Y in the front-back direction of the wiring region 15 .

The wiring 9 is arranged in the wiring region 15 so as to be continuous with the first electrode 11 and the second electrode 12 . The wiring 9 has a width W, and has a generally meandering shape in plan view in the wiring region 15 . Both ends of the wiring 9 are continuous with each of the first electrode 11 and the second electrode 12 . Specifically, the wiring 9 continuously has a plurality of linear portions 13 and a plurality of connecting portions 14 that connect one end portions or both end portions of two adjacent linear portions 13 in the longitudinal direction. The plurality of linear portions 13 are arranged at intervals from each other in the front-rear direction. Each of the plurality of linear portions 13 has a shape extending along the longitudinal direction. Among the plurality of straight portions 13 , for example, the straight portion 13 at the rear end is continuous with the rear end of the first electrode 11 , and the straight portion 13 at the front end is continuous with the front end of the second electrode 12 . Each of the plurality of connecting portions 14 is shorter than each of the plurality of straight portions 13 . The plurality of connection portions 14 are alternately arranged in the vicinity of the first electrode 11 and in the vicinity of the second electrode 12 in the wiring region 15 .

In addition, the first electrode 11, the second electrode 12, and the wiring 9 are located on the same plane. The first electrode 11, the second electrode 12, and the wiring 9 overlap each other when projected in the longitudinal direction, and more specifically, coincide with each other. Also, as can be seen from FIG. 2 , in the above projection, the upper and lower surfaces of the first electrode 11 , the second electrode 12 , and the wiring 9 also overlap, and more specifically, coincide.

The wiring 9, the first electrode 11, and the second electrode 12 in the conductive pattern 3 are made of the same material. The material of the conductor pattern 3 can be, for example, the conductor disclosed in Japanese Patent Application Laid-Open No. 2014-189015, preferably metal such as copper.

The thickness of the conductive pattern 3 is, for example, 5 μm or more, preferably 10 μm or more, and, for example, 300 μm or less, preferably 100 μm or less.

The dimensions and the like of the conductive pattern 3 in plan view will be described in detail below.

The first bump 4 is a contact point for electrical connection between the first electrode 11 and the connection member 21 (see the phantom line in FIG. 2 described below). The first bump 4 is arranged on the upper surface of the first electrode 11 . specific and In other words, the first bump 4 has a substantially rectangular box (plate) shape extending in the front-rear direction and the thickness direction. The first bump 4 has a shape substantially similar to that of the first electrode 11 . The lower surface of the first bump 4 is in contact with the central portion of the upper surface of the first electrode 11 , while the upper surface of the first bump 4 is exposed on the upper side. In addition, the peripheral end portion of the first electrode 11 is exposed from the first bump 4 . The side surfaces (both sides in the longitudinal direction and front and rear surfaces) of the first bump 4 are covered with an insulating cover layer 6 described below. Since the first bump 4 is in contact with the upper surface of the first electrode 11, it is also a first electrode post. As a material of the 1st bump 4, the above-mentioned conductor (including solder) is mentioned.

The ratio (BS1/S1) of the planar area BS1 of the first bump 4 to the planar area S1 (described below) of the first electrode 11 is, for example, 70% or more, preferably 80% or more, more preferably 90% or more, Also, for example, it is 100% or less. When BS1/S1 is more than the above lower limit, the resistance of the first bump 4 and the first electrode 11 can be reduced, and the reduction of the electrical connection reliability between the electronic device (not shown) and the first electrode 11 can be suppressed.

The second bump 5 is a contact point used for electrical connection between the second electrode 12 and the connection member 21 (see phantom line in FIG. 2 described below). The second bump 5 is arranged on the upper surface of the second electrode 12 . Specifically, the second protrusion 5 has a substantially rectangular box (plate) shape extending in the front-rear direction and the thickness direction. The second bump 5 has a substantially similar shape to the second electrode 12 . The lower surface of the second bump 5 is in contact with the central portion of the upper surface of the second electrode 12 , while the upper surface of the second bump 5 is exposed on the upper side. In addition, the peripheral end portion of the second electrode 12 is exposed from the second bump 5 . The side surfaces (both sides in the longitudinal direction and front and rear surfaces) of the second bump 5 are covered with an insulating cover layer 6 described below. Since the second bump 5 is in contact with the upper surface of the second electrode 12, it is also a second electrode post. The material of the second bump 5 is the same as that of the first bump 4 .

The ratio (BS2/S2) of the planar area BS2 of the second bump 5 to the planar area S2 (described below) of the second electrode 12 is, for example, 70% or more, preferably 80% or more, more preferably 90% More than, and, for example, 100% or less. When BS2/S2 is more than the above-mentioned lower limit, the resistance of the second bump 5 and the second electrode 12 can be reduced, and the reduction of the electrical connection reliability between the electronic device (not shown) and the second electrode 12 can be suppressed.

The thickness T1 of the first bump 4 and the thickness T1 of the second bump 5 are the same as each other, for example, 15 μm or more, preferably 50 μm or more, and for example, 600 μm or less, preferably 500 μm or less. Furthermore, the thickness T1 of the first bump 4 is the distance from the top surface of the first electrode 11 (conductor pattern 3 ) to the top surface of the first bump 4 . The thickness T1 of the second bump 5 is the distance from the upper surface of the second electrode 12 (conductor pattern 3 ) to the upper surface of the second bump 5 .

The magnetic layer 10 is a layer that imparts high inductance in the inductor 1 . The magnetic layer 10 has a substantially sheet shape extending in the long-side direction and the short-side direction of the inductor 1 . The magnetic layer 10 covers the wiring 9 on the insulating base layer 8 . Therefore, the magnetic layer 10 has a lower surface corresponding to the shape of the wiring 9 and a flat upper surface facing the upper side of the lower surface. On the other hand, the magnetic layer 10 is located inside the first electrode 11 and the second electrode 12 at intervals in the longitudinal direction of the inductor 1 , and does not cover the first electrode 11 and the second electrode 12 .

That is, one end edge in the longitudinal direction of the magnetic layer 10 is located on the other side in the longitudinal direction with a slight distance from the other end edge in the longitudinal direction of the first bump 4 , and the other end edge in the longitudinal direction of the magnetic layer 10 is It is located on one side in the longitudinal direction with a slight interval from one end edge in the longitudinal direction of the second bump 5 . Specifically, the magnetic layer 10 is separated from the first bump 4 and the second bump 5 in the longitudinal direction by an interval IN of, for example, 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. For example, the interval IN is 10 μm or less.

If the said interval IN is more than the said minimum, the short circuit of the 1st bump 4 and the 2nd bump 5, and the magnetic layer 10 can be prevented effectively.

Also, when the front and rear ends of the magnetic layer 10 are projected in the thickness direction, they are aligned with the substrate. The front and rear edges of layer 2 are consistent.

The thickness T2 of the magnetic layer 10 is shorter than the thickness T1 of the 1st bump 4 and the 2nd bump 5, for example. In other words, the thickness T1 of the first bump 4 and the second bump 5 is longer than the thickness T2 of the magnetic layer 10 .

Specifically, the thickness T2 of the magnetic layer 10 relative to the thickness T1 of the first bump 4 and the second bump 5 is, for example, 99% or less, preferably 97% or less, more preferably 95% or less, and, for example, More than 70%.

Specifically, the thickness T2 of the magnetic layer 10 is, for example, 500 μm or less, preferably 300 μm or less, more preferably 100 μm or less, and, for example, 10 μm or more.

If the thickness T2 of the magnetic layer 10 is below the said upper limit, miniaturization of the inductor 1 can be realizable.

Furthermore, the thickness T2 of the magnetic layer 10 is the distance from the upper surface of the wiring 9 (conductor pattern 3 ) to the upper surface of the magnetic layer 10 .

If the thickness T1 of the first bump 4 and the second bump 5 is longer than the thickness T2 of the magnetic layer 10, the connecting member 21 (described below) and the first bump 4 and the second bump 5 When the surfaces are in contact, the connecting member 21 is less likely to be in contact with the magnetic layer 10 , so the electrical connection reliability between the electronic device (not shown) and the first electrode 11 and the second electrode 12 can be improved.

The material of the magnetic layer 10 is the same as that of the second magnetic layer 7 .

The cover insulating layer 6 is a protective insulating layer for protecting the first electrode 11 , the second electrode 12 and the wiring 9 . The insulating cover layer 6 is formed on the insulating base layer 8 , covers the first electrode 11 , the first bump 4 , the second electrode 12 , and the second bump 5 , and covers the entire magnetic layer 10 . Specifically, the insulating cover layer 6 covers the side surfaces of the first bump 4 , the side surface of the second bump 5 , the peripheral end and the side surface of the upper surface of the first electrode 11 , and the peripheral end of the upper surface of the second electrode 12 . head and sides. In addition, the insulating cover layer 6 covers the side surfaces and the upper surface of the magnetic layer 10 . Further, the cover insulating layer 6 also covers the base insulating layer. The portion of the upper surface of the insulating layer 8 other than the portion where the first electrode 11 and the second electrode 12 and the magnetic layer 10 are formed. Therefore, the insulating cover layer 6 has a lower surface corresponding to the first electrode 11 and the second electrode 12 and the magnetic layer 10 , and a flat upper surface facing the upper side of the lower surface. In addition, the upper surface of the insulating cover layer 6 is flush with the upper surfaces of the first bump 4 and the second bump 5 . That is, the upper surface of the insulating cover layer 6 and the upper surfaces of the first bump 4 and the second bump 5 form one plane. In addition, the peripheral edge of the insulating cover layer 6 coincides with the peripheral edge of the base layer 2 when projected in the thickness direction.

The material of the covering insulating layer 6 is the same as that of the base insulating layer 8 . The thickness of the insulating cover layer 6 is, for example, 120 μm or less, preferably 100 μm or less, and, for example, 0.1 μm or more, preferably 0.3 μm or more.

Next, the relationship between the length L between the first electrode 11 and the second electrode 12 and the length X of the wiring region 15 in the longitudinal direction will be described in detail in comparison with Comparative Example 1, which is outside the scope of the present invention.

As shown in FIGS. 1A and 1B , in one embodiment, the length L between the first electrode 11 and the second electrode 12 is equal to the length X of the wiring region 15 in the longitudinal direction.

Also, as shown in FIG. 5 , in the first modification within the scope of the present invention, which will be described in detail below, when the first electrode 11 and the second electrode 12 are projected in the longitudinal direction, a part of them overlaps, and the The length of the imaginary shortest line segment IL0 connecting the first electrode 11 and the second electrode 12 at the shortest distance, that is, the length L between the first electrode 11 and the second electrode 12 is equal to the length X of the wiring region 15 in the longitudinal direction.

On the other hand, as shown in FIG. 15 , in Comparative Example 1, the first electrode 11 and the second electrode 12 do not overlap (offset) when projected in the longitudinal direction, and the imaginary shortest line segment IL0, that is, the first The length L between the first electrode 11 and the second electrode 12 is longer than the length X of the wiring region 15 in the longitudinal direction. That is, the length L between the first electrode 11 and the second electrode 12 and the length direction of the wiring region 15 The length X is different. Therefore, Comparative Example 1 is outside the scope of the present invention.

Next, as shown in FIG. 1A and FIG. 1B , the dimension of the conductor pattern 3 in plan view will be described in detail.

The average value of the width W of the wiring 9 is, for example, 500 μm or less, preferably 100 μm or less, and, for example, 10 μm or more, preferably 50 μm or more. In addition, the interval SP between the adjacent linear portions 13 is equal to the width W described above. Moreover, the number of wiring 9 is not specifically limited, For example, it is 1 or more, Preferably it is 3 or more, Also, for example, it is 1000 or less, Preferably it is 100 or less.

The planar area S1 of the first electrode 11 and the ^{planar area S2 of the second electrode 12 are each equal to or greater than the square value (W 2 )} of the width W of the wiring 9. Specifically, the ratio (S1/ W ² or S2/W ² ) exceeds 1, preferably 2 or greater, more preferably 3 or greater, further preferably 4 or greater, particularly preferably 5 or greater, and, for example, 100 or less.

If the planar area S1 of the first electrode 11 and the planar area S2 of the second electrode 12 are each smaller than the square value (W ² ) of the width W of the wiring 9, the inductor 1 cannot be reduced in resistance. In other words, if the planar area S1 of the first electrode 11 and the planar area S2 of the second electrode 12 are equal to or larger than the square value (W ² ) of the width W of the wiring 9, the resistance of the inductor 1 can be reduced.

Furthermore, since the first electrode 11 is rectangular, the planar area S1 of the first electrode 11 can be determined according to the length (short side) SS1 of the first electrode 11 in the long side direction of the inductor 1 and the length (short side) SS1 of the first electrode 11 in the front and back direction. The length (long side) LS1 of 11 is calculated|required, specifically, it is SS1*LS1.

Since the second electrode 12 is rectangular, the plane area S2 of the second electrode 12 can be determined according to the length (short side) SS2 of the second electrode 12 in the long side direction of the inductor 1 and the length of the second electrode 12 in the front and back direction. (Long side) LS2 is calculated|required, specifically, it is SS2*LS2.

Specifically, the plane area S1 of the first electrode 11 and the plane area S2 of the second electrode 12 are, for example, 10,000 μm ² or more, preferably more than 20,000 μm ² , more preferably more than 25,000 μm ² , and, for example, 100,000 μm ² or less, preferably 50,000 μm ² or less.

The ratio (LS1/W) of the long side LS1 of the first electrode 11 to the width W of the wiring 9 is, for example, 1 or more, preferably 2 or more, more preferably 4 or more, and for example, 50 or less. The short side SS1 of the first electrode 11 is appropriately set corresponding to the above-mentioned planar area S1 and long side LS1 .

The ratio (LS2/W) of the long side LS2 of the second electrode 12 to the width W of the wiring 9 is the same as the above ratio (LS1/W). The short side SS2 of the second electrode 12 is appropriately set corresponding to the above-mentioned planar area S2 and long side LS2.

Also, the length X in the longitudinal direction of the wiring region 15 is equal to or greater than 1.5 times the length Y in the shorter direction.

That is, the following formula (1) is satisfied.

X/Y≧1.5 (1)

It is preferable to satisfy the following formula (2).

X/Y≧2.0 (2)

If X/Y is lower than the above-mentioned lower limit (1.5 in formula (1), 2.0 in formula (2)), further miniaturization in the front-back direction of the second bump 5 cannot be achieved. In other words, if X/Y is more than the above-mentioned lower limit, further miniaturization in the front-back direction of the second bump 5 can be realized, and as a result, the miniaturization of the inductor 1 can be realized.

Next, the manufacturing method of the inductor 1 will be described with reference to FIGS. 3A to 3E and FIGS. 4A to 4D.

As shown in FIGS. 3A and 4A , in this method, first, the insulating base layer 8 and the conductor layer 16 are prepared.

The insulating base layer 8 is prepared in the form of a long sheet that is long in the front-back direction (short-side direction) of the finally obtained inductor 1 . On the other hand, base insulating layer 8 has the same inductance as The length in the longitudinal direction of the device 1 is the same as the width W3.

The conductive layer 16 is a thin conductive sheet disposed on the entire surface of the insulating base layer 8 . The material of the conductive layer 16 is the same as that of the conductive pattern 3 .

In addition, the insulating base layer 8 and the conductor layer 16 can be prepared in a state supported by the support sheet 17 from below. The support sheet 17 is a spacer made of resin or metal.

That is, the laminated body 20 provided with the support sheet 17, the 2nd magnetic layer 7, and the conductor layer 16 sequentially toward the upper side in the thickness direction is prepared.

As shown in FIGS. 3B and 4B , next, the conductive pattern 3 is formed from the conductive layer 16 . For example, the conductor pattern 3 which has the 1st electrode 11, the 2nd electrode 12, and the wiring 9 is formed by the subtractive method etc. which include etching. Specifically, a plurality of cells 18 including one first electrode 11 , one second electrode 12 , and one wiring 9 are formed along the front-back direction (the longitudinal direction of the insulating base layer 8 ).

As shown in FIG. 3C and FIG. 4C , next, the magnetic layer 10 is provided on the base insulating layer 8 in such a manner as to cover the wiring 9 .

To provide the magnetic layer 10, first, as shown in the upper side view of FIG. 3B and the upper side view of FIG. 4B, a magnetic sheet 19 having a long sheet shape long in the front-rear direction is prepared.

The width W4 of the magnetic sheet 19 is the same as the length in the longitudinal direction of the plurality of magnetic layers 10 . The material of the magnetic sheet 19 can be, for example, the curable magnetic composition disclosed in Japanese Patent Application Laid-Open No. 2014-189015. The thickness of the magnetic sheet 19 can be appropriately set according to the thickness of the magnetic layer 10 to be obtained.

Next, as shown by the arrows in FIG. 3B and FIG. 4B , the magnetic sheets 19 are arranged on the plurality of units 18 so as to collectively cover the upper surfaces and side surfaces of the plurality of wirings 9 in the plurality of units 18 . Specifically, one long magnetic sheet 19 is pressed (pressed down) against the plurality of cells 18 . As shown in Figure 3C and Figure 4C, thereafter or simultaneously with pressing, if necessary, make the magnetic The flakes 19 are hardened to form the magnetic layer 10 continuous in the front-back direction.

At the same time, the second magnetic layer 7 is provided on the lower surface of the insulating base layer 8 . In order to install the second magnetic layer 7, first, the support sheet 17 shown in FIG. The second magnetic layer 7 is formed.

As shown in FIGS. 3D and 4D , first bumps 4 and second bumps 5 are then provided. Specifically, a plurality of first bumps 4 and a plurality of second bumps 5 are formed on the upper surfaces of the first electrodes 11 and the second electrodes 12 by, for example, an additive method, a subtractive method, and other patterning methods.

Thereafter, the cover insulating layer 6 is provided in the above-described pattern.

As shown by the imaginary line in FIG. 4D, thereby, a plurality of inductor aggregates 22 are collectively manufactured, and the inductor aggregates 22 include a base layer 2, a plurality of units 18 (refer to FIG. 4C ), and a plurality of first bumps. Block 4 and a plurality of second bumps 5 , one magnetic layer 10 , and one cover insulating layer 6 .

Thereafter, as shown by the thick imaginary line in FIG. 4D , in the inductor assembly 22, the plurality of units 18, the plurality of first bumps 4, and the plurality of second bumps 5 are singulated. The strip-shaped covering insulating layer 6 (refer to FIG. 3E ), the strip-shaped magnetic layer 10 , and the strip-shaped base layer 2 (the base insulating layer 8 and the second magnetic layer 7 ) are along the thickness direction of the inductor 1 (the direction perpendicular to the front-back direction) cut off.

In this way, an inductor 1 including one base layer 2, one conductive pattern 3, one first bump 4 and one second bump 5, one magnetic layer 10, and one cover insulating layer 6 is manufactured. . Preferably, the inductor 1 is composed only of the base layer 2 , the conductive pattern 3 , the first bump 4 and the second bump 5 , the magnetic layer 10 , and the insulating cover layer 6 .

Inductor 1 is not the following electronic equipment, but a part of electronic equipment, that is, a part used to make electronic equipment, does not contain electronic components (chips, capacitors, etc.), or install electrical components Sub-component mounting substrates are distributed in the form of individual parts and are industrially available devices.

This inductor 1 is mounted (assembled) in, for example, an electronic device or the like. Although not shown in the figure, an electronic device includes a mounting board and electronic components (chips, capacitors, etc.) mounted on the mounting board. Furthermore, in an electronic device, the inductor 1 is mounted on a mounting board.

Specifically, as shown by phantom lines in FIG. 2 , connection members 21 such as wires or solder are in contact with the upper surfaces of the first bump 4 and the second bump 5 . The inductor 1 is mounted on a mounting board via the connection member 21, and is electrically connected to other electronic devices, and functions as a passive element.

Furthermore, in this inductor 1, since the wiring 9, the first electrode 11, and the second electrode 12 are located on the same plane, miniaturization in the thickness direction can be achieved. In addition, since the length X of the wiring region 15 in the longitudinal direction is 1.5 times or more the length Y in the front-back direction, the miniaturization of the wiring region 15 in the front-back direction can be realized. As a result, further miniaturization of the inductor 1 can be realized.

In addition, in this inductor 1, the planar area S1 of the first electrode 11 and the planar area S2 of the second electrode 12 are each equal to or greater than the square value (W ² ) of the width W of the wiring 9, so that the low resistance of the inductor 1 can be realized. change.

Since this inductor 1 further includes a magnetic layer 10, high inductance can be ensured.

In this inductor 1, high inductance of the inductor 1 can be ensured, and if the thickness T2 of the magnetic layer 10 is 500 micrometers or less, the miniaturization of the inductor 1 can be realized.

Since the inductor 1 includes the first bump 4 and the second bump 5, if the connection member 21 is brought into contact with the upper surfaces of the first electrode 11 and the second electrode 12, an electronic device on which the inductor 1 is mounted can be easily realized. (not shown), electrical connection with the first electrode 11 and the second electrode 12 .

In the inductor 1, if the ratio of the planar area BS1 of the first bump 4 to the planar area S1 of the first electrode 11 is 70% or more, and the ratio of the planar area BS2 of the second bump 5 to the planar area S1 of the second electrode 12 is The ratio of the plane area S2 is more than 70%, then the low resistance of the inductor 1 can be realized It can suppress the reduction of the electrical connection reliability between the electronic device (not shown) and the first electrode 11 and the second electrode 12.

In this inductor 1, if the length T1 in the thickness direction of the first bump 4 and the second bump 5 is longer than the thickness T2 of the magnetic layer 10, the connecting member 21 and the first bump 4 and the second bump When the upper surface of the bump 5 is in contact, the connecting member 21 is not easily in contact with the magnetic layer 10. Therefore, the short circuit caused by the connecting member 21 contacting the magnetic layer 10 can be suppressed, and the electronic equipment (not shown) and the first The electrical connection reliability between the electrode 11 and the second electrode 12 is improved.

In this inductor 1, if the first bump 4 and the second bump 5 and the magnetic layer 10 are arranged with an interval IN of 100 μm or more in the plane direction, it is possible to effectively prevent the first bump 4 and the second bump from Block 5, short circuit with magnetic layer 10. Therefore, the electrical connection reliability between an electronic device (not shown) and the first electrode 11 and the second electrode 12 can be improved.

Since the inductor 1 is provided with the covering insulating layer 6, the first electrode 11, the second electrode 12, and the wiring 9 can be covered (protected) by the covering insulating layer 6, so that the electrical connection reliability can be improved.

Since the inductor 1 further includes the second magnetic layer 7 in addition to the magnetic layer 10, high inductance can be ensured.

In the manufacturing method of the inductor 1, the upper surfaces of the plurality of wires 9 in the plurality of units are collectively covered, and the long magnetic sheets 19 that are long in the front-rear direction are arranged on the plurality of units 18. The flakes 19 form the magnetic layer 10 . That is, an inductor aggregate 22 including a plurality of inductors 1 is manufactured. Thereafter, the inductor assembly 22 is singulated to manufacture a plurality of inductors 1 . As a result, a plurality of inductors 1 can be manufactured efficiently.

<Changes>

In each of the following variations, for the same components and steps as those in the above-mentioned embodiment, mark Note the same reference symbols and omit their detailed description. In addition, each modification example can be combined suitably. Furthermore, each modification example can exhibit the same operation and effect as that of the one embodiment, unless otherwise stated.

In addition, in the top views of FIGS. 5 to 8 , in order to clearly show the relative arrangement of the first electrode 11, the second electrode 12, and the wiring 9 (wiring region 15), the first bump, the second bump, and the insulating cover layer are omitted. .

Variation 1

As shown in FIG. 5 , in the inductor 1 , when the first electrode 11 and the second electrode 12 are projected in the longitudinal direction, they partially overlap each other. Specifically, when projected in the longitudinal direction, the first electrode 11 overlaps the rear side portion of the wiring region 15 and the central portion in the front-rear direction. When projected in the longitudinal direction, the second electrode 12 overlaps the front side portion and the front-back direction center portion of the wiring region 15 . Therefore, when projected in the longitudinal direction, the front end portion of the first electrode 11 , the rear end portion of the second electrode 12 , and the center portion in the front-rear direction of the wiring region 15 overlap.

In addition, the front end of the first electrode 11 and the rear end of the second electrode 12 face each other in the longitudinal direction. Therefore, the imaginary shortest line segment IL0 connecting the first electrode 11 and the second electrode 12 at the shortest distance is a line segment along the longitudinal direction. Similar to the first embodiment, the length of the imaginary shortest line segment IL0 is the length of the first electrode 11. The length L between the second electrode 12 and the second electrode 12 is equal to the length X of the wiring region 15 in the longitudinal direction.

Variation 2

The pattern shape of the wiring 9 is not limited to the above. As shown in FIG. 6 , in the second modification, a plurality of linear portions 13 are arranged at intervals from each other in the longitudinal direction. The plurality of linear portions 13 extend in the front-rear direction, respectively.

Variation 3

As shown in FIG. 7 , in the third modification example, the wiring 9 has only one connecting portion 14 . Link 14 It is located at the central portion in the longitudinal direction, and connects one end edge of the front linear portion 13 in the longitudinal direction to the longitudinal end of the rear linear portion 13 in the front-rear direction. In the third modification example, the length of the connecting portion 14 may be the same as that of the straight portion 13 or longer than that of the straight portion 13 .

Variation 4

As shown in FIG. 8 , in the fourth modification, the plurality of linear portions 13 are arranged at intervals from each other in the first inclination direction that inclines to one side in the longitudinal direction as it goes to the front. Each of the plurality of linear portions 13 has a shape extending in a direction perpendicular to the first inclination direction (a second inclination direction inclining to the other side in the longitudinal direction as it goes to the front side).

The connecting portion 14 may have, for example, a planar curved shape.

Variation 5

As shown in FIG. 9 , the inductor 1 does not include the second magnetic layer 7 (see FIG. 2 ). The base layer 2 does not include the second magnetic layer 7 , but consists only of the insulating base layer 8 . The insulating base layer 8 is the lowest layer of the inductor 1 .

Variation 6

As shown in FIG. 10 , the inductor 1 does not include the insulating base layer 8 (see FIG. 2 ). Base layer 2 does not include base insulating layer 8 , and is composed of only second magnetic layer 7 . The upper surface of the second magnetic layer 7 is a plane for arranging the conductor patterns 3 on the same plane. That is, the conductive pattern 3 is arranged on the upper surface of the second magnetic layer 7 .

Variation 7

As shown in FIG. 11 , the magnetic layer 10 also covers the peripheral end portion of the first electrode 11 and the peripheral end portion of the second electrode 12 . In the seventh modification example, the magnetic layer 10 is also separated from the first bump 4 and the second bump 5 by the above-mentioned interval IN in the longitudinal direction.

Variation 8

As shown in FIG. 12 , each of the first bump 4 and the second bump 5 is arranged below each of the first electrode 11 and the second electrode 12 . Each of the first bump 4 and the second bump 5 is in contact with the lower surface of the first electrode 11 and the second electrode 12 .

The insulating cover layer 6 is disposed under the insulating base layer 8 . The insulating cover layer 6 covers the side surfaces of the first bump 4 and the second bump 5 , and the lower surface and side surfaces of the second magnetic layer 7 .

The covering insulating layer 6 is smaller than the base insulating layer 8 in plan view.

The first bump 4 and the second bump 5 penetrate through the insulating base layer 8 and the insulating cover layer 6 in the thickness direction, respectively, and their lower surfaces are flush with the lower surface of the insulating cover layer 6 .

The second magnetic layer 7 is separated from the first bump 4 and the second bump 5 by an interval IN in the longitudinal direction.

Variation 9

As shown in Figure 13, the first bump 4 and the second bump 5 are in contact with the lower surfaces of the first electrode 11 and the second electrode 12 respectively, and the second magnetic layer 7 also covers the first bump 4 and the second bump. The peripheral end of block 5. Also in the ninth modification example, the second magnetic layer 7 is separated from the first bump 4 and the second bump 5 by the above-mentioned interval IN in the longitudinal direction.

Variation 10

As shown in FIG. 14 , the inductor 1 does not include the first bump 4 and the second bump 5 (see FIG. 2 ). That is, the inductor 1 is constituted only by the base layer 2 , the conductive pattern 3 , the magnetic layer 10 , and the insulating cover layer 6 .

The insulating cover layer 6 has a first opening 24 and a second opening 25 exposing the central portions of the respective upper surfaces of the first electrode 11 and the second electrode 12 .

The connection member 21 is in contact with each of the upper surfaces of the first electrode 11 and the second electrode 12 through each of the first opening 24 and the second opening 25 .

Other Variations

In one embodiment, the third imaginary line segment IL3 and the fourth imaginary line segment IL4 defining the wiring region 15 are along the respective front and rear edges of the first electrode 11 and the second electrode 12, but for example, as shown in FIG. As shown, as a further variation of the fourth variation example, the third imaginary line segment IL3 may also be located on the front side of the front edge of the first electrode 11 and the second electrode 12, and the fourth imaginary line segment IL4 may be located on the front side of the first electrode 11 and the second electrode 12. The rear end edges of the electrode 11 and the second electrode 12 are closer to the rear side.

In one embodiment, the conductive pattern 3 is formed by a subtractive method. Although not shown in the figure, the conductive layer 16 may not be prepared, and the conductive pattern 3 may be formed on the upper surface of the insulating base layer 8 by an additive method using a seed film. .

In addition, the inductor 1 can also be manufactured by either the roll-to-roll method or the monolithic method.

In one embodiment, as shown in FIG. 3D , the first bump 4 and the second bump 5 are provided, and thereafter, as shown in FIG. 3E , the insulating cover layer 6 is provided. However, although not shown, the insulating cover layer 6 may be provided in a pattern having the first opening 24 and the second opening 25 first, and then the first bump 4 and the second bump 5 may be provided.

Example

Examples and comparative examples are shown below to more specifically describe the present invention. In addition, this invention is not limited at all by an Example and a comparative example. Specific numerical values such as compounding ratios (content ratios), physical property values, and parameters used in the following descriptions can replace the corresponding compounding ratios (content ratios), physical property values, parameters, etc. described in the above-mentioned "embodiments" Limit value (defined as "below", "less than" value) or lower limit value (defined as "above", "exceeded" value).

Example 1

The inductor 1 of one embodiment shown in FIGS. 1A to 2 is manufactured according to the above-mentioned manufacturing method. Inductor 1 includes second magnetic layer 7 , base insulating layer 8 , conductive pattern 3 , first bump 4 and second bump 5 , magnetic layer 10 , and cover insulating layer 6 .

The conductive pattern 3 includes the first electrode 11, the second electrode 12, and the wiring 9, is made of copper, and has a thickness of 50 μm. Also, the material of the first bump 4 and the second bump 5 is SnAgCu solder, and the thickness is 140 μm.

The material of the second magnetic layer 7 and the magnetic layer 10 is the magnetic composition described in Example 1 of Japanese Patent Application Laid-Open No. 2014-189015.

The dimensions of the first electrode 11 , the second electrode 12 , and the wiring 9 , and the interval IN between the first bump 4 and the second bump 5 and the magnetic layer 10 are as described in Table 1, respectively.

Embodiment 2~Comparative example 1

The inductor 1 was prepared in the same manner as in Example 1 except that the dimensions and the like of the first electrode 11 and the second electrode 12 were changed as described in Table 1.

In addition, Example 3 is the inductor 1 of the 1st modification shown in FIG. 5, and the comparative example 1 is the inductor 1 outside the range of this invention shown in FIG.

<assessment>

[resistance]

The resistance R1 between the first electrode 11 and the second electrode 12 shown in FIG. 3B and FIG. 4B in the process of manufacture, and the first bump 4 and the second bump 5 of the obtained inductor 1 were respectively measured by the four-terminal method Calculate the resistance R2 between the first electrode 11 and the second electrode 12 relative to the resistance R2 between the first bump 4 and the second bump 5 (R1/R2×100).

[short circuit]

Measure the resistance value between the first bump 4 and the magnetic layer 10 by the two-terminal method, and evaluate according to the following Short-circuit property (conductivity) between the first bump 4 and the magnetic layer 10 .

○: 1 MΩ or more.

Δ: More than 0.1 MΩ and less than 1 MΩ.

×: Less than 0.1 MΩ.

In addition, the above-mentioned invention is provided as an exemplary embodiment of the present invention, but it is only an illustration and should not be interpreted limitedly. Modifications of the present invention that are clear to those skilled in the art are included in the following claims.

[Industrial availability]

Inductors are used, for example, as passive components.

1‧‧‧Inductor

2‧‧‧Base layer

3‧‧‧conductor pattern

4‧‧‧1st bump

5‧‧‧The second bump

6‧‧‧Covering insulating layer

8‧‧‧Insulating base layer

9‧‧‧Wiring

10‧‧‧Magnetic layer

11‧‧‧1st electrode

12‧‧‧Second electrode

13‧‧‧straight line

14‧‧‧connection part

15‧‧‧Wiring area

IL0‧‧‧imaginary shortest line segment

IL1‧‧‧1st imaginary line segment

IL2‧‧‧The second imaginary line segment

IL3‧‧‧3rd imaginary line segment

IL4‧‧‧4th imaginary line segment

L‧‧‧The length between the first electrode and the second electrode along the long side direction (shortest direction)

LS1‧‧‧long side of the first electrode

LS2‧‧‧long side of the second electrode

SP‧‧‧Interval

SS1‧‧‧The short side of the first electrode

SS2‧‧‧Short side of the second electrode

W‧‧‧Width

W3‧‧‧width

X‧‧‧long side length

Y‧‧‧Length in front and rear direction

Claims (10)

An inductor characterized by comprising: a wiring having a width W; and a first electrode and a second electrode continuous with each of both ends of the wiring; and the wiring, the first electrode, and the second The electrodes are located on the same plane, the plane area S1 of the above-mentioned first electrode and the plane area S2 of the above-mentioned second electrode are respectively more than the square value (W ² ) of the above-mentioned width W, and the area where the above-mentioned wiring is arranged is located between the above-mentioned first electrode and the above-mentioned Between the second electrodes, the region has: a length X in the longitudinal direction equal to the length L between the first electrode and the second electrode along the opposing direction of the first electrode and the second electrode, and relative to The length Y in the short direction in the direction perpendicular to the long side direction, and the length X in the long side direction is at least 1.5 times the length Y in the short side direction. The inductor according to claim 1, further comprising a magnetic layer covering one side of the wiring in the thickness direction. The inductor according to claim 2, wherein the thickness of the above-mentioned magnetic layer is 500 μm or less. The inductor according to claim 2, further comprising: a first bump disposed on one side of the first electrode in the thickness direction; and a second bump disposed on one side of the second electrode in the thickness direction. The inductor according to claim 4, wherein the ratio of the planar area BS1 of the first bump to the planar area S1 of the first electrode is 70% or more, and the planar area BS2 of the second bump is larger than that of the second electrode. The ratio of the planar area S2 of the electrode is 70% or more. The inductor according to claim 4, wherein the length in the thickness direction of the first bump and the second bump is longer than the thickness of the magnetic layer. The inductor according to claim 4, wherein the first bump and the second bump are arranged at a distance of 0.1 μm or more from the magnetic layer in the plane direction. The inductor according to claim 4, further comprising an insulating covering layer covering the surroundings of the first bump and the second bump and arranged between the wiring, the first electrode, and the second electrode One side in the thickness direction. The inductor according to claim 1, further comprising: an insulating base layer arranged on the other surface of the wiring in the thickness direction; and a second magnetic layer arranged on the other surface of the insulating base layer in the thickness direction. A manufacturing method of an inductor, characterized in that it is a manufacturing method for manufacturing an inductor according to claim 2, and has the following steps: making a plurality of wires including one of the above-mentioned wires, one A unit of the above-mentioned first electrode and one of the above-mentioned second electrodes; in such a way as to collectively cover one side in the thickness direction of the above-mentioned plurality of wirings in the above-mentioned plurality of units, arrange the elongated magnetic sheet that is longer in the above-mentioned one direction In the plurality of units, the magnetic layer is formed from the magnetic sheet; and the magnetic layer is cut in a direction crossing the one direction to separate the plurality of units into pieces.

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