TWI899670B - Etching analysis system and etching analysis method - Google Patents

Abstract

An etching analysis system and an etching analysis method are provided. The etching analysis system includes a measuring device and a processing device. The measuring device is configured to measure the substrate and obtain image information of a first region of the substrate. The processing device is electrically connected to the measuring device. The processing device is configured to generate measurement circuit information according to the image information, and is configured to adjust operating parameters or circuit layout parameters for an etching device according to the measurement circuit information.

Description

Etching analysis system and etching analysis method

The present invention relates to etching analysis technology, and in particular to a non-contact etching analysis system and etching analysis method.

Etching processes are widely used to form complex circuit patterns on various substrates, thereby creating electronic components such as printed circuit boards (PCBs) and flexible circuit boards (FPCs). As electronic components continue to shrink in size, the dimensions of circuit patterns are also becoming increasingly refined. However, this miniaturization presents challenges for etching processes. For example, during the etching process, some locations on the substrate may experience unexpected etching rates, resulting in non-conforming circuit patterns or even failure.

In prior art, wet etching processes typically involve immersing a substrate, equipped with a patterned mask and a conductive layer, in an etching solution to form electronic components with a specific circuit pattern. Ideally, the resulting circuit pattern has stable line widths (e.g., upper and lower line widths) and line heights. However, in practice, different locations on a single substrate may exhibit different etching rates, resulting in non-uniform line widths in the resulting circuit pattern. In some cases, different substrates produced within the same batch may also exhibit different etching rates at corresponding locations (e.g., the center region). As a result, the electronic components may not meet design requirements.

Therefore, how to effectively analyze the etching process and improve the potential problems mentioned above has become an urgent issue in this field.

In some embodiments, an etch analysis system is provided. The etch analysis system includes a metrology device and a processing device. The metrology device is configured to measure a substrate and obtain image information of a first area of the substrate. The processing device is electrically connected to the metrology device. The processing device is configured to generate measurement circuit information based on the image information and to adjust an operating parameter or a circuit layout parameter of the etch device based on the measurement circuit information.

In some embodiments, an etching analysis method is provided. The etching analysis method includes: measuring a substrate using a measurement device to obtain image information of a first area of the substrate; generating measurement circuit information based on the image information using a processing device; and adjusting an operating parameter or a circuit layout parameter of an etching device using the processing device based on the measurement circuit information.

The disclosed etching analysis system and etching analysis method utilize imaging for non-contact inspection. Inspection accuracy and convenience are unaffected by electronic component size, and they can be applied to etching processes for a wide variety of electronic components, demonstrating their wide applicability. To further enhance the understanding of the features and advantages of this disclosure, various embodiments are presented below, along with accompanying figures, for detailed description.

1: Etching Analysis System

11: Measuring device

11a: First image capture device

11b: Second image capture device

11c: Third Image Capture Device

11d: Dispersive confocal displacement sensing device

12: Processing device

13: Carrier device

14: Mobile devices

15: Light source device

A1: Area 1

A2: Second Area

A3: Third Area

A20: Area 20

C: Circuit diagram

C10: Side surface

D: Sidewall width when viewed from above

E: Abnormal Mark

H: Line height

M ₁ (X ₁ ,Y ₁ ,Z ₁ ),M _n (X _n ,Y _n ,Z _n ),M _N (X _N ,Y _N ,Z _N ): coordinates

S:Substrate

S1: First substrate

S2: Second substrate

S3: Third substrate

S20: 20th substrate

SA1, SA2, SA3, SA8, SAn: First sub-area

W1: Upper line width

W2: Lower line width

W3: Sidewall width

θ: Indentation angle

The following detailed description, combined with the accompanying drawings, will provide a better understanding of the presently disclosed embodiments. It should be noted that, in accordance with standard industry practice, some features may not be drawn to scale. In fact, the dimensions of various components may be increased or decreased for clarity of description.

FIG1 is a block diagram of an etching analysis system according to some embodiments of the present disclosure; FIG2 is a schematic diagram of an etching analysis system according to some embodiments of the present disclosure; FIG3 is a three-dimensional schematic diagram of an electronic component according to some embodiments of the present disclosure; FIG4 is a three-dimensional schematic diagram of an electronic component according to other embodiments of the present disclosure; FIG5 is a flow chart of an etching analysis method according to some embodiments of the present disclosure; FIG6 is a top view schematic diagram of an electronic component according to some embodiments of the present disclosure; FIG7 is a flow chart of an electronic component according to some embodiments of the present disclosure FIG8 is a schematic side view of an electronic component according to some embodiments of the present disclosure; FIG9 is a schematic diagram showing the partitioning of an electronic component according to some embodiments of the present disclosure; FIG10 is a schematic diagram showing abnormality marking of an electronic component according to some embodiments of the present disclosure; FIG11 is a schematic diagram showing the analysis of an electronic component according to some embodiments of the present disclosure; FIG12 is a schematic diagram showing the partitioning of multiple electronic components according to other embodiments of the present disclosure; and FIG13 is a schematic diagram showing the analysis of an electronic component according to other embodiments of the present disclosure.

The following disclosure provides numerous different embodiments or examples for implementing the provided etching analysis system and etching analysis method. Specific examples of components and their configurations are described below to simplify the disclosed embodiments and are not intended to limit the disclosure. For example, a description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, as well as embodiments in which an additional component is formed between the first and second components, preventing direct contact. Furthermore, the disclosure may repeat reference numerals and/or characters across different embodiments or examples. This repetition is for simplicity and clarity and is not intended to indicate a relationship between the different embodiments and/or examples discussed.

Directional terms used herein, such as "up," "down," "left," "right," and similar terms, refer to directions in the drawings. Therefore, the directional terms used are intended to illustrate and not to limit this disclosure.

In some embodiments of the present disclosure, terms such as "disposed," "connected," and similar terms, unless otherwise specified, may refer to two components being in direct contact, or to two components being in indirect contact, with additional components located between the two structures. Terms such as "disposed," "connected," and similar terms may also include situations where both structures are movable or both structures are fixed.

Furthermore, the terms "first," "second," and similar terms mentioned in this specification or patent application are used to designate different components or to distinguish between different embodiments or scopes. They are not intended to limit the upper or lower limit on the number of components, nor are they intended to define the order in which the components may be manufactured or installed.

Hereinafter, "approximately," "substantially," or similar terms mean within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range of values. The quantities given herein are approximate quantities, meaning that even without the specific wording "approximately" or "substantially," the meaning of "approximately" or "substantially" is implied.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by one of ordinary skill in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the context of this disclosure.

This disclosure provides an etching analysis system and etching analysis method that, by analyzing circuit pattern images, effectively adjusts etching process operating parameters or circuit layout parameters, thereby improving the problems described in the prior art. It is worth noting that while the prior art uses electronic components that undergo a wet etching process as an example, this disclosure is not limited to this. In some embodiments, the etching analysis system and etching analysis method of this disclosure can also be used on electronic components that undergo a dry etching process, or on electronic components that undergo a hybrid process that includes both wet and dry etching processes, to improve the problems described in the prior art.

In some embodiments, the substrate of an electronic component may be or may include a polymer material, a fiber material, or other suitable materials, but the present disclosure is not limited thereto. For example, the polymer material may be or may include epoxy resin, polyimide (PI), polypropylene (PP), other suitable polymer materials, or combinations thereof. For example, the fiber material may be or may include carbon fiber, glass fiber, other suitable fiber materials, or combinations thereof. In some embodiments, the substrate of an electronic component may be a printed circuit board (PCB), a flexible printed circuit (FPC), a ceramic substrate, or other types of boards on which various conductive traces can be etched. Furthermore, the substrate of an electronic component may be a wafer, but the present disclosure is not limited thereto.

In some embodiments, the circuit pattern of the electronic component may be or include a conductive material. For example, the conductive material may be or include a metal, a metal compound, other suitable conductive materials, or a combination thereof, but the present disclosure is not limited thereto. For example, the metal may be or include tin (Sn), copper (Cu), gold (Au), silver (Ag), nickel (Ni), indium (In), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), molybdenum (Mo), titanium (Ti), magnesium (Mg), zinc (Zn), germanium (Ge), or alloys thereof. For example, the metal compound may be or may include tungsten nitride (TaN), titanium nitride (TiN), tungsten silicide (WSi2), indium tin oxide (ITO), etc.

Next, some embodiments of the etching analysis system and etching analysis method disclosed herein will be described with reference to Figures 1 to 3 to provide a clearer and easier understanding of the present disclosure. Figures 1 and 2 are, respectively, a block diagram and a schematic diagram of the etching analysis system, and Figure 3 is a schematic three-dimensional diagram of an electronic component.

As shown in Figure 1, the etching analysis system 1 includes a measurement device 11, a processing device 12, a carrier device 13, a moving device 14, and a light source device 15. The processing device 12 is electrically connected to the measurement device 11, carrier device 13, moving device 14, and light source device 15 to control these devices to perform etching analysis on a circuit pattern of an electronic component. For ease of understanding, the following uses a substrate S and a circuit pattern C thereon, as shown in Figures 2 and 3, as an example of etching analysis. Circuit pattern C is the remaining conductive layer after the etching process, protruding from the surface of substrate S. In some embodiments, the cross-section of circuit pattern C may have a trapezoidal shape. In other words, the width of the top surface of the circuit pattern C (i.e., the upper line width) can be smaller than the width of the bottom surface (i.e., the lower line width).

As shown in Figure 2, in some embodiments, the measurement device 11 includes a first image capture device 11a and a second image capture device 11b. The first image capture device 11a is configured to measure a first area A1 of a substrate S to obtain a first overhead image corresponding to the first area A1. For example, the first image capture device 11a can be positioned directly above the substrate S and capture the first area A1 of the substrate S vertically to obtain the first overhead image. It is worth noting that the term "directly above" as used herein includes an error range that does not affect image accuracy or an error range that can be corrected through image processing.

As shown in FIG3 , in some embodiments, the size (e.g., area) of the first area A1 may be the same as the size (e.g., area of the top surface) of the substrate S. In other words, in these embodiments, the first image capture device 11a may capture the entire surface of the substrate S to obtain a first top-view image corresponding to the entire substrate S. However, the present disclosure is not limited to this. In other embodiments, the size of the first area A1 may be smaller than the size of the substrate S. In other words, in these embodiments, the first image capture device 11a may capture only a portion of the substrate S (e.g., the center region) where the circuit pattern C is disposed, while avoiding other regions (e.g., the peripheral region) where the circuit pattern C is not disposed, to obtain a first top-view image corresponding to a portion of the substrate S surface. In this case, the information content (e.g., number of bits) of the first overhead image can be reduced, thereby improving the efficiency of subsequent image processing.

In some embodiments, the first image capture device 11a may include an optical lens and a photosensitive element coupled to the optical lens. For example, the optical lens may be or may include a telecentric lens, which allows the captured image to be unaffected by lens parallax within a certain physical distance while simultaneously achieving a wide depth of field. Alternatively, the optical lens may be a conventional lens, a wide-angle lens, a telephoto lens, a combination thereof, or other suitable lens, but the present disclosure is not limited thereto. For example, the photosensitive element may be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS), a combination thereof, or other suitable photosensitive element, but the present disclosure is not limited thereto.

As shown in Figure 2 , the second image capture device 11b is configured to measure a first area A1 of the substrate S at an angle to obtain a first side-view image corresponding to the substrate S. For example, the second image capture device 11b can be positioned diagonally above the substrate S (e.g., to one side of the first image capture device 11a ) and capture the first area A1 of the substrate S at an angle to obtain the first side-view image. In some embodiments, an angle θ is formed between the optical axis of the second image capture device 11b and the normal direction of the substrate S, where the angle θ can be greater than 0 degrees and less than or equal to 90 degrees. For example, the angle θ can be 10 degrees, 20 degrees, 30 degrees, 40 degrees, 50 degrees, 60 degrees, 70 degrees, 80 degrees, 90 degrees, or any value or range therebetween. In some embodiments, the optical axis of the second image capture device 11b can be substantially parallel to the normal direction of the side surface of the circuit pattern C, but the present disclosure is not limited thereto.

In some embodiments, the second image capture device 11b may include multiple second sub-image capture devices (not shown), each of which can measure the first area A1 at different angles (e.g., different angles of intersection θ) to obtain multiple first side-view images. For example, a second sub-image capture device can be placed on either side of the first image capture device 11a, or two second sub-image capture devices can be placed on the same side of the first image capture device 11a to obtain multiple first side-view images with different viewing angles. Acquiring multiple first side-view images with different viewing angles can enhance the accuracy of subsequent image processing and etching analysis.

In some embodiments, the second image capture device 11b or the second sub-image capture device may include an optical lens and a photosensitive element coupled to the optical lens. For example, the optical lens may be or may include a telecentric lens, a normal lens, a wide-angle lens, a telephoto lens, a combination thereof, or other suitable lens, but the present disclosure is not limited thereto. For example, the photosensitive element may be a photocoupler element or a complementary metal oxide semiconductor, a combination thereof, or other suitable photosensitive element, but the present disclosure is not limited thereto. In some embodiments, the first image capture device 11a may be similar or identical to the second image capture device 11b (or its second sub-image capture device), but the present disclosure is not limited thereto. For example, the first image capture device 11a and the second image capture device 11b may use different optical lenses or photosensitive elements based on the image requirements of the first and second overhead images.

It should be noted that the specific configuration of the measurement device 11 described above is merely an example and the present disclosure is not limited thereto. Any electronic device capable of measuring electronic components may be used in the present disclosure. For example, referring to FIG. 4 , which is a schematic perspective view of an electronic component according to other embodiments of the present disclosure, in some embodiments, the measurement device 11 includes a third image capture device 11c and a dispersive confocal shift sensing device 11d. The third image capture device 11c is configured to measure a first area A1 of the substrate S to obtain a top-view image corresponding to the first area A1. Since the third image capture device 11c may be similar or identical to the first image capture device 11a or the second image capture device 11b described above, further description thereof is omitted.

Meanwhile, the dispersive confocal shift sensing device 11d is positioned on one side of the third image capture device 11c and is used to acquire optical signals from the first area A1. Specifically, calculations can be performed on the optical signals to obtain information such as the thickness, height, and depth of the circuit pattern C. In some embodiments, the dispersive confocal shift sensing device 11d is positioned to measure the first area A1 from a top-down perspective (as shown in FIG. 4 ), but the present disclosure is not limited to this. In some embodiments, the dispersive confocal shift sensing device 11d can also be positioned on an inclined side (not shown) of the third image capture device 11c to measure the first area A1 from an inclined perspective, but the present disclosure is not limited to this.

Continuing with Figures 1 and 2 (or Figures 1 and 4), in some embodiments, in addition to controlling the measurement device 11, the carrier device 13, the moving device 14, and the light source device 15, the processing device 12 is further configured to generate measurement line information and to adjust operating parameters or line layout parameters of the etching device (not shown) based on the measurement line information. The measurement line information includes physical characteristics of the circuit pattern C, such as upper line width, lower line width, line height, line spacing, line volume, or three-dimensional line shape, but the present disclosure is not limited thereto. In some embodiments, the measurement line information may also include etching factor information, intensity distribution information, stability distribution information, and process capability index (CPK), but the present disclosure is not limited thereto. The specific operations used to generate measurement line information will be further described in the etching analysis method below. Here, only the possible configurations and functions of each device are described.

It is worth noting that in addition to the aforementioned implementation of the measurement device 11, in some embodiments, etched surface information can also be obtained through 3D scanning technology (such as time of flight (TOF), triangulation, stereo vision), etc., but the present disclosure is not limited thereto.

When one or more of the physical characteristics of the circuit pattern C, the etching factor information, the intensity distribution information, the stability distribution information, and the process capability index (CPK) in the measured circuit information do not meet the standards, the processing device 12 can adjust the etching device operating parameters or circuit layout parameters based on these physical characteristics or information. In other words, the present disclosure uses the processing device 12 to analyze the results of the current etching process and improve the next etching process based on these results.

In some embodiments, operating parameters for wet etching may include etchant type, etchant concentration, etchant volume, etching process temperature, etching process execution time, combinations thereof, or other suitable parameters; and for dry etching, may include gas composition, gas pressure, RF power, etching time, temperature, exhaust rate, combinations thereof, or other suitable parameters, but the present disclosure is not limited thereto. In some embodiments, the circuit layout may be presented as a digital file in engineering drawing software, and the circuit layout parameters may include the circuit pattern's upper line width, lower line width, line height, line spacing, material, combinations thereof, or other suitable parameters, but the present disclosure is not limited thereto.

In some embodiments, the processing device 12 may include processing and storage components such as a processor, computer-readable media, and memory to execute computer programs to implement the functions described above. Examples of processors may include a central processing unit (CPU), a multi-core CPU, a graphics processing unit (GPU), etc., but the present disclosure is not limited thereto. Examples of computer-readable media may include a compact disc read-only memory (CD-ROM), a hard drive, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc., but the present disclosure is not limited thereto. Examples of memory may include dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, etc., but the present disclosure is not limited thereto. It is worth noting that the term "computer program" as used herein refers to an application program stored in a computer-readable medium that can be read into a memory for processing by a processor. In some embodiments, the application program may be written in any combination of one or more programming languages. Programming languages include object-oriented programming languages such as Java, Smalltalk, C++, or similar languages, as well as traditional procedural programming languages such as C or similar programming languages.

As shown in Figure 2, the carrier device 13 is configured to transport an electronic component (e.g., a substrate S) having a first area A1 to a capture area of the measurement device 11. It is worth noting that the capture area refers to the area toward which the optical axis of the measurement device 11 points, i.e., the area where images are captured. For example, the carrier device 13 may include a transport assembly for transporting the electronic component (e.g., substrate S or other substrates), a clamping assembly or a suction assembly for securing the electronic component, or any combination thereof or any suitable assembly known to those skilled in the art, but the present disclosure is not limited thereto. Examples of the transport assembly include a conveyor belt, the clamping assembly include a robotic arm, and the suction assembly include a vacuum suction assembly.

As shown in Figure 2, the moving device 14 is physically connected to the measuring device 11 and is configured to adjust the sensing angle of the measuring device 11. Specifically, the moving device 14 can move, for example, the first image capture device 11a and the second image capture device 11b in Figure 2, or the third image capture device 11c and the dispersive confocal shift sensing device 11d in Figure 4. In some embodiments, the moving device 14 may include a clamping assembly or a suction assembly for securing the image capture device, and may include a horizontal movement assembly, a vertical movement assembly, or a combination thereof, but the present disclosure is not limited thereto. The clamping assembly may be a robotic arm, the suction assembly may be a vacuum suction assembly, and the horizontal and vertical movement assemblies may be electric slides.

As shown in Figure 2, a light source device 15 is disposed above the first area A1 of the substrate S to provide auxiliary illumination. In some embodiments, the light source device 15 may be a backlight, an annular light, a dome light, a parallel light, a diffuse light, a coaxial light assembly, a combination thereof, or other suitable light sources, but the present disclosure is not limited thereto. In some embodiments, providing multiple light source devices 15 can improve image capture efficiency. In some embodiments, a lighting switching controller connected to different types of light source devices 15 can be provided. By switching lighting modes and capturing images of the first area A1 of the substrate S under different environments, the contrast between features can be enhanced, thereby facilitating image capture or image segmentation of the captured area.

Referring also to FIG. 5 , a flowchart illustrating an etching analysis method according to some embodiments of the present disclosure is shown. First, an electronic component (i.e., substrate S) having a first area A1 is transported to the imaging area of a measurement device 11 by a carrier device 13 . The sensing position and angle of the measurement device 11 are then adjusted by a moving device 14 . It is worth noting that the moving device 14 can also continuously adjust the sensing position and angle of the measurement device 11 in subsequent steps to improve image capture accuracy.

Next, as shown in Figure 5 , in step S0 , the measurement device 11 measures the substrate S (e.g., photographs the substrate S) to obtain image information of a first area A1 of the substrate S. In some embodiments, as shown in Figure 2 , the image information may include a first top-view image and a first side-view image. In other embodiments, as shown in Figure 4 , the image information may include a top-view image and an optical signal of the first area A1. Continuing with the above, in step S2 , the processing device 12 generates measurement circuit information based on the image information. In step S4 , the processing device 12 adjusts operating parameters or circuit layout parameters of the etching device based on the measurement circuit information.

To provide a clearer understanding of steps S2 and S4, the image analysis operations for generating measurement circuit information using the first top-view image and the first side-view image in some embodiments shown in FIG. 2 will be described below with reference to FIG. 3 and FIG. 6 through FIG. 8 , respectively, show schematic top-view, side-view, and cross-sectional views of an electronic component according to some embodiments of the present disclosure.

In some embodiments, the image analysis operation includes obtaining physical feature information. As shown in FIG. 3 , in some embodiments, the circuit pattern C in the first area A1 is a long, trapezoidal structure. First, the starting point of the circuit pattern C is defined as having coordinates _M1 ( _X1 , _Y1 , _Z1 ), any point in the circuit pattern C is defined as having coordinates _Mn ( _Xn , _Yn , _Zn ), and the ending point of the circuit pattern C is defined as having coordinates _MN ( _XN , _YN , _ZN ).

Next, the first image capture device 11a captures a first top-view image (as shown in FIG. 6 ) directly above the electronic component. The processing device 12 defines the upper line width W1 and lower line width W2 of the circuit pattern C at the coordinates _Mn ( _Xn , _Yn , _Zn ) based on the first top-view image. In some embodiments, the top-view sidewall width D of the circuit pattern C at the coordinates _Mn ( _Xn , _Yn , _Zn ) can also be directly defined.

On the other hand, the second image capture device 11b captures a first side-view image, as shown in FIG. 7 , from an obliquely upper portion of the electronic component. The processing device 13 defines the sidewall width W3 of the circuit pattern C at coordinates _Mn ( _Xn , _Yn , _Zn ) based on the first side-view image. It is worth noting that, in this embodiment, because the optical axis of the second image capture device 11b is substantially parallel to the normal direction of the sidewall surface C10 of the circuit pattern C, only one sidewall surface C10 of the circuit pattern C can be observed from the first side-view image shown in FIG. Finally, as shown in Figure 8, after obtaining the top-view sidewall width D and sidewall width W3, the line height H can be obtained using the Pisces theorem (D ² +H ² =W3 ² ). In this way, the physical characteristic information of the circuit pattern C at the coordinates M _n (X _n ,Y _n ,Z _n ) can be obtained (for example, upper line width W1, lower line width W2, line height H, top-view sidewall width D, etc.).

In other embodiments, the line height H can be calculated using alternative methods. For example, when the angle θ between the optical axis of the second image capture device 11b and the normal to the substrate S is 90 degrees (i.e., the optical axis of the second image capture device 11b is parallel to the extension direction of the upper and lower surfaces of the substrate S), the line height H can be directly obtained from the first side view image without the need for calculation using the Pisces theorem.

It is worth noting that the image analysis operations described above are merely some embodiments of the present disclosure, intended to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. In other embodiments, image analysis operations different from those described above may be employed to achieve similar or identical functions. For example, in some embodiments shown in FIG. 4 , the processing device 12 may analyze the optical signal (and overhead image) captured by the dispersive confocal shift sensing device 11 d to directly obtain measurement line information (e.g., the height physical characteristics described above).

Continuing with the above, the processing device 12 can adjust the operating parameters or circuit layout parameters of the etching device based on the measured circuit information including the physical characteristic information. For example, the step of adjusting the operating parameters of the wet etching device may include adjusting the type of etching solution, the concentration of the etching solution, the volume of the etching solution, the temperature of the etching process, and the execution time of the etching process, etc., but the present disclosure is not limited to this. Adjusting the operating parameters of the dry etching apparatus may include selecting gas composition, adjusting gas pressure, adjusting RF power, adjusting etching time, temperature control, exhaust rate control, combinations thereof, or other suitable parameters, but the present disclosure is not limited thereto. For example, adjusting the line layout parameters of the etching apparatus may include adjusting the upper line width, lower line width, line height, line spacing, line volume, or three-dimensional line shape and material, but the present disclosure is not limited thereto.

In some embodiments, the image analysis operation further includes obtaining etch factor information. After obtaining the aforementioned physical feature information (i.e., upper line width W1, lower line width W2, top sidewall width D, and line height H), the etch factor is defined as line height H/top sidewall width D. In some embodiments, the etch factor may be between 1.2 and 1.8, but the present disclosure is not limited thereto. For example, the etch factor may be 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, or any value or range therebetween. In other words, in addition to intuitively determining whether the etching process meets expectations by measuring physical characteristics in the circuit information (for example, upper line width W1, lower line width W2, and sidewall width W3), the etching factor defined above can also be used to determine whether the etching process meets expectations.

In some embodiments, the cross-section of any location in the circuit pattern C may have an asymmetrical trapezoidal shape. Therefore, at that location, two etching factors may exist, one corresponding to each side. Therefore, the etching factor can alternatively be defined as line height H/(lower line width W2 - upper line width W1)/2) to obtain an average etching factor at that location. In other words, the image analysis step described above is merely an example and can be replaced or substituted with methods known to those skilled in the art.

Referring to Figures 9 through 11 , there are shown schematic diagrams illustrating electronic component segmentation, abnormal marking, and analysis, respectively, according to some embodiments of the present disclosure. As shown in Figure 9 , in some embodiments, the image analysis operation further includes obtaining full-panel intensity distribution information for substrate S. Substrate S comprises a plurality of first sub-areas SA1, SA2, ..., SAn, each containing the same circuit pattern. These first sub-areas SA1, SA2, ..., SAn will be further segmented during subsequent manufacturing processes. The measurement device 11 captures and processes the measured sub-line information for each first sub-area SA1, SA2, ..., SAn. The processing device 12 then compares the measured sub-line information for each first sub-area SA1, SA2, ..., SAn with a preset line information. If the difference between the two exceeds a threshold (e.g., 5% above or below the standard), it is considered abnormal and an abnormality mark E is displayed on the sub-area. In some embodiments, the measured sub-line information for each first sub-area can be line-related dimensions or etching factors, but the present disclosure is not limited to this. As the number of anomalies in the same first sub-area increases, the range of the anomaly marks in that first sub-area also increases. For example, in Figure 9, no anomalies occur in first sub-area SA3, while the number of anomalies in first sub-area SA8 is much greater than that in first sub-area SA26. Furthermore, in Figure 9, the number of anomalies in the upper half of substrate S is greater than that in the lower half. The distribution of anomalies can reveal the gradient of etch line anomalies, facilitating subsequent judgment and adjustment of various substrate process variables. In some embodiments, in addition to displaying the distribution of anomalies across the entire substrate S, the distribution of localized anomalies can also be displayed, thereby demonstrating the distribution trend of localized etching anomaly. The desired portion of substrate S to be displayed can be selected by the operator, but the present disclosure is not limited thereto.

Next, in some embodiments, as shown in FIG. 10 , when an abnormality mark E is displayed on any first sub-area (e.g., first sub-area SA1), an operator can select the first sub-area via a display device (not shown) connected to the processing device 12 to display the complete circuit diagram of the first sub-area. The distribution of the abnormality mark E will also be displayed on the complete circuit diagram of the first sub-area, allowing detailed identification of the defect location of the circuit.

Then, in some embodiments, as shown in FIG11 , statistics of the number or degree of non-compliance can also be presented in an analysis diagram via a display device (not shown) connected to the processing device 12.

As described above, after completing the full-plate etching analysis, the processing device 12 is further configured to adjust the operating parameters or circuit layout parameters of the etching device based on the intensity distribution information. For example, for locations with insufficient etching, the processing device 12 can increase the etching temperature and/or humidity in those locations to speed up the etching speed. Conversely, for locations with excessive etching, these parameters can be reduced to slow down the etching speed. Alternatively, the processing device 12 can increase the etchant concentration or etchant flow rate to address insufficient etching, or reduce these parameters to address excessive etching. For example, in some embodiments, the processing device 12 can adjust the nozzle pressure and/or direction to control the etchant spray velocity and distribution range, thereby improving the problem of uneven etching. For example, in some embodiments, the processing device 12 can adjust the stirring speed of the etchant, which also helps ensure uniform etching. For example, in some embodiments, the processing device 12 can adjust the etching time of the substrate S. The etching time is roughly proportional to the etching depth, thereby improving the problem of insufficient etching or excessive etching. For example, in some embodiments, the processing device 12 can adjust the size, shape, and material of the mask to adjust the etching effect by changing the contact range between the etchant and the substrate S. For example, in some embodiments, the processing device 12 can increase the contact time between the etching liquid and the substrate S, or increase the concentration and/or flow rate of the etching liquid, to solve the problem that the thickness of the substrate S body, the photoresist layer and/or the circuit layer exceeds the threshold value, thereby adjusting the etching effect; conversely, the processing device 12 can reduce the contact time between the etching liquid and the substrate S, or reduce the concentration and/or flow rate of the etching liquid, to solve the problem that the thickness of the substrate S body, the photoresist layer and/or the circuit layer is lower than the threshold value, thereby adjusting the etching effect. The above-mentioned process adjustment methods are merely examples of several methods to facilitate understanding of the present invention. The present invention is not limited to the above-mentioned embodiments, and the present invention does not intend to limit the number of process control variables that can be adjusted at one time. These are described here first.

In some embodiments, etching anomalies can be adjusted by changing circuit design parameters. For example, for locations with insufficient etching, the circuit can be designed to be narrower than the original size. This way, the expected size can be achieved under the same process parameters. Conversely, for locations with excessive etching, the circuit can be designed to be wider than the original size. This way, the expected size can be achieved under the same process parameters. The present disclosure is not limited to this.

Referring to Figures 12 and 13 , respectively, they illustrate a schematic diagram of the partitioning and analysis of multiple electronic components according to some embodiments of the present disclosure. As shown in these figures, in some embodiments, the image analysis operation further includes obtaining stability distribution information. For example, the etching process can be applied to batch-produced electronic components. Each batch of electronic components includes multiple substrates, such as a first substrate S1, a second substrate S2, a third substrate S3, ..., a twentieth substrate S20, and so on. In this case, the measuring device 11 is configured to measure the first area A1 of the first substrate S1, the second area A2 of the second substrate S2, the third area A3 of the third substrate S3, ..., and the twentieth area A20 of the twentieth substrate S20, etc., to obtain a first image corresponding to the first area A1, a second image corresponding to the second area A2, a third image corresponding to the third area A3, ..., and the twentieth image corresponding to the twentieth area A20, etc. The first area A1 of the first substrate S1 corresponds to the second area A2 of the second substrate S2, ..., and the twentieth area A20 of the twentieth substrate S20.

Next, an etch analysis operation as described above can be used to determine whether the line width or etch factor at corresponding locations within these regions (e.g., the center region) meets standards. When the line width or etch factor exceeds a threshold (e.g., exceeds or falls below the standard by 5%), the analysis results can be recorded in the memory of the processing device 12. In this way, etching stability at corresponding locations on different substrates can be confirmed by performing etch analysis on mass-produced electronic components. As shown in FIG13 , in some embodiments, a display device (not shown) connected to the processing device 12 can be used to display historical etch factor data in the form of a statistical chart within the analysis diagram.

Finally, the processing device 12 can generate stability distribution information based on the first measurement line information of the first substrate S1, the second measurement line information of the second substrate S2, and the third measurement line information of the third substrate S3. The operating parameters or circuit layout parameters used in the etching device can be adjusted based on the stability distribution information. The details and adjustment directions of the operating parameters and circuit layout parameters can be found above and will not be elaborated here. It is worth noting that while FIG. 12 only analyzes the stability distribution of the central region of each substrate, the present disclosure is not limited to this. In other embodiments, the stability distribution analysis can be performed on multiple regions of each substrate.

In some embodiments, operating parameters or circuit layout parameters of an etching device may be adjusted using both stability distribution information and intensity distribution information, but the present disclosure is not limited thereto. In some embodiments, the operating parameters or circuit layout parameters may be adjusted first based on the stability distribution information to ensure high stability of the etching process. Subsequently, the operating parameters or circuit layout parameters may be adjusted based on the intensity distribution information to ensure high precision of the etching process.

In some embodiments, the process capability index (CPK) can be calculated by the following formula:

Where USL is the upper specification limit for the selected line segment, LSL is the lower specification limit for the selected line segment, representing the maximum and minimum values allowed by the process, σ is the allowable standard deviation within the process, and μ is the average value of the measurement line information for the entire substrate S at a specific line segment. The unitless CPK value is calculated and used to assess process capability. A CPK value greater than or equal to 1.33 indicates good process capability, while a CPK value less than 1.33 indicates that the process requires improvement.

It is worth noting that the threshold for measuring circuit information is not limited to 5% and can be changed based on manufacturing requirements. Furthermore, when conducting the aforementioned etching intensity or stability analysis, the etching factor is not the only criterion used; other criteria may be used as needed.

It is worth noting that in some embodiments, the processing device 12 can be an artificial intelligence model that generates measurement circuit information after receiving images provided by the measurement device 11. The artificial intelligence also adjusts process control variables of the etching process and calculates the adjustment amounts for circuit design parameters. In some embodiments, the artificial intelligence model can be trained by providing images with etching defects and/or images without etching defects as a training set, and using process variables as annotations (for example, images with etching defects are annotated with the process parameters to be adjusted, while images without etching defects are left blank).

In some embodiments, the etching analysis system 1 can not only analyze and subsequently adjust the circuit patterns of electronic components, but also perform measurement and adjustment on etched holes. For example, after the measurement device 11 captures an image of the hole, the processing device 12 calculates hole information such as the upper hole diameter, lower hole diameter, hole depth, and hole tilt. In addition to detecting defects such as the hole bottom, hole wall, and hole tilt, the acquired hole information can also be used to adjust the etching process or hole design, but the present disclosure is not limited to this.

In summary, the disclosed etching analysis system and etching analysis method utilize imaging for non-contact inspection. This method is not affected by the size of electronic components, ensuring accuracy and convenience. Furthermore, the system and method can be applied to etching processes for a variety of electronic components, demonstrating a wide range of applications.

The above overview of several embodiments is provided to help those skilled in the art better understand the concepts of the disclosed embodiments. Those skilled in the art will appreciate that other processes and structures can be designed or modified based on the disclosed embodiments to achieve the same objectives and/or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent processes and structures do not depart from the spirit and scope of the disclosed embodiments, and that various modifications, substitutions, and replacements can be made without departing from the spirit and scope of the disclosed embodiments.

1: Etching Analysis System 11: Measurement Device 12: Processing Device 13: Carrier Device 14: Transport Device 15: Light Source Device

Claims (22)

An etch analysis system includes: a measurement device configured to measure a substrate and obtain image information of a first area of the substrate; and a processing device electrically connected to the measurement device and configured to generate measurement line information based on the image information, wherein the measurement line information includes an upper line width, a lower line width, a line height, and a top-view sidewall width. The processing device is further configured to generate etch factor information based on the upper line width, the lower line width, the line height, and the top-view sidewall width, and is configured to adjust an operating parameter or a line layout parameter for an etch device based on the etch factor information. The etch analysis system of claim 1, wherein the size of the first region is equal to or smaller than the size of the substrate. An etching analysis system as claimed in claim 1, wherein the substrate has a plurality of first sub-regions, and the measurement circuit information includes a plurality of measurement sub-circuit information corresponding to the first sub-regions, wherein the processing device is configured to generate intensity distribution information based on the measurement sub-circuit information, and the processing device is further configured to adjust the operating parameters or the circuit layout parameters used for the etching device based on the intensity distribution information. As in claim 3, the etching analysis system, wherein the processing device obtains a process capability index (CPK) based on the upper specification limit, the lower specification limit, the standard deviation allowed in the process of the selected line segments in all the first sub-areas, and the average value in the measurement sub-line information. An etching analysis system as claimed in claim 1, wherein the measurement device is configured to measure a plurality of substrates and obtain a plurality of image information from corresponding areas of the substrates, wherein the processing device is further configured to generate a plurality of measurement line information based on the image information and to generate stability distribution information based on the measurement line information, wherein the processing device is further configured to adjust the operating parameters or the line layout parameters used for the etching device based on the stability distribution information. The etching analysis system of claim 5, wherein the stability distribution information is displayed in the form of a statistical graph. The etching analysis system of claim 1, wherein the operating parameters of the etching device include the type of etching solution, the concentration of the etching solution, the volume of the etching solution, the temperature of the etching process, the execution time of the etching process, the gas composition, the gas pressure, the RF power, the etching time, and the exhaust rate. The etching analysis system of claim 1, wherein the line layout parameters of the etching device include upper line width, lower line width, line height, line spacing and material. The etching analysis system of claim 1, wherein the measurement device includes: a first image capture device for obtaining a first overhead image of the first area; and a second image capture device for obtaining a first side view image of the first area; wherein the processing device generates the measurement line information based on the first overhead image and the first side view image. The etching analysis system of claim 1, wherein the measurement device includes: a third image capture device for obtaining a top-view image of the first area; and a dispersive confocal shift sensing device, disposed on one side of the third image capture device and used to obtain a light wave signal of the first area; wherein the processing device generates the measurement line information based on the top-view image and the light wave signal. The etching analysis system of claim 1, wherein the processing device is an artificial intelligence model, and the artificial intelligence model generates the measurement circuit information by artificial intelligence, and adjusts the operating parameters or the circuit layout parameters of the etching device by artificial intelligence. An etch analysis method includes: measuring a substrate using a metrology device to obtain image information of a first area of the substrate; generating measurement circuit information using a processing device based on the image information, wherein the measurement circuit information includes an upper line width, a lower line width, a line height, and a top-view sidewall width; generating etch factor information using the processing device based on the upper line width, the lower line width, the line height, and the top-view sidewall width; and adjusting an operating parameter or a circuit layout parameter of an etch device using the processing device based on the etch factor information. The etching analysis method of claim 12, wherein the size of the first region is equal to or smaller than the size of the substrate. An etching analysis method as claimed in claim 12, wherein the substrate has a plurality of first sub-regions, the measurement circuit information includes a plurality of measurement sub-circuit information corresponding to the first sub-regions, and the etching analysis method further includes: generating intensity distribution information based on the measurement sub-circuit information by the processing device; and adjusting the operating parameters or the circuit layout parameters used for the etching device based on the intensity distribution information by the processing device. The etching analysis method of claim 14 further includes: obtaining a process capability index (CPK) by the processing device based on the upper specification limit, the lower specification limit, the standard deviation allowed in the process of the selected line segments in all the first sub-areas, and the average value in the measurement sub-line information. The etching analysis method of claim 12 further includes: measuring a plurality of substrates by the measurement device and obtaining a plurality of image information from corresponding areas of the substrates; generating a plurality of measurement line information based on the image information by the processing device; generating stability distribution information based on the measurement line information by the processing device; and adjusting the operating parameters or the line layout parameters used for the etching device by the processing device based on the stability distribution information. The etching analysis method of claim 16, wherein the stability distribution information is displayed in the form of a statistical graph. The etching analysis method of claim 12, wherein the step of adjusting the operating parameters used for the etching device includes: adjusting the type of etching solution, the concentration of the etching solution, the volume of the etching solution, the temperature of the etching process, the execution time of the etching process, the gas composition, the gas pressure, the RF power, the etching time and the exhaust rate in the operating parameters. The etching analysis method of claim 12, wherein the step of adjusting the circuit layout parameters used for the etching device includes: adjusting the upper line width, lower line width, line height, line spacing and material of the circuit layout parameters. The etching analysis method of claim 12, wherein the step of obtaining the image information by the measuring device includes: obtaining a first overhead image of the first area by a first image capture device in the measuring device, and obtaining a first side image of the first area by a second image capture device in the measuring device, wherein the step of generating the measurement line information by the processing device includes: generating the measurement line information by the processing device based on the first overhead image and the first side image. The etching analysis method of claim 12, wherein the step of obtaining the image information by the measuring device includes: obtaining a top-view image of the first area by a third image capture device in the measuring device, and obtaining a light wave signal of the first area by a dispersive confocal shift sensing device in the measuring device, wherein the step of generating the measurement line information by the processing device includes: generating the measurement line information by the processing device based on the top-view image and the light wave signal. The etching analysis method of claim 12, wherein the processing device is an artificial intelligence model, and the artificial intelligence model generates the measurement circuit information by artificial intelligence, and adjusts the operating parameters or the circuit layout parameters of the etching device by artificial intelligence.