TWI898962B - Chip pin configuration system and method thereof - Google Patents

Abstract

A chip pin configuration system comprises: a generative artificial intelligence module, an artificial intelligence agent module and a tool program module. The prompt interface of the generative artificial intelligence module is used to input the application scenario or pin configuration template of the chip, and a retrieval-augmented generation model of the generative artificial intelligence module is used to generate the pin configuration code of the chip. A chip pin configuration method includes the following steps: inputting application scenarios; analyzing peripheral resources; pin configuration; clock configuration; conflict analysis; generating pin configuration code; and generating pin configuration files.

Description

Chip pin configuration system and method

The present invention relates to a chip pin configuration system and method, and more particularly to a system and method for automatically generating pin configurations using generative artificial intelligence.

A system on chip (SoC) typically contains hundreds of pins and dozens of peripheral functions. Currently, the pin configuration of the chip's pin multiplexer (Pinmux) still relies on the engineer's expertise and experience to manually configure each pin on the chip. However, the chip's specification documents are numerous pages long, detailing the details of various peripheral functions. Engineers need to spend a lot of effort to understand and apply these pin configuration specifications, causing the system development cycle to be as long as several months. In addition, due to the diversity of peripheral functions and the need to consider conflicting factors such as multiplexing restrictions, manual pin configuration is prone to errors and difficult to achieve optimal configuration, which may affect development efficiency and quality.

System-on-a-chip (SoC) applications can be applied in a variety of scenarios, each with distinct requirements for pin configuration and peripheral functionality. However, traditional Pinmux configuration methods rely primarily on manual operation. Although some pin multiplexer design tools (e.g., automated Pinmux configuration tools) exist to assist engineers with pin configuration, these tools still cannot fully meet the diverse chip application requirements of using the same chip in multiple application scenarios. Therefore, there is an urgent need for an efficient automated tool that can quickly generate pin configuration solutions for different application scenarios, thereby significantly improving system development efficiency and accuracy.

One embodiment of the present invention provides a chip pin configuration system, comprising: a generative artificial intelligence module, an artificial intelligence agent module and a tool program module. The generative artificial intelligence module comprises a retrieval enhancement generation model and a prompt interface. The prompt interface is used to guide the user to input the application scenario of the chip or input the pin configuration template of the chip. The retrieval enhancement generation model is used to generate the pin configuration code of the chip. In addition, the artificial intelligence agent module comprises an artificial intelligence agent, the artificial intelligence agent module is used to use the generative artificial intelligence module to generate a task plan that meets the application scenario of the chip, and the artificial intelligence agent executes a plurality of tasks in the task plan. In addition, the tool program module is used to provide a plurality of application program interfaces for the artificial intelligence agent to call. Among them, a plurality of tasks correspond to a plurality of application program interfaces, and the artificial intelligence agent executes the corresponding tasks by calling the application program interface.

One embodiment of the present invention provides a chip pin configuration method, comprising: a generative artificial intelligence module providing a prompt interface to guide a user to input a chip application scenario or a chip pin configuration template so that the retrieval-enhanced generation model of the generative artificial intelligence module generates a chip pin configuration code; an artificial intelligence agent module generates a task plan that conforms to the chip application scenario through the generative artificial intelligence module, and an artificial intelligence agent of the artificial intelligence agent module executes a plurality of tasks in the task plan; and a tool program module provides a plurality of application program interfaces for the artificial intelligence agent to call, wherein a plurality of tasks correspond to a plurality of application program interfaces, and the artificial intelligence agent executes the corresponding tasks by calling the application program interfaces.

One embodiment of the present invention provides a chip pin configuration method, comprising the following steps, which are collaboratively processed by a generative artificial intelligence module, an artificial intelligence agent module, and/or a tool module: inputting an application scenario; analyzing peripheral resources; pin configuration; clock configuration; conflict analysis; generating pin configuration code; and generating a pin configuration file.

One embodiment of the present invention provides a chip pin configuration method, comprising the following steps: pin configuration labeling; collaborative operation of a generative artificial intelligence module and an artificial intelligence agent module; generating a pin configuration; verifying the pin configuration; evaluating an optimal pin configuration; and obtaining a pin configuration template.

1 , which illustrates a block diagram of a chip pin configuration system 100 according to an embodiment of the present invention. In the embodiment shown in FIG1 , the chip pin configuration system 100 includes a generative artificial intelligence module 110 , an artificial intelligence agent module 120 , and a tool module 130 .

In the embodiment shown in FIG1 , the chip pin configuration system 100 includes a generative artificial intelligence module 110. The generative artificial intelligence module 110 includes a large language model (LLM) and a retrieval-augmented generation model (RAG). Furthermore, the generative artificial intelligence module 110 includes a prompt interface for providing a user with prompt words to input. In one embodiment, the prompt interface of the generative artificial intelligence module 110 can guide the user to input the application scenario of the chip, for example, providing relevant prompt words to assist the user in selecting and customizing the application scenario of the chip. In one embodiment, the prompt interface of the generative artificial intelligence module 110 can also input a chip pin configuration template, with different pin configuration templates corresponding to different chip application scenarios (for example, industrial gateways, drones, collaborative robots, autonomous mobile robots, etc.). In addition, the retrieval-enhanced generation model of the generative artificial intelligence module 110 can search the expert knowledge base to improve the accuracy of the results generated by the generative artificial intelligence module 110. The expert knowledge base contains technical information related to the chip. The data sources of the expert knowledge base include: chip design documents (such as data sheets and technical manuals), code templates (such as .c and .dts files), and design constraints (such as pin voltage and clock requirements). After data processing, these data sources can be converted into structured data or vector data and stored in a relational database or a vector database. In addition, the generative artificial intelligence module 110 uses the retrieval-enhanced generation model to assist the large language model in generating the pin configuration code of the chip. These codes include C language code and device tree source code (Device Tree Source) formats.

In the embodiment shown in FIG1 , the chip pin configuration system 100 includes an artificial intelligence agent module 120. The artificial intelligence agent module 120 includes an artificial intelligence agent. The artificial intelligence agent generates a task plan that conforms to the chip's application scenario through the large language model of the generative artificial intelligence module 110. Modern chips, such as microcontrollers or system-on-chips (SoCs), can be set with different pin configurations to suit different application scenarios (e.g., industrial gateways, drones, collaborative robots, autonomous mobile robots, etc.). The number of physical pins on a chip is often limited, but these pins are defined during design to support a variety of candidate functions (e.g., GPIO, UART, SPI, I2C, etc.). By using a pin multiplexer (Pinmux), a specific function can be assigned to each pin from a variety of candidate functions, allowing the same chip to meet the needs of different application scenarios. For example, when the application scenario is a four-axis drone, the chip needs to be configured to include four sets of pulse width modulation (PWM) pin configurations to be able to adjust the speeds of four motors. When the application scenario is a six-axis drone, the chip needs to be configured to include six sets of pulse width pin configurations to be able to adjust the speeds of six motors. In addition, artificial intelligence agents can decompose the task planning of the chip application scenario generated by large language models into multiple tasks, and the artificial intelligence agent can execute multiple tasks. In one embodiment, the plurality of tasks include pin configuration, clock configuration, and conflict analysis, etc. Then, the artificial intelligence agent can execute the plurality of tasks separately or sequentially to generate pin configuration code that meets the application scenario of the chip.

In the embodiment shown in FIG1 , the chip pin configuration system 100 includes a tool module 130 . The tool module 130 includes a plurality of application programming interfaces (APIs) for providing a plurality of APIs for an artificial intelligence agent to call. The artificial intelligence agent calls the plurality of APIs through function calls. The plurality of APIs include an automatic test API 131, a programming API 132, and a program checking API 133. The automatic test API 131 is used to automatically generate chip application scenarios as a prompt interface for the generative artificial intelligence module 110. The programming API 132 is used to generate pin configuration code. The program checker API 133 is used to check the correctness of the script configuration code. Furthermore, the program checker API 133 includes a parser and a compiler, which are used to check the correctness of the script configuration code. Furthermore, multiple tasks correspond to multiple APIs, and the artificial intelligence agent executes the corresponding tasks by calling the APIs.

In addition, the tool module 130 provides a REST API service. The REST API is an HTTP-based communication protocol for standardized data exchange. Artificial intelligence agents can send requests to an application programming interface (API) using HTTP methods (e.g., GET and POST) and receive responses. The REST API can be used to connect large language models, search-enhanced generative models, artificial intelligence agents, and multiple APIs within the tool module 130.

In one embodiment, the REST API services provided by the tool module 130 include: configuration wizard (pinmux-wiz), configuration generation (pinmux-gen), configuration clock (pinmux-clock), and configuration validation (pinmux-validate). The artificial intelligence agent calls the configuration wizard (pinmux-wiz) through a function call to guide the user to perform pin configuration. The artificial intelligence agent calls the configuration generation (pinmux-gen) through a function call to generate corresponding code or configuration files based on the pin configuration. The artificial intelligence agent calls the configuration clock (pinmux-clock) through a function call to process the pin configuration and the clock parameter configuration of peripheral functions to ensure that the clock requirements of peripheral resources (such as UART or SPI) can operate normally. The AI agent invokes configuration validation (pinmux-validate) through a function call to verify that the pin configuration complies with the specifications and check for resource conflicts and incompatibilities.

Please refer to Figure 2, which illustrates a flow chart of a first embodiment of a chip pin configuration method 200 according to one embodiment of the present invention. In the embodiment shown in Figure 2, the chip pin configuration method 200 includes the following steps: inputting an application scenario (step S201); analyzing peripheral resources (step S202); pin configuration (step S203); clock configuration (step S204); conflict analysis (step S205); generating pin configuration code (step S206); and generating a pin configuration file (step S207).

In one embodiment, the chip pin configuration method 200 includes: inputting a chip application scenario or pin configuration template through a prompt interface of the generative artificial intelligence module 110 (step S201); the generative artificial intelligence module 110 determines the peripheral resources of the chip required for the application scenario (step S202); the generative artificial intelligence module 110 performs pin configuration based on the peripheral resources of the chip required for the application scenario (step S203); and performing pin configuration. After the pin configuration is completed, the generative artificial intelligence module 110 performs clock configuration (step S204). After the clock configuration is completed, the generative artificial intelligence module 110 performs conflict analysis (step S205). After the conflict analysis is completed, the generative artificial intelligence module 110 generates pin configuration code (step S206). After the pin configuration code is generated, the generative artificial intelligence module 110 generates a pin configuration file (step S207).

In step S201, the prompt interface of the generative AI module 110 can guide the user to input the chip's application scenario. For example, relevant prompts can be provided to assist the user in selecting and customizing the chip's application scenario. Furthermore, the prompt interface of the generative AI module 110 can also input a pin configuration template for the chip. Because chips can be applied to a variety of application scenarios, different pin configuration templates can be provided as input content in the prompt interface of the generative AI module 110 to reduce the number of dialogues. Furthermore, the AI agent can call a configuration wizard (pinmux-wiz) to guide the user in pin configuration.

In step S202, since the chip contains a variety of peripheral resources, common peripheral resources (or peripheral functions) include: communication interfaces (such as UART, SPI, I2C, USB, etc.), digital I/O interfaces (such as GPIO), control modules (such as PWM), etc. Taking a drone as an example, the chip's required peripheral resources may include: UART for communicating with the GPS module; SPI for connecting to the camera module; I2C for reading data from sensors such as accelerometers and gyroscopes; USB for connecting to external storage devices; GPIO for controlling LEDs; and PWM for controlling motor speed. According to the application scenario of the chip, the retrieval-enhanced generation model of the generative artificial intelligence module 110 can analyze peripheral resources based on the expert knowledge base to determine the peripheral resources required for the application scenario of the chip, laying the foundation for the footprint configuration.

In step S203, the chip's pins can be assigned to a specific peripheral function. Modern chips include multiplexed pins. Some pins in the chip can support multiple functions (e.g., GPIO, UART, I2C), but can only be assigned to one peripheral function at a time. After determining the chip's application scenario and the required peripheral resources, the retrieval-enhanced generation model of the generative artificial intelligence module 110 can perform pin configuration based on the expert knowledge base and optimize the pin configuration according to certain pin configuration principles to avoid resource conflicts. Pin configuration principles, for example, high-priority peripherals can be configured first; multiplexed pins should not be configured to multiple peripheral functions at the same time; dedicated clock sources should be configured; or related functions should be configured to the same pin group to reduce the complexity of cross-area wiring, etc.

In step S204, after pin configuration, the search-enhanced generation model of the generative AI module 110 can perform clock configuration based on the expert knowledge base, ensuring that each peripheral resource operates under the correct clock parameters. Clock configurations include, for example, the baud rate of UART communication, the clock frequency of SPI transmission, or the frequency and duty cycle of PWM control signals. Furthermore, the AI agent can call the configured clock (pinmux-clock) to ensure that the peripheral resource's clock requirements are met.

In step S205, after clock configuration, the search-enhanced generation model of the generative AI module 110 can perform conflict analysis based on the expert knowledge base to check whether the pin configuration complies with specifications or whether there are any resource conflicts. Resource conflicts include, for example, multiplex pin configuration conflicts, clock parameter conflicts, and electrical specification violations. Furthermore, the AI agent can call configuration validation (pinmux-validate) to verify whether the pin configuration complies with specifications or whether there are any resource conflicts.

In step S206, after performing the conflict analysis, if the pin configuration is verified to be compliant with the specification, the search-enhanced generation model of the generative artificial intelligence module 110 can generate the pin configuration code based on the expert knowledge base. In one embodiment, if the pin configuration does not meet the specification or there is a resource conflict, the generative artificial intelligence module 110 will prompt the user or automatically regenerate a new pin configuration. In addition, the artificial intelligence agent can call configuration generation (pinmux-gen) to generate corresponding code (e.g., .c source code and .dts source code, etc.) based on the pin configuration for developers to use in firmware or driver development.

In step S207, after generating the pin configuration code, the search-enhanced generation model of the generative AI module 110 can generate pin configuration files based on the expert knowledge base. These pin configuration files include: 1. C source code file (.c): Contains the pin configuration code for integration into the chip driver or system initialization code. 2. Header file (.h): Provides hardware configuration parameters and settings, structure definitions, and functions in the .c code. 3. Device tree source code (.dts): Describes the chip's hardware structure and resource configuration, such as clock, power, and pin function mapping. The device tree source code can be compiled into a binary format for Linux to load at boot time to initialize the hardware. 4. Pin Summary (.csv): Lists the function, status, and usage of each pin in a table format, serving as a reference document for configuration design.

Furthermore, these pin configuration files can be used as pin configuration templates to adapt to specific chip application scenarios. In one embodiment, the pin configuration templates can be input into the prompt interface of the generative AI module 110, which then interprets them to reduce the number of dialogues and errors. Furthermore, the collaborative operation of the generative AI module 110 and the AI agent module 120 can achieve the goal of automating the chip's pin configuration and automatically generating pin configuration code, thereby shortening development time.

Please refer to Figure 3, which shows a flow chart of a second embodiment of a chip pin configuration method 300 according to one embodiment of the present invention. In the embodiment shown in Figure 3, the chip pin configuration method 300 includes the following steps: pin configuration labeling (step S301); collaborative operation of the generative artificial intelligence module 110 and the artificial intelligence agent module 120 (step S302); generating a pin configuration (step S303); verifying the pin configuration (step S304); evaluating the optimal pin configuration (step S305); and obtaining a pin configuration template (step S306).

In step S301, the pin configuration is marked. The pin configuration of the chip is converted into a marked string representation so that the large language model of the generative artificial intelligence module 110 can more easily process and generate the pin configuration. For example, a standardized syntax structure is used to represent the pin configuration. Standardized syntax structures, such as JSON, XML, YAML, etc. Pin configuration, for example: PIN0: GPIO, PIN1: UART, PIN2: I2C, etc. In one embodiment, Digital Twins Definition Language (DTFL) can be used to define peripheral devices, pin layout and clock configuration.

In step S302, the generative AI module 110 and the AI agent module 120 operate in collaboration. The generative AI module 110 includes a large language model and a retrieval-enhanced generative model, while the AI agent module 120 includes an AI agent. The AI agent uses the large language model of the generative AI module 110 to generate a task plan that matches the chip's application scenario. The AI agent breaks the task plan into a plurality of tasks and executes the plurality of tasks. In one embodiment, the plurality of tasks includes generating and verifying a footprint configuration.

In step S303, the pin configuration is generated. The search-enhanced generative model of the generative AI module 110 can perform pin configuration based on the expert knowledge base. In one embodiment, step S303 includes the steps of the generative AI module 110 performing clock configuration and generating pin configuration code. In addition, the AI agent can call the configuration wizard (pinmux-wiz), configuration generation (pinmux-gen), and configuration clock (pinmux-clock) to generate the pin configuration.

In step S304, the pin configuration is validated. The search-enhanced generation model of the generative AI module 110 can validate the pin configuration and the pin configuration code based on the expert knowledge base to verify whether the pin configuration complies with the specifications or whether there are any resource conflicts. Additionally, the AI agent can call the pinmux-validate function to verify whether the pin configuration has any resource conflicts.

In step S305, the best pin configuration is evaluated. In one embodiment, multiple pin configurations can be generated, and the performance of each pin configuration can be evaluated to retain the top three pin configurations. The user can adjust the ranking of the pin configurations to determine the best pin configuration. The evaluation principles include: layout/routing efficiency, signal integrity, power consumption, etc. In addition, the retrieval-enhanced generation model of the generative artificial intelligence module 110 can perform multiple rounds of configuration optimization based on the expert knowledge base to generate the best pin configuration. In one embodiment, when the evaluation is not the best pin configuration, the process returns to step S302 to regenerate a pin configuration; when the evaluation is the best pin configuration, the process executes step S306.

In step S306, a footprint template is obtained. After obtaining the optimal footprint, the search-enhanced generation model of the generative artificial intelligence module 110 can generate a footprint file based on the expert knowledge base, including: C source code files, header files, device tree source code, and footprint summary. These footprint files can be used as footprint templates for the chip.

Please refer to Figure 4, which shows a flow chart of a third embodiment of a chip pin configuration method 400 according to an embodiment of the present invention. In the embodiment shown in Figure 4, the chip pin configuration method 400 includes steps S401-S403.

In step S401 , the generative artificial intelligence module 110 provides a prompt interface to guide the user to input the application scenario of the chip or input the pin configuration template of the chip so that the retrieval-enhanced generation model of the generative artificial intelligence module 110 generates the pin configuration code of the chip.

In step S402 , the artificial intelligence agent module 120 generates a task plan that meets the application scenario of the chip through the generative artificial intelligence module 110 , and the artificial intelligence agent of the artificial intelligence agent module 120 executes a plurality of tasks in the task plan.

In step S403, the tool module 130 provides a plurality of application programming interfaces (APIs) for the artificial intelligence agent to call, wherein a plurality of tasks correspond to a plurality of APIs, and the artificial intelligence agent executes the corresponding tasks by calling the APIs.

In one embodiment, the artificial intelligence agent can call multiple application programming interfaces (APIs) through function calls. The multiple APIs include an automatic testing API 131, a programming API 132, and a program checking API 133. The automatic testing API 131 is used to automatically generate a chip application scenario as a prompt interface for the generative artificial intelligence module 110. The programming API 132 is used to generate the pin configuration code. The program checking API 133 is used to check the correctness of the pin configuration code. In addition, the program checking API 133 includes a parser and a compiler, which are used to check the pin configuration code.

In one embodiment, the AI agent can invoke a pin configuration tool, such as the Pinmux tool, through a function call. The Pinmux tool includes a configuration wizard (pinmux-wiz), configuration generation (pinmux-gen), configuration clock (pinmux-clock), and configuration validation (pinmux-validate). In one embodiment, the pin configuration tool can be an application programming interface, a program module, or a utility program.

In one embodiment, when generating footprint code, the search-enhanced generative model of the generative AI module 110 can generate footprint files based on an expert knowledge base, including C source code files, header files, device tree source code, and footprint summaries. These footprint files can serve as footprint templates for the chip. Furthermore, these footprint templates can be input into the prompt interface of the generative AI module 110 for parsing, thereby reducing the number of dialogues and errors.

Although the present invention has been disclosed above by way of embodiments, they are not intended to limit the present invention. Any person having ordinary skill in the art may make slight modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Chip Pin Assignment System 110: Generative AI Module 120: Artificial Intelligence Agent Module 130: Tool Programming Module 131: Automatic Testing API 132: Programming API 133: Program Checking API 200, 300, 400: Chip Pin Assignment Method S201-S207, S301-S306, S401-S403: Steps

Figure 1 is a block diagram of a chip pin allocation system according to an embodiment of the present invention. Figure 2 is a flow chart of a first embodiment of a chip pin allocation method according to an embodiment of the present invention. Figure 3 is a flow chart of a second embodiment of a chip pin allocation method according to an embodiment of the present invention. Figure 4 is a flow chart of a third embodiment of a chip pin allocation method according to an embodiment of the present invention.

100: Chip pin configuration system

110: Generative Artificial Intelligence Module

120: Artificial Intelligence Agent Module

130: Utility Module

131:Automatically test the application programming interface

132: Programming Application Programming Interface

133: Program Check API

Claims (20)

A chip pin configuration system comprises: A generative artificial intelligence module comprising a retrieval-enhanced generative model, the generative artificial intelligence module providing a prompt interface to guide a user to input an application scenario for a chip or a pin configuration template for the chip, and using the retrieval-enhanced generative model to generate a pin configuration code for the chip; An artificial intelligence agent module comprising an artificial intelligence agent, the artificial intelligence agent module using the generative artificial intelligence module to generate a task plan that matches the application scenario for the chip, and the artificial intelligence agent executing a plurality of tasks in the task plan; and A tool module providing a plurality of application programming interfaces for the artificial intelligence agent to call; The plurality of tasks correspond to the plurality of application programming interfaces (APIs), and the artificial intelligence agent executes the corresponding tasks by calling the APIs. The chip pin configuration system as described in claim 1, wherein the generative artificial intelligence module includes an expert knowledge base, and the expert knowledge base includes technical information related to the chip. The chip pin configuration system of claim 1, wherein the generative artificial intelligence module generates a pin configuration file based on the pin configuration code. The chip pin configuration system as described in claim 3, wherein the pin configuration file includes a C source code file, a header file, a device tree source code and a pin summary. The chip pin configuration system as described in claim 3, wherein the pin configuration file can serve as the pin configuration template of the chip. A chip pin configuration system as described in claim 1, wherein the plurality of application program interfaces includes an automatic test application program interface, which is used to automatically generate the application scenario of the chip to the prompt interface of the generative artificial intelligence module. The chip pin configuration system as described in claim 1, wherein the plurality of application program interfaces includes a programming application program interface, and the programming application program interface is used to generate the pin configuration code. The chip pin configuration system as described in claim 1, wherein the plurality of application program interfaces includes a program check application program interface, which is used to check the correctness of the pin configuration code. A chip pin configuration system as described in claim 8, wherein the program check application program interface includes a parser and a compiler, and the parser and the compiler are used to check the pin configuration code. A chip pin configuration method comprises: (a) a generative artificial intelligence module provides a prompt interface to guide a user to input an application scenario for a chip or a pin configuration template for the chip, so that a retrieval-enhanced generative model of the generative artificial intelligence module generates a pin configuration code for the chip; (b) an artificial intelligence agent module generates a task plan that matches the application scenario for the chip through the generative artificial intelligence module, and an artificial intelligence agent of the artificial intelligence agent module executes a plurality of tasks in the task plan; and (c) a tool module provides a plurality of application programming interfaces (APIs) for the artificial intelligence agent to call; wherein, the plurality of tasks correspond to the plurality of APIs, and the artificial intelligence agent executes the corresponding tasks by calling the APIs. A chip pin configuration method as described in claim 10, wherein the generative artificial intelligence module includes an expert knowledge base, and the expert knowledge base includes technical information related to the chip. The chip pin configuration method of claim 10 further comprises: Generting a pin configuration file based on the pin configuration code by the generative artificial intelligence module. The chip pin configuration method as described in claim 12, wherein the pin configuration file includes a C source code file, a header file, a device tree source code and a pin summary. A chip pin configuration method as described in claim 12, wherein the pin configuration file can serve as the pin configuration template of the chip. The chip pin configuration method of claim 10, wherein the plurality of application program interfaces includes an automatic test application program interface, and step (c) comprises: The artificial intelligence agent automatically generates the application scenario of the chip for the prompt interface of the generative artificial intelligence module by calling the automatic test application program interface. The chip pin configuration method of claim 10, wherein the plurality of application program interfaces includes a programming application program interface, and step (c) comprises: The artificial intelligence agent generates the pin configuration code by calling the programming application program interface. The chip pin configuration method of claim 10, wherein the plurality of application program interfaces includes a program check application program interface, and step (c) comprises: The artificial intelligence agent checks the correctness of the pin configuration code by calling the program check application program interface. A chip pin configuration method as described in claim 17, wherein the program check application program interface includes a parser and a compiler, and the parser and the compiler are used to check the pin configuration code. A chip pin configuration method comprises: Inputting an application scenario or a pin configuration template for a chip through a prompt interface of a generative artificial intelligence module; The generative artificial intelligence module determines a peripheral resource of the chip required for the application scenario; Based on the peripheral resource of the chip required for the application scenario, the generative artificial intelligence module performs a pin configuration; After performing the pin configuration, the generative artificial intelligence module performs a clock configuration; After performing the clock configuration, the generative artificial intelligence module performs a conflict analysis; After performing the conflict analysis, the generative artificial intelligence module generates a pin configuration code; and After generating the pin configuration code, the generative artificial intelligence module generates a pin configuration file. A chip pin configuration method as described in claim 19, wherein the pin configuration file includes a C source code file, a header file, a device tree source code and a pin summary, and the pin configuration file can serve as the pin configuration template.