CN119203893A - Chip verification system based on code service layer - Google Patents
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Abstract
The invention relates to the technical field of chips, in particular to a chip verification system based on a code service layer, which comprises the code service layer, a software test library, a driving module, a conversion interface and a chip design to be tested, wherein the code service layer, the software test library, the driving module, the conversion interface and the chip design to be tested are sequentially connected, the code service layer and the software test library are realized based on software codes, the chip design to be tested is realized based on hardware codes, the conversion interface is realized based on the software codes and the hardware codes, the software test library comprises N software test library files { F 1,F2,...,Fn,...,FN }, wherein F n is an nth software test library file, the value range of N is 1 to N, the code service layer comprises a global function module, a command packet creation and distribution module, a queue wakeup module, a multi-process scheduling module and an operation result checking module, and each module of the code service layer is at least bound with one F n. The invention improves the generation efficiency of the software test case, thereby improving the chip verification efficiency.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a chip verification system based on a code service layer.
Background
In the process of chip verification, a software Test case needs to be generated based on a software Test library (Test library), and the chip design to be tested is verified based on interaction between the software Test case and the chip design to be tested. Different library files exist in the software test library, the requirements of different users for generating different test cases are also different, the number of the library files is large, the reusability of the library files is poor, the scheduling mechanism is lacked, parallelization and multiprocessing operations are difficult to realize, each user needs to select the library files according to specific application scenes, the efficiency of constructing the software test cases is low, and therefore the chip verification efficiency is low. Therefore, how to improve the generation efficiency of the software test case and further improve the chip verification efficiency is a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a chip verification system based on a code service layer, which improves the generation efficiency of software test cases and further improves the chip verification efficiency.
According to a first aspect of the invention, a chip verification system based on a code service layer is provided, comprising the code service layer, a software test library, a driving module, a conversion interface and a chip design to be tested, which are sequentially connected, wherein the code service layer and the software test library are realized based on software codes, the chip design to be tested is realized based on hardware codes, and the conversion interface is realized based on the software codes and the hardware codes;
The software test library comprises N software test library files { F 1,F2,...,Fn,...,FN }, wherein F n is an nth software test library file, and the value range of N is 1 to N;
The code service layer comprises a global function module, a command packet creation and distribution module, a queue wakeup module, a multi-process scheduling module and an operation result checking module, wherein each module of the code service layer is at least bound with one F n;
Each module of the code service layer is used for calling the bound F n to transmit corresponding functional instructions to the chip design to be tested through the driving module and the conversion interface;
The conversion interface is used for converting the function instruction realized by the software language issued by each module of the code service layer into the function instruction realized by the hardware language and sending the function instruction to the chip design to be tested;
The global function module is used for generating a preset function opening or closing instruction;
The command packet creation and distribution module is used for creating command packets and randomly mapping the command packets onto a single queue or a plurality of queues, or mapping each command packet onto a corresponding queue one by one according to a preset mapping relation, and distributing the command packets to the corresponding queues after the queues corresponding to the command packets are awakened;
The queue awakening module is used for awakening the queue through doorbell operation according to the execution sequence of the queue;
The multi-process scheduling module is used for setting at least one process, if the multi-process scheduling module is a plurality of processes, the plurality of processes are set to be executed in order or in parallel, a mapping relation between each process and a queue is constructed, a command packet corresponding to the chip design to be tested is executed in the queue through the corresponding process when the queue wakes up, and the chip design to be tested generates an execution result;
The operation result checking module is used for acquiring an execution result, comparing the execution result with a target result, and if the execution result is consistent with the target result, verifying to pass, otherwise, verifying to fail.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the chip verification system based on the code service layer can achieve quite technical progress and practicality, has wide industrial utilization value, and has at least the following beneficial effects:
according to the invention, the code service layer is constructed, the universal functional module is arranged, the functional module is well bound with the software test library file, and the user can generate the software test case by calling the functional module corresponding to the code service layer through simple parameter control, so that the generation efficiency of the software test case is improved, and the chip verification efficiency is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a chip verification system based on a code service layer according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a chip verification system based on a code service layer, which is shown in figure 1 and comprises the code service layer, a software test library, a driving module, a conversion interface and a chip design to be tested, wherein the code service layer and the software test library are sequentially connected, the code service layer and the software test library are realized based on software codes, and the software codes can be specifically realized by C language, C++ language and the like. The chip design to be tested is realized based on hardware codes, the conversion interface is realized based on software codes and hardware codes, and the hardware codes can be realized by Verilog language, systemVeriliog language and the like. It should be noted that, in the chip verification process, the software test case may generally run directly in the system level verification and/or the software level verification stage, and run on a hardware accelerator or a physical chip that is actually present. If the problem is found again in the system level verification stage and the software verification stage, a large amount of update cost is required, and the chip development efficiency is reduced. If some system level verification and/or software level verification can be performed in advance based on the chip RTL code, some problems existing in the RTL code can be solved before the hardware accelerator or the physical chip is generated, so that the chip development efficiency can be improved, and the chip development cost can be reduced. Therefore, the system of the embodiment of the invention operates the generated software test case on the chip design to be tested so as to realize that some system level verification and/or software level verification are performed in advance.
The software test library comprises N software test library files { F 1,F2,...,Fn,...,FN }, wherein F n is the nth software test library file, the value range of N is 1 to N, and N is the total number of software test library files in the software test library. The software test library can be an existing MQL test library or a GQL test library. The software test library files comprise a drawing library file, a carrying database file, a general calculation library file, a matrix operation library file, a model analysis library file and the like.
As an embodiment, the code service layer includes a global function module, a command packet creation and distribution module, a queue wakeup module, a multi-process scheduling module, and an operation result checking module, where each module of the code service layer binds at least one F n. It should be noted that each module of the code service layer may bind one F n or multiple fs n. The same F n may be bound to a code service layer on a number of different modules. After binding, a user does not need to directly butt-joint a large number of test library files when generating the software test cases, and only needs to call related functional modules based on simple parameter configuration.
As an embodiment, each module of the code service layer is configured to invoke the bound F n to transmit a corresponding functional instruction to the chip design to be tested through the driving module and the conversion interface. The conversion interface is used for converting the function instruction realized by the software language issued by each module of the code service layer into the function instruction realized by the hardware language and sending the function instruction to the chip design to be tested. It should be noted that, the code service layer and the software test library are implemented based on software codes, and the chip design to be tested is implemented based on hardware codes, so that a conversion interface is required to convert a functional instruction implemented by a software language issued by each module of the code service layer into a functional instruction implemented by a hardware language, so that the functional instruction can be run in the chip design to be tested.
As an embodiment, the conversion interface may be implemented specifically by an existing direct programming interface (Direct Programming Interface, abbreviated as DPI), which is a standard interface allowing the SystemVerilog code to directly call the C or c++ functions, and vice versa. DPI allows data and control information to be transferred between the two languages, and therefore, conversion between software language and SystemVerilog language can be achieved based on DPI, which is not described herein.
The system comprises an option library file generated by a user, the system extracts parameter options in the code service layer through the option library file, and the system respectively calls the corresponding application program interfaces to configure the parameter options into the corresponding modules of the code service layer.
As an embodiment, the global function module is configured to generate a preset function on or off instruction, where the preset functions include a virtualized function, a virtual address translation function, and a multi-card interconnection function, and the preset function on or off instruction is set by the global function module, so that the same test case is effective, and the preset function on or off instruction does not need to be set at each position related to the preset function.
As an embodiment, the command packet creation and distribution module is configured to create a command packet, and randomly map the command packet onto a single queue or multiple queues according to a user requirement, or map each command packet onto a corresponding queue one by one according to a preset mapping relationship, and distribute the command packet to the corresponding queue after the queue corresponding to the command packet wakes up. The command package creation and distribution module comprises M command package templates { R 1,R2,...,Rm,...,RM},Rm is an mth command package template, the value range of M is 1 to M, and the command package creation and distribution module is used for calling the corresponding command package template based on the corresponding parameter options and updating the corresponding parameters in the command package template based on the corresponding parameter options to generate the corresponding command package. It should be noted that, one test case may create one or more command packages, and if multiple command packages are created, the multiple command packages may be the same command package or different command packages.
As an embodiment, the queue wakeup module is configured to wake up a queue through doorbell operation according to a queue execution order. It should be noted that, the queue wakeup module may wake up the queue in a categorized manner. The queue wakeup module comprises a physical function queue wakeup unit, a virtualized queue wakeup unit and a queue wakeup unit in a multi-GPU mode, wherein the physical function queue wakeup unit, the virtualized queue wakeup unit and the queue wakeup unit in the multi-GPU mode are bound with different F n. The physical function queue awakening unit is used for calling a bound F n awakening unit physical function queue, the virtualized queue awakening unit is used for calling a bound F n awakening virtualized queue, and the queue awakening unit in the multi-GPU mode is used for calling a bound F n awakening queue in the multi-GPU mode.
As an embodiment, the multi-process scheduling module is configured to set at least one process, if the multi-process scheduling module is a plurality of processes, the plurality of processes may be set to be executed in order or in parallel according to a user requirement, and a mapping relationship between each process and a queue is constructed, and when the queue wakes up, a command packet corresponding to the chip design to be tested is executed in the queue through the corresponding process, and the chip design to be tested generates an execution result.
As an embodiment, the operation result checking module is configured to obtain an execution result, compare the execution result with a target result, and if the execution result is consistent with the target result, verify to pass, otherwise, verify to fail. And the running result checking module is used for acquiring the executing result based on the target address, comparing the executing result with the target result, and if the executing result is consistent with the target result, verifying that the executing result is passed, or else, verifying that the executing result is not passed. It should be noted that, in the embodiment of the invention, by setting the operation result checking module, the execution result can be obtained only by transmitting the target address, and the execution result is compared with the target result, so that a complex monitoring module is not required to be designed, the chip verification cost is reduced, and the chip verification efficiency is improved.
As an embodiment, the code service layer further includes a parallel operation module, where the parallel operation module is configured to issue a parallel operation instruction of multiple virtual devices, and set the multiple virtual devices to work in parallel.
In some application scenarios, a plurality of engines are required to work cooperatively, and as an embodiment, the code service layer further includes an engine cooperative instruction, which is configured to sequentially issue a cooperative instruction between the plurality of engines according to an engine working order and an execution quality type, so as to support the cooperative work of the plurality of engines, specifically, write data first for the engine 0, read data for the engine 2 and the engine 3, and so on.
The chip circuit is abnormal and is also part of an abnormal test, and as an embodiment, the code service layer further comprises an abnormal processing module for issuing an abnormal test instruction, and when the target test abnormality of the chip design to be tested is obtained, the instruction accords with the expected abnormal test, the next operation can be continued, an abnormal clearing instruction can be issued, and the operation is continued. If the target test abnormality does not occur, the abnormal test is not passed, and prompt information can be generated.
In order to make the updating of the software test library more reliable, the embodiment of the invention provides a method for updating the software test library, which comprises the following steps:
Step S1, a current software test library is obtained, wherein the current software test library comprises N software test library files { F 1,F2,...,Fn,...,FN }, F n is an nth software test library file, the value range of N is 1 to N, and N is the total number of software test library files in the current software test library.
Step S2, acquiring a software test library file { A 1,A2,...,Aq,...,AQ},Aq to be updated as a Q-th software test library file to be updated, wherein the value range of Q is 1 to Q, Q is the total number of software test library files to be updated, and N is more than or equal to Q.
And step S3, running a preset test case in a preset test case set based on the current software test library and the software test library file to be updated, wherein the corresponding A q is called when F n needing to be called exists corresponding A q, otherwise, the corresponding F n is called, and the preset test case is a test case of which the updated software test library of the software test library can affect hardware.
And S4, if all the preset test cases in the preset test case set pass the test, updating { A 1,A2,...,Aq,...,AQ } into { F 1,F2,...,Fn,...,FN }.
It should be noted that, the software test library file to be updated is written based on a software language and is usually aligned with the software code, that is, the software verification interface is not affected by the update, and if the verification of the preset test case is passed, it is indicated that the software test library file to be updated does not affect the hardware verification interface or the software verification interface. If all the preset test cases in the preset test case set pass the test, the update of the software test library file to be updated is not influenced by the verification, so { A 1,A2,...,Aq,...,AQ } can be updated into { F 1,F2,...,Fn,...,FN }. The software test library file updating flow can be standardized through the steps S1-S4, the reliability of software test library updating is improved, and further the chip verification efficiency is improved.
As an embodiment, in the step S4, if there is a failed preset test case in the preset test case set, step S5 is executed;
and S5, judging whether the software code and the hardware code are aligned with the software test library file to be updated, if not, executing the step S6, and if not, executing the step S7.
It should be noted that the alignment of the software code with the software test library file to be updated means that the software test library file to be updated is generated without affecting the software verification interface. The alignment of the hardware code with the software test library file to be updated means that the software test library file to be updated is generated without affecting the hardware verification interface.
And S6, updating a code service layer based on the failed preset test case, wherein the code service layer is used for calling a software test library to generate a software test case, and returning to the step S1.
It should be noted that, the preset test case caused by the misalignment with the hardware code is not caused by the update of the hardware interface, and in this case, the software interface and the hardware interface can be matched with the preset test case by updating the code service layer, so that the preset test case can run through.
And step S7, updating { A 1,A2,...,Aq,...,AQ } based on the failed preset test case, and returning to the step S1.
It should be noted that { A 1,A2,...,Aq,...,AQ } is often an unreasonable update if it is not aligned with the software code, and thus { A 1,A2,...,Aq,...,AQ } needs to be retrieved.
As an embodiment, the step S3 includes:
step S31, generating an option parameter file based on each preset test case.
And S32, extracting parameter options corresponding to each module of the code service layer from the option parameter file, and respectively calling corresponding application program interfaces to configure the parameter options into the modules corresponding to the code service layer.
And step S33, each module of the code service layer is used for calling the bound F n to generate a corresponding functional instruction, converting the functional instruction corresponding to each module into a functional instruction realized by a hardware language and sending the functional instruction to a chip design to be tested, wherein the chip design to be tested executes the received functional instruction realized by the hardware language to generate an execution result, and comparing the execution result with a target result, if the execution result is consistent with the target result, the verification is passed, otherwise, the verification is not passed.
As an embodiment, the step S33 includes:
step S331, a function on or off instruction is generated based on the global function module.
The preset functions comprise a virtualization function, a virtual address translation function and a multi-card interconnection function, a preset function opening or closing instruction is set through the global function module, the same test case is validated, and the preset functions do not need to be set at each position related to the preset functions.
Step S332, a command packet creation and distribution module is used for creating command packets, and the command packets are randomly mapped onto a single queue or a plurality of queues according to user requirements, or each command packet is mapped onto a corresponding queue one by one according to a preset mapping relation, and the command packets are distributed to the corresponding queues after the queues corresponding to the command packets are awakened.
As an embodiment, the command packet creation and distribution module includes M command packet templates { R 1,R2,...,Rm,...,RM},Rm is an mth command packet template, M has a value range from 1 to M, and M is a total number of command packet templates, and in step S332, the command packet creation and distribution module is configured to create a command packet based on the command packet creation and distribution module, and includes:
step S3321, the command packet creation and distribution module calls a corresponding command packet template based on the corresponding parameter options, and updates the corresponding parameters in the command packet template based on the corresponding parameter options to generate a corresponding command packet.
It should be noted that, one test case may create one or more command packages, and if multiple command packages are created, the multiple command packages may be the same command package or different command packages.
Step S333, the queue is awakened by doorbell operation according to the queue execution sequence based on the queue awakening module.
The queue awakening module is used for awakening the queue through doorbell operation according to the queue execution sequence. It should be noted that, the queue wakeup module may wake up the queue in a categorized manner. The queue wakeup module comprises a physical function queue wakeup unit, a virtualized queue wakeup unit and a queue wakeup unit in a multi-GPU mode, wherein the physical function queue wakeup unit, the virtualized queue wakeup unit and the queue wakeup unit in the multi-GPU mode are bound with different F n. The physical function queue awakening unit is used for calling a bound F n awakening unit physical function queue, the virtualized queue awakening unit is used for calling a bound F n awakening virtualized queue, and the queue awakening unit in the multi-GPU mode is used for calling a bound F n awakening queue in the multi-GPU mode.
Step 334, at least one process is set based on the multi-process scheduling module, if the multi-process scheduling module is a plurality of processes, the plurality of processes are set to be executed in order or in parallel according to the user requirement, a mapping relation between each process and the queue is constructed, a corresponding command packet is designed in the chip to be tested through a corresponding process execution queue when the queue wakes up, and the chip to be tested is designed to generate an execution result.
Step S335, based on the operation result checking module to obtain the execution result, comparing the execution result with the target result, if the execution result is consistent with the target result, verifying to pass, otherwise, verifying to fail.
According to the embodiment of the invention, the code service layer is constructed, the universal functional module is arranged, the functional module is well bound with the software test library file, the user can generate the software test case by calling the functional module corresponding to the code service layer through simple parameter control, the generation efficiency of the software test case is improved, and the chip verification efficiency is further improved.
The present invention is not limited to the preferred embodiments, and the present invention is described above in any way, but is not limited to the preferred embodiments, and any person skilled in the art will appreciate that the present invention is not limited to the embodiments described above, while the above disclosure is directed to various equivalent embodiments, which are capable of being modified or varied in several ways, it is apparent to those skilled in the art that many modifications, variations and adaptations of the embodiments described above are possible in light of the above teachings.
Claims (10)
1. A chip verification system based on a code service layer is characterized in that,
The system comprises a code service layer, a software test library, a driving module, a conversion interface and a chip design to be tested, which are sequentially connected, wherein the code service layer and the software test library are realized based on software codes, the chip design to be tested is realized based on hardware codes, and the conversion interface is realized based on the software codes and the hardware codes;
The software test library comprises N software test library files { F 1,F2,...,Fn,...,FN }, wherein F n is an nth software test library file, and the value range of N is 1 to N;
The code service layer comprises a global function module, a command packet creation and distribution module, a queue wakeup module, a multi-process scheduling module and an operation result checking module, wherein each module of the code service layer is at least bound with one F n;
Each module of the code service layer is used for calling the bound F n to transmit corresponding functional instructions to the chip design to be tested through the driving module and the conversion interface;
The conversion interface is used for converting the function instruction realized by the software language issued by each module of the code service layer into the function instruction realized by the hardware language and sending the function instruction to the chip design to be tested;
The global function module is used for generating a preset function opening or closing instruction;
The command packet creation and distribution module is used for creating command packets and randomly mapping the command packets onto a single queue or a plurality of queues, or mapping each command packet onto a corresponding queue one by one according to a preset mapping relation, and distributing the command packets to the corresponding queues after the queues corresponding to the command packets are awakened;
The queue awakening module is used for awakening the queue through doorbell operation according to the execution sequence of the queue;
The multi-process scheduling module is used for setting at least one process, if the multi-process scheduling module is a plurality of processes, the plurality of processes are set to be executed in order or in parallel, a mapping relation between each process and a queue is constructed, a command packet corresponding to the chip design to be tested is executed in the queue through the corresponding process when the queue wakes up, and the chip design to be tested generates an execution result;
The operation result checking module is used for acquiring an execution result, comparing the execution result with a target result, and if the execution result is consistent with the target result, verifying to pass, otherwise, verifying to fail.
2. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
The preset functions comprise a virtualization function, a virtual address translation function and a multi-card interconnection function.
3. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
The software test library file comprises a drawing library file, a carrying database file, a general calculation library file, a matrix operation library file and a model analysis library file.
4. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
Each module in the code service layer is provided with an application program interface for configuring each module;
The system comprises an option library file generated by a user, extracts the parameter options in the code service layer through the option library file, and respectively calls the corresponding application program interfaces to configure the parameter options into the corresponding modules of the code service layer.
5. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
The command package creation and distribution module comprises M command package templates { R 1,R2,...,Rm,...,RM},Rm is an mth command package template, and the value range of M is 1 to M;
The command package creation and distribution module is used for calling a corresponding command package template based on the corresponding parameter options, updating the corresponding parameters in the command package template based on the corresponding parameter options, and generating a corresponding command package.
6. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
The code service layer also comprises a parallel operation module, wherein the parallel operation module is used for issuing a plurality of virtual equipment parallel operation instructions.
7. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
The code service layer also comprises an engine cooperative work instruction, and the engine cooperative work instruction is used for sequentially issuing the cooperative work instruction among a plurality of engines according to the engine work order and the execution quality type.
8. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
The code service layer also comprises an exception handling module which is used for issuing an exception test instruction, and issuing an exception clearing instruction when the target test exception of the chip design to be tested is obtained.
9. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
After the chip design to be tested generates an execution result, storing the execution result into a target address, and sending the target address to the operation result checking module;
the operation result checking module is used for acquiring an execution result based on the target address, comparing the execution result with the target result, and if the execution result is consistent with the target result, verifying to pass, otherwise, verifying to fail.
10. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
The queue wakeup module comprises a physical function queue wakeup unit, a virtualized queue wakeup unit and a queue wakeup unit in a multi-GPU mode, wherein the physical function queue wakeup unit, the virtualized queue wakeup unit and the queue wakeup unit in the multi-GPU mode are bound with different F n;
The physical function queue awakening unit is used for calling the physical function queue of the F n awakening unit;
The virtualization queue awakening unit is used for invoking the F n for awakening the virtualization queue;
The queue wakeup unit in the multi-GPU mode is used for invoking the F n for waking up the queue in the multi-GPU mode.
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| CN119556956A (en) * | 2024-11-29 | 2025-03-04 | 沐曦科技(北京)有限公司 | Software testing library updating method, electronic device and medium |
| CN120066969A (en) * | 2025-03-11 | 2025-05-30 | 沐曦集成电路(上海)股份有限公司 | IPC-based software and hardware joint debugging method, electronic equipment and medium |
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