TWI898875B - Method of manufacturing semiconductor device - Google Patents

Abstract

The present disclosure provides a method of manufacturing a semiconductor device. The method includes: sequentially forming a substrate, a target layer, a hardmask layer, and a temperature sensitive material layer, in which the temperature sensitive material layer is located over the substrate, the target layer is located between the substrate and the hardmask layer, and the hardmask layer is located between the target layer and the temperature sensitive material layer; forming a plurality of first hollowed portions on the temperature sensitive material layer by a patterned etching photomask; removing the patterned etching photomask; cooling the temperature sensitive material layer to form a plurality of second hollowed portions in situ on places where the first hollowed portions locate; forming a plurality of third hollowed portions on the hardmask layer by the temperature sensitive material layer; removing the temperature sensitive material layer; forming a plurality of fourth hollowed portions on the target layer by the hardmask layer; and removing the hardmask layer.

Description

Method for manufacturing semiconductor device

This disclosure relates to a method for manufacturing a semiconductor device.

In semiconductor manufacturing, a patterned mask is generally used to pattern the target layer. Specifically, the patterning of the target layer is performed through repeated photolithography and etching processes. However, with the miniaturization of semiconductor devices, the thickness limit of the patterned mask and the characteristics of the etch selectivity between layers will cause the pattern transferred to the target layer to be severely deformed. For example, the trench with the same width from top to bottom may be wider at the top and narrower at the bottom after the conventional patterning process. Therefore, there is an urgent need in the field for a semiconductor device manufacturing method that can solve the above problem.

In view of this, one purpose of the present disclosure is to provide a method for manufacturing a semiconductor device that can solve the above-mentioned problems.

To achieve the above-mentioned object, according to one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: sequentially forming a substrate, a target layer, a hard mask layer, and a temperature sensitive material layer, wherein the temperature sensitive material layer is located above the substrate, the target layer is located between the substrate and the hard mask layer, and the hard mask layer is located between the target layer and the temperature sensitive material layer; A plurality of first cutouts are formed on a temperature-sensitive material layer; the patterned etch mask is removed; the temperature-sensitive material layer is cooled to in-situ form a plurality of second cutouts at the first cutouts; a plurality of third cutouts are formed on a hard mask layer through the temperature-sensitive material layer; the temperature-sensitive material layer is removed; a plurality of fourth cutouts are formed on a target layer through the hard mask layer; and the hard mask layer is removed.

In one or more embodiments of the present disclosure, the width of each of the second cutouts is greater than the width of each of the first cutouts.

In one or more embodiments of the present disclosure, the width of each of the third hollow portions and the width of each of the fourth hollow portions are the same as the width of each of the second hollow portions.

In one or more embodiments of the present disclosure, the temperature-sensitive material layer is made of a positive thermal expansion material.

In one or more embodiments of the present disclosure, the step of cooling the temperature-sensitive material layer is performed before the step of forming a fourth hollow portion on the target layer using a hard mask layer.

To achieve the above objectives, according to one embodiment of the present disclosure, a method for fabricating a semiconductor device includes: sequentially forming a substrate, a target layer, a mold layer, and a hard mask layer, wherein the hard mask layer is located above the substrate, the target layer is located between the substrate and the mold layer, and the mold layer is located between the target layer and the hard mask layer; forming a plurality of first cutouts in the hard mask layer using a patterned etch mask; and removing the patterned etch mask. A plurality of second hollow portions are formed on the casting layer using a hard mask layer; the hard mask layer is removed; a temperature-sensitive material layer is filled into the second hollow portions of the casting layer; the casting layer is removed to in-situ form a plurality of third hollow portions in the casting layer; the temperature-sensitive material layer is cooled to in-situ form a plurality of fourth hollow portions in the third hollow portions; a plurality of fifth hollow portions are formed on the target layer using the temperature-sensitive material layer; and the temperature-sensitive material layer is removed.

In one or more embodiments of the present disclosure, the width of each of the fourth cutouts is greater than the width of each of the third cutouts.

In one or more embodiments of the present disclosure, the width of each of the fifth cutouts is the same as the width of each of the fourth cutouts.

In one or more embodiments of the present disclosure, the temperature-sensitive material layer is made of a positive thermal expansion material.

In one or more embodiments of the present disclosure, the step of cooling the temperature-sensitive material layer is performed before the step of forming a fifth hollow portion on the target layer using the temperature-sensitive material layer.

In summary, in the semiconductor device manufacturing method disclosed herein, because the temperature-sensitive material layer can expand isotropically with temperature changes, the tedious step of precisely adjusting the etch pattern of the patterned etch mask can be eliminated. In the semiconductor device manufacturing method disclosed herein, because the temperature-sensitive material layer, whose volume changes with temperature, is configured as a patterned mask for the target layer, the target layer pattern can be satisfactorily achieved. This semiconductor device manufacturing method disclosed herein not only significantly improves the process window but also enhances the electrical performance of the semiconductor device.

The above description is merely intended to illustrate the problems to be solved by this disclosure, the technical means for solving the problems, and the resulting effects. The specific details of this disclosure will be described in detail in the following implementation methods and related figures.

100,200:Semiconductor components

110,210: Target layer

120,230: Hard mask layer

130,250: Temperature-sensitive material layer

140,240: Patterned etch mask

220: Casting layer

CD1, CD2, CD3, CD4: Critical Size

EH1, EH2, EH3, EH4, EH5, EH6, EH7, EH8, EH9, EH10: Etching process

HP1, HP2, HP3, HP4, HP5, HP6, HP7, HP8, HP9: Hollow area

HT1, HT2: Temperature Control Process

M1, M2: Methods

PT1, PT2: Etched Pattern

RF: Filling process

S101, S102, S103, S104, S105, S106, S107, S108, S201, S202, S203, S204, S205, S206, S207, S208, S209, S210: Steps

SUB:Substrate

W _HP1 , W _HP2 , W _HP3 , W _HP4 , W _HP5 , W _HP6 , W _HP7 , W _HP8 , W _HP9 : Width

To make the above and other purposes, features, advantages and implementation methods of this disclosure more clearly understood, the attached drawings are explained as follows:

Figure 1 is a flow chart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

Figure 2 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.

Figure 3 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.

Figure 4 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.

Figure 5 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.

Figure 6 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.

Figure 7 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.

Figure 8 is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor device according to one embodiment of the present disclosure.

Figure 9 is a flow chart illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

FIG10 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure.

Figure 11 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure.

Figure 12 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure.

FIG13 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure.

Figure 14 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure.

Figure 15 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure.

FIG16 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure.

Figure 17 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure.

The following figures illustrate several embodiments of the present disclosure. For the sake of clarity, numerous practical details are included in the following description. However, it should be understood that these practical details should not be construed as limiting the present disclosure. In other words, these practical details are not essential to some embodiments of the present disclosure. Furthermore, to simplify the drawings, some commonly used structures and components are shown in simplified schematic form. The same reference numerals will be used throughout the figures to indicate identical or similar components.

Please refer to FIG. 1 . FIG. 1 is a flow chart of a method M1 for manufacturing the semiconductor device 100 shown in FIG. 8 , according to one embodiment of the present disclosure. Method M1 shown in FIG. 1 includes steps S101, S102, S103, S104, S105, S106, S107, and S108. For a better understanding of step S101, please refer to FIG. 1 and FIG. 2 . For a better understanding of step S102, please refer to FIG. 1 and FIG. 3 . For a better understanding of step S103, please refer to FIG. 1 and FIG. 4 . For a better understanding of step S104, please refer to FIG. 1 and FIG. 5 . For a better understanding of step S105, please refer to Figures 1 and 6. For a better understanding of step S106, please refer to Figures 1 and 7. For a better understanding of steps S107 and S108, please refer to Figures 1 and 8.

The following describes steps S101, S102, S103, S104, S105, S106, S107, and S108 in detail.

In step S101, a substrate SUB, a target layer 110, a hard mask layer 120, and a temperature-sensitive material layer 130 are sequentially formed.

Please refer to Figures 1 and 2. Figure 2 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device 100 according to one embodiment of the present disclosure. As shown in Figure 2, in this embodiment, a substrate SUB is provided. A target layer 110 is formed on the substrate SUB. A hard mask layer 120 is formed on the target layer 110. A temperature-sensitive material layer 130 is formed on the hard mask layer 120. As shown in Figure 2, the temperature-sensitive material layer 130 is located above the substrate SUB. The target layer 110 is located between the substrate SUB and the hard mask layer 120. The hard mask layer 120 is located between the target layer 110 and the temperature-sensitive material layer 130. As shown in FIG. 2 , in this embodiment, a patterned etch mask 140 is provided and positioned over the temperature-sensitive material layer 130 . The patterned etch mask 140 has an etch pattern PT1 . In some embodiments, the etch pattern PT1 penetrates the patterned etch mask 140 . In some embodiments, the patterned etch mask 140 having the etch pattern PT1 exposes the temperature-sensitive material layer 130 .

In some embodiments, the substrate SUB may include materials such as silicon-based materials and pad oxides. However, any suitable material may be used.

In some embodiments, the substrate SUB can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or similar methods. This disclosure is not intended to be limited to the method for forming the substrate SUB.

In some embodiments, the target layer 110 may include, for example, polysilicon. However, any suitable material may be used.

In some embodiments, the target layer 110 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. This disclosure is not intended to limit the method for forming the target layer 110.

In some embodiments, the hard mask layer 120 may include, for example, a nitride material such as silicon nitride (Si _x N _y ) or titanium nitride (Ti _x N _y ). However, any suitable material may be used.

In some embodiments, the hard mask layer 120 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. This disclosure is not intended to limit the method for forming the hard mask layer 120.

In some embodiments, the temperature-sensitive material layer 130 may be, for example, a temperature-sensitive material, such as a thermal expansion material or a negative thermal expansion material (NTE). However, any suitable temperature-sensitive material may be used.

In some embodiments, the temperature-sensitive material layer 130 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or similar methods. This disclosure is not intended to limit the method for forming the temperature-sensitive material layer 130.

In some embodiments, the patterned etch mask 140 may be made of a material such as photoresist (PR) or quartz glass. However, any suitable material may be used.

In some embodiments, the patterned etch mask 140 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to limit the method for forming the patterned etch mask 140.

In some embodiments, the etched pattern PT1 may have a plurality of hollowed portions.

In some embodiments, the etched pattern PT1 can be formed by any suitable method, such as photolithography or a similar method. This disclosure is not intended to limit the method for forming the etched pattern PT1.

In step S102, a plurality of hollow portions HP1 are formed on the temperature-sensitive material layer 130 by patterning the etching mask 140.

Please refer to FIG. 1 and FIG. 3. FIG. 3 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in FIG. 3, in this embodiment, a plurality of hollow portions HP1 are formed on a temperature-sensitive material layer 130. Specifically, the hollow portions HP1 penetrate the temperature-sensitive material layer 130, exposing the hard mask layer 120. As shown in FIG. 3, in some embodiments, the temperature-sensitive material layer 130 is subjected to an etching process EH1, so that an etch pattern PT1 of a patterned etching mask 140 is transferred to the temperature-sensitive material layer 130 to form the plurality of hollow portions HP1. In some embodiments, each hollow portion HP1 formed by performing the etching process EH1 has a width W _HP1 .

In some embodiments, the etching process EH1 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In step S103, the patterned etching mask 140 is removed.

Please refer to FIG. 1 and FIG. 4 . FIG. 4 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device 100 according to one embodiment of the present disclosure. As shown in FIG. 4 , in this embodiment, the patterned etch mask 140 located on the temperature-sensitive material layer 130 is removed by performing an etching process EH2 . In some embodiments, because each hollow portion HP1 has a width W _HP1 by the etching process EH1 in step S102 , the remaining portion of the temperature-sensitive material layer 130 correspondingly has a critical dimension CD1 .

In some embodiments, the etching process EH2 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In step S104, the temperature-sensitive material layer 130 is heated to form a plurality of hollow portions HP2.

Please refer to Figures 1 and 5. Figure 5 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device 100 according to one embodiment of the present disclosure. As shown in Figure 5, in this embodiment, a hollow portion HP2 is formed on a temperature-sensitive material layer 130. Specifically, the hollow portion HP2 penetrates the temperature-sensitive material layer 130, exposing the hard mask layer 120. As shown in Figure 5, in some embodiments, the temperature-sensitive material layer 130 is subjected to a temperature control process HT1, thereby converting a plurality of hollow portions HP1 into a plurality of hollow portions HP2. Specifically, during the temperature control process HT1, the temperature-sensitive material layer 130 deforms as the temperature changes, causing the hollow portion HP2 to be formed in situ within the hollow portion HP1.

In some embodiments, each hollow portion HP2 formed by performing the temperature control process HT1 has a width W _HP2 .

In some embodiments, since each hollow portion HP2 has a width W _HP2 through the temperature control process HT1 in step S104 , the remaining portion of the temperature sensitive material layer 130 correspondingly has a critical dimension CD2 .

In some embodiments where the temperature-sensitive material layer 130 is a negative thermal expansion material, the temperature control process HT1 can be a temperature-raising process (e.g., heating). The temperature-sensitive material layer 130 is heated and contracts, thereby making the width W _HP2 of each hollow portion HP2 greater than the width W _HP1 of each hollow portion HP1 (i.e., the critical dimension CD2 of the temperature-sensitive material layer 130 is smaller than the critical dimension CD1 of the temperature-sensitive material layer 130). However, the present disclosure is not limited to this. In some embodiments where the temperature-sensitive material layer 130 is a positive thermal expansion material, the temperature control process HT1 can be a temperature-lowering process, which also falls within the spirit and scope of the present disclosure.

In step S105, a plurality of hollow portions HP3 are formed on the hard mask layer 120 using the temperature-sensitive material layer 130.

Please refer to Figure 1 and Figure 6. Figure 6 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in Figure 6, in this embodiment, a plurality of hollow portions HP3 are formed on the hard mask layer 120. Specifically, the hollow portions HP3 penetrate the hard mask layer 120, so that the target layer 110 is exposed. As shown in Figure 6, in some embodiments, the hard mask layer 120 is formed by performing an etching process EH3 and forming a plurality of hollow portions HP3 on the hard mask layer 120 through a plurality of hollow portions HP2 of the temperature-sensitive material layer 130. In some embodiments, each hollow portion HP3 formed by performing the etching process EH3 has a width W _HP3 .

In some embodiments, the etching process EH3 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In some embodiments, the width W _HP3 of each hollow portion HP3 is equal to the width W _HP2 of each hollow portion HP2.

In step S106, the temperature-sensitive material layer 130 is removed.

Please refer to Figures 1 and 7. Figure 7 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device 100 according to one embodiment of the present disclosure. As shown in Figure 7, in this embodiment, the temperature-sensitive material layer 130 located on the hard mask layer 120 is removed by performing an etching process EH4.

In some embodiments, the etching process EH4 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In step S107, a plurality of hollow portions HP4 are formed on the target layer 110 using the hard mask layer 120.

Please refer to FIG. 1 and FIG. 8 . FIG. 8 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in FIG. 8 , in this embodiment, a plurality of hollow portions HP4 are formed on a target layer 110. Specifically, the hollow portions HP4 penetrate the target layer 110, exposing the substrate SUB. As shown in FIG. 8 , in some embodiments, the target layer 110 is etched by performing an etching process EH5, and a plurality of hollow portions HP4 are formed on the target layer 110 through the plurality of hollow portions HP3 of the hard mask layer 120. Specifically, the hard mask layer 120 is configured as a patterned mask for patterning the target layer 110. In some embodiments, each hollow portion HP4 formed by performing the etching process EH5 has a width W _HP4 .

In some embodiments, the etching process EH5 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In some embodiments, the width W _HP4 of each hollow portion HP4 is equal to the width W _HP3 of each hollow portion HP3.

In step S108, the hard mask layer 120 is removed.

Please refer again to Figures 1 and 8. As shown in Figure 8, in this embodiment, the hard mask layer 120 on the target layer 110 is removed by performing an additional etching process, thereby forming the semiconductor device 100. As shown in Figure 8, by sequentially performing steps S101 to S108, the semiconductor device 100 including the substrate SUB and the target layer 110 having a plurality of hollow portions HP4 can be manufactured.

In some embodiments, the width W _HP4 of each hollow portion HP4 is greater than the width W _HP1 of each hollow portion HP1. This means that the manufacturer does not need to define an etch pattern on the patterned etch mask 140, which is difficult to control in the patterning process used in current technology. Instead, the manufacturer can use the etch pattern PT1, which maintains quality in current technology, and then use the temperature-sensitive material layer 130, which isotropically expands with temperature changes, as a patterning mask to pattern the target layer 110. This allows the manufacturer to manufacture a semiconductor device 100 including a satisfactorily patterned target layer 110.

The following describes in detail a method M2 for manufacturing a semiconductor device 200 according to another embodiment of the present disclosure.

Please refer to FIG. 9 . FIG. 9 is a flow chart of method M2 for manufacturing the semiconductor device 200 shown in FIG. 17 , according to another embodiment of the present disclosure. Method M2 shown in FIG. 9 includes steps S201, S202, S203, S204, S205, S206, S207, S208, S209, and S210. For a better understanding of step S201, please refer to FIG. 9 and FIG. 10 . For a better understanding of steps S202 and S203, please refer to FIG. 9 and FIG. 11 . For a better understanding of step S204, please refer to FIG. 9 and FIG. 12 . For a better understanding of step S205, please refer to Figures 9 and 13. For a better understanding of step S206, please refer to Figures 9 and 14. For a better understanding of step S207, please refer to Figures 9 and 15. For a better understanding of step S208, please refer to Figures 9 and 16. For a better understanding of steps S209 and S210, please refer to Figures 9 and 17.

The following describes steps S201, S202, S203, S204, S205, S206, S207, S208, S209, and S210 in detail.

In step S201, the substrate SUB, target layer 210, mold layer 220, and hard mask layer 230 are sequentially formed.

Please refer to Figures 9 and 10. Figure 10 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 200 according to another embodiment of the present disclosure. As shown in Figure 10, in this embodiment, a substrate SUB is provided. A target layer 210 is formed on the substrate SUB. A mold layer 220 is formed on the target layer 210. A hard mask layer 230 is formed on the mold layer 220. As shown in Figure 10, the hard mask layer 230 is located above the substrate SUB. The target layer 210 is located between the substrate SUB and the mold layer 220. The mold layer 220 is located between the target layer 210 and the hard mask layer 230. As shown in FIG. 2 , in this embodiment, a patterned etch mask 240 is provided on the hard mask layer 230 . The patterned etch mask 240 has an etch pattern PT2 . In some embodiments, the etch pattern PT2 penetrates the patterned etch mask 240 . In some embodiments, the patterned etch mask 240 having the etch pattern PT2 exposes the hard mask layer 230 .

In some embodiments, the target layer 210 may include, for example, polysilicon. However, any suitable material may be used.

In some embodiments, the target layer 210 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. This disclosure is not intended to limit the method for forming the target layer 210.

In some embodiments, the mold layer 220 may include, for example, a nitride material such as silicon nitride (SiO ₂ ) or titanium nitride (TiO ₂ ). However, any suitable material may be used.

In some embodiments, the casting layer 220 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. This disclosure is not intended to limit the method for forming the casting layer 220.

In some embodiments, the hard mask layer 230 may include, for example, a nitride material such as silicon nitride (Si _x N _y ) or titanium nitride (Ti _x N _y ). However, any suitable material may be used.

In some embodiments, the hard mask layer 230 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. This disclosure is not intended to limit the method for forming the hard mask layer 230.

In some embodiments, the patterned etch mask 240 may be made of a material such as photoresist (PR) or quartz glass. However, any suitable material may be used.

In some embodiments, the patterned etch mask 240 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. This disclosure is not intended to be limited to the method used to form the patterned etch mask 240.

In some embodiments, the etched pattern PT2 may have a plurality of hollowed portions.

In some embodiments, the etched pattern PT2 can be formed by any suitable method, such as photolithography or a similar method. This disclosure is not intended to limit the method for forming the etched pattern PT2.

In step S202, a plurality of hollow portions HP5 are formed on the hard mask layer 230 by patterning the etching mask 240.

Please refer to Figures 9 and 11. Figure 11 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 200 according to another embodiment of the present disclosure. As shown in Figure 11, in this embodiment, a plurality of hollow portions HP5 are formed on a hard mask layer 230. Specifically, the hollow portions HP5 penetrate the hard mask layer 230, exposing the mold layer 220. As shown in Figure 11, in some embodiments, the hard mask layer 230 is subjected to an etching process EH6, so that the etch pattern PT2 of the patterned etching mask 240 is transferred to the hard mask layer 230 to form the plurality of hollow portions HP5. In some embodiments, each hollow portion HP5 formed by performing the etching process EH6 has a width W _HP5 .

In some embodiments, the etching process EH6 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In step S203, the patterned etching mask 240 is removed.

Please continue to refer to Figures 9 and 11. As shown in Figure 11, in this embodiment, the patterned etch mask 240 located on the hard mask layer 230 is removed by performing an additional etching process.

In step S204, a plurality of hollow portions HP6 are formed on the casting layer 220 using the hard mask layer 230.

Please refer to Figures 9 and 12. Figure 12 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 200 according to another embodiment of the present disclosure. As shown in Figure 12, in this embodiment, a plurality of hollow portions HP6 are formed on the mold layer 220. Specifically, the hollow portions HP6 penetrate the mold layer 220, exposing the target layer 210. As shown in Figure 12, in some embodiments, the mold layer 220 is etched by performing an etching process EH7 through the hollow portions HP5 of the hard mask layer 230 to form the plurality of hollow portions HP6 on the mold layer 220. In some embodiments, each hollow portion HP6 formed by performing the etching process EH7 has a width W _HP6 .

In some embodiments, the etching process EH7 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In some embodiments, the width W _HP6 of each hollow portion HP6 is equal to the width W _HP5 of each hollow portion HP5.

In step S205, the hard mask layer 230 is removed.

Please refer to Figures 9 and 13. Figure 13 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device 200 according to another embodiment of the present disclosure. As shown in Figure 13, in this embodiment, the hard mask layer 230 located on the mold layer 220 is removed by performing an etching process EH8.

In some embodiments, the etching process EH8 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In step S206, the temperature-sensitive material layer 250 is filled into the plurality of hollow portions HP6 of the casting layer 220.

Please refer to Figures 9 and 14. Figure 14 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device 200 according to another embodiment of the present disclosure. As shown in Figure 14, in this embodiment, after forming a plurality of hollow portions HP6 in the mold layer 220, a temperature-sensitive material layer 250 is filled into the hollow portions HP6, causing the hollow portions HP6 to be backfilled. As shown in Figure 14, in some embodiments, the temperature-sensitive material layer 250 is subjected to a filling process RF, so that the hollow portions HP6 are completely filled with the temperature-sensitive material layer 250.

In some embodiments, the temperature-sensitive material layer 250 can be, for example, a temperature-sensitive material, such as a thermal expansion material or a negative thermal expansion material (NTE). However, any suitable temperature-sensitive material can be used.

In some embodiments, the temperature-sensitive material layer 250 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or similar methods. This disclosure is not intended to limit the method for forming the temperature-sensitive material layer 250.

In step S207, the casting layer 220 is removed to form a plurality of hollow portions HP7 in the casting layer 220.

Please refer to Figures 9 and 15. Figure 15 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device 200 according to another embodiment of the present disclosure. As shown in Figure 15, in this embodiment, the mold layer 220 is removed, leaving the temperature-sensitive material layer 250. Specifically, the mold layer 220 is removed by performing an etching process EH9, while the temperature-sensitive material layer 250 is left intact, resulting in the formation of a plurality of in-situ hollows HP7 where the mold layer 220 originally existed. In some embodiments, the hollows HP7 are defined by the temperature-sensitive material layer 250 and expose the target layer 210.

In some embodiments, each hollow portion HP7 formed by performing the etching process EH9 has a width W _HP7 , but the present disclosure is not limited thereto.

In some embodiments, since each hollow portion HP7 has a width W _HP7 through the etching process EH9 in step S207 , the temperature sensitive material layer 250 correspondingly has a critical dimension CD3 .

In some embodiments, the width W _HP7 of each hollow portion HP7 is greater than the width W _HP6 of each hollow portion HP6.

In step S208, the temperature-sensitive material layer 250 is heated to form a plurality of hollow portions HP8.

Please refer again to Figures 9 and 16. Figure 16 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device 200 according to another embodiment of the present disclosure. As shown in Figure 16, in this embodiment, a hollow portion HP8 is formed on a temperature-sensitive material layer 250. Specifically, the hollow portion HP8 penetrates the temperature-sensitive material layer 250, exposing the target layer 210. As shown in Figure 16, in some embodiments, the temperature-sensitive material layer 250 undergoes a temperature control process HT2, thereby transforming a plurality of hollow portions HP7 into a plurality of hollow portions HP8. Specifically, during the temperature control process HT2, the temperature-sensitive material layer 250 deforms as the temperature changes, causing the hollow portion HP8 to be formed in situ within the hollow portion HP7.

In some embodiments, each hollow portion HP8 formed by performing the temperature control process HT2 has a width W _HP8 .

In some embodiments, since each hollow portion HP8 has a width W _HP8 through the temperature control process HT2 in step S208 , the temperature sensitive material layer 250 correspondingly has a critical dimension CD4 .

In some embodiments where the temperature-sensitive material layer 250 is a negative thermal expansion material, the temperature control process HT2 may be a temperature-raising process (e.g., heating). The temperature-sensitive material layer 250 is heated and contracts, thereby making the width W _HP8 of each hollow portion HP8 greater than the width W _HP7 of each hollow portion HP7 (i.e., the critical dimension CD4 of the temperature-sensitive material layer 250 is smaller than the critical dimension CD3 of the temperature-sensitive material layer 250). However, the present disclosure is not limited to this. In some embodiments where the temperature-sensitive material layer 250 is a positive thermal expansion material, the temperature control process HT2 may be a temperature-lowering process, which also falls within the spirit and scope of the present disclosure.

In step S209, a plurality of hollow portions HP9 are formed on the target layer 210 using the temperature-sensitive material layer 250.

Please refer to FIG. 9 and FIG. 17 . FIG. 17 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in FIG. 17 , in this embodiment, a plurality of hollow portions HP9 are formed on a target layer 210. Specifically, the hollow portions HP9 penetrate the target layer 210, exposing the substrate SUB. As shown in FIG. 17 , in some embodiments, the target layer 210 is etched by performing an etching process EH10, and a plurality of hollow portions HP8 are defined by a temperature-sensitive material layer 250 to form a plurality of hollow portions HP9 on the target layer 210. Specifically, the temperature-sensitive material layer 250 is configured as a patterned mask for patterning the target layer 210. In some embodiments, each hollow portion HP9 formed by performing the etching process EH10 has a width W _HP9 .

In some embodiments, the etching process EH10 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In some embodiments, the width W _HP9 of each hollow portion HP9 is equal to the width W _HP8 of each hollow portion HP8.

In step S210, the temperature-sensitive material layer 250 is removed.

Please refer again to Figures 9 and 17. As shown in Figure 17, in this embodiment, the temperature-sensitive material layer 250 on the target layer 210 is removed by performing an additional etching process, thereby forming the semiconductor device 200. As shown in Figure 17, by sequentially performing steps S201 to S210, a semiconductor device 200 including a substrate SUB and a target layer 210 having a plurality of hollow portions HP9 can be manufactured.

In some embodiments, the width W _HP9 of each hollow portion HP9 is greater than the width W _HP5 of each hollow portion HP5. This means that the manufacturer does not need to define an etch pattern on the patterning reticle 240, which is difficult to control in the patterning process used in current technology. Instead, the manufacturer can use the etch pattern PT2, which maintains quality in current technology, and then use a temperature-sensitive material layer 250 that isotropically expands with temperature as a patterning mask to pattern the target layer 210. This allows the manufacturer to manufacture a semiconductor device 200 including a satisfactorily patterned target layer 210.

By performing the method M1 shown in FIG. 1 and the method M2 shown in FIG. 9 of the present disclosure, semiconductor devices 100 and 200 with improved electrical performance can be formed.

From the above detailed description of the specific embodiments of the present disclosure, it is apparent that in the semiconductor device manufacturing method disclosed herein, because the temperature-sensitive material layer can isotropically expand with temperature changes, the cumbersome step of precisely adjusting the etching pattern of the patterned etch mask can be eliminated. In the semiconductor device manufacturing method disclosed herein, because the temperature-sensitive material layer, whose volume changes with temperature, is configured as a patterned mask for the target layer, the target layer pattern can be satisfactorily achieved. The semiconductor device manufacturing method disclosed herein not only significantly improves the process window but also enhances the electrical performance of the semiconductor device.

Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

The above content summarizes the features of several embodiments, enabling those skilled in the art to better understand the present invention. Those skilled in the art should understand that, without departing from the spirit and scope of the present invention, the above content can readily serve as a basis for designing or modifying other variations that achieve the same objectives and/or advantages as the embodiments described herein. The above content should be understood as examples of the present disclosure, and the scope of protection thereof shall be determined by the scope of the patent application.

M1: Methods

S101, S102, S103, S104, S105, S106, S107, S108: Steps

Claims (10)

A method for manufacturing a semiconductor device comprises: sequentially forming a substrate, a target layer, a hard mask layer, and a temperature-sensitive material layer, wherein the temperature-sensitive material layer is located above the substrate, the target layer is located between the substrate and the hard mask layer, and the hard mask layer is located between the target layer and the temperature-sensitive material layer; forming a plurality of first cutouts on the temperature-sensitive material layer using a patterned etch mask; removing the patterned etch mask; cooling the temperature-sensitive material layer to in-situ form a plurality of second cutouts at the locations of the first cutouts; forming a plurality of third cutouts on the hard mask layer using the temperature-sensitive material layer; removing the temperature-sensitive material layer; A plurality of fourth cutouts are formed on the target layer using the hard mask layer; and the hard mask layer is removed. The method of claim 1, wherein a width of each of the second hollow portions is greater than a width of each of the first hollow portions. The method of claim 2, wherein a width of each of the third hollow portions and a width of each of the fourth hollow portions are the same as the width of each of the second hollow portions. The method of claim 2, wherein one of the materials of the temperature-sensitive material layer is a positive thermal expansion material. The method of claim 1, wherein the step of cooling the temperature-sensitive material layer is performed before the step of forming the fourth hollow portions on the target layer through the hard mask layer. A method for manufacturing a semiconductor device comprises: Sequentially forming a substrate, a target layer, a mold layer, and a hard mask layer, wherein the hard mask layer is located above the substrate, the target layer is located between the substrate and the mold layer, and the mold layer is located between the target layer and the hard mask layer; Forming a plurality of first cutouts on the hard mask layer using a patterned etch mask; Removing the patterned etch mask; Forming a plurality of second cutouts on the mold layer using the hard mask layer; Removing the hard mask layer; Filling the second cutouts of the mold layer with a temperature-sensitive material layer; The casting layer is removed to in-situ form a plurality of third cutouts in the casting layer; The temperature-sensitive material layer is cooled to in-situ form a plurality of fourth cutouts in the third cutouts; A plurality of fifth cutouts are formed on the target layer using the temperature-sensitive material layer; and The temperature-sensitive material layer is removed. The method of claim 6, wherein a width of each of the fourth hollow portions is greater than a width of each of the third hollow portions. The method of claim 7, wherein a width of each of the fifth cutouts is the same as the width of each of the fourth cutouts. The method of claim 7, wherein one of the materials of the temperature-sensitive material layer is a positive thermal expansion material. The method of claim 6, wherein the step of cooling the temperature-sensitive material layer is performed before the step of forming the fifth hollow portions on the target layer through the temperature-sensitive material layer.