TWI864891B - Method of manufacturing semiconductor device - Google Patents

Abstract

The present disclosure provides a method of manufacturing a semiconductor device. The method includes: sequentially forming a substrate, a target layer, a hardmask layer, and a temperature sensitive material layer, in which the temperature sensitive material layer is located over the substrate, the target layer is located between the substrate and the hardmask layer, and the hardmask layer is located between the target layer and the temperature sensitive material layer; forming a plurality of first hollowed portions on the temperature sensitive material layer by a patterned etching photomask; removing the patterned etching photomask; heating the temperature sensitive material layer to form a plurality of second hollowed portions in situ on places where the first hollowed portions locate; forming a plurality of third hollowed portions on the hardmask layer by the temperature sensitive material layer; removing the temperature sensitive material layer; forming a plurality of fourth hollowed portions on the target layer by the hardmask layer; and removing the hardmask layer.

Description

Method for manufacturing semiconductor device

The present disclosure relates to a method for manufacturing a semiconductor device.

In semiconductor manufacturing processes, a patterned mask is generally used to pattern the target layer. Specifically, the patterning of the target layer is performed by repeated photolithography and etching processes. However, with the miniaturization of semiconductor components, the thickness limitation of the patterned mask and the characteristics of the etch selectivity between layers will cause the pattern transferred to the target layer to be severely deformed. For example, an ideal trench with equal width from top to bottom may have a problem of being wider at the top and narrower at the bottom after the known patterning process. Therefore, the field is in urgent need of a method for manufacturing semiconductor components that can solve the above problems.

In view of this, one purpose of the present disclosure is to provide a method for manufacturing a semiconductor device that can solve the above-mentioned problems.

To achieve the above-mentioned purpose, according to one embodiment of the present disclosure, a method for manufacturing a semiconductor device comprises: sequentially forming a substrate, a target layer, a hard mask layer, and a temperature sensitive material layer, wherein the temperature sensitive material layer is located above the substrate, the target layer is located between the substrate and the hard mask layer, and the hard mask layer is located between the target layer and the temperature sensitive material layer; Forming a plurality of first hollow portions on the temperature sensitive material layer; removing the patterned etching mask; heating the temperature sensitive material layer to in-situ form a plurality of second hollow portions at the first hollow portions; forming a plurality of third hollow portions on the hard mask layer through the temperature sensitive material layer; removing the temperature sensitive material layer; forming a plurality of fourth hollow portions on the target layer through the hard mask layer; and removing the hard mask layer.

In one or more embodiments of the present disclosure, the width of each of the second hollow portions is greater than the width of each of the first hollow portions.

In one or more embodiments of the present disclosure, the width of each of the third hollow portions and the width of each of the fourth hollow portions are the same as the width of each of the second hollow portions.

In one or more embodiments of the present disclosure, the material of the temperature sensitive material layer is a negative thermal expansion material.

In one or more embodiments of the present disclosure, the step of heating the temperature sensitive material layer is performed before the step of forming a fourth hollow portion on the target layer through a hard mask layer.

To achieve the above-mentioned purpose, according to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: sequentially forming a substrate, a target layer, a mold layer, and a hard mask layer, wherein the hard mask layer is located above the substrate, the target layer is located between the substrate and the mold layer, and the mold layer is located between the target layer and the hard mask layer; forming a plurality of first hollow portions on the hard mask layer by using a patterned etching mask; removing the patterned etching mask; A plurality of second hollow portions are formed on the casting layer by means of a hard mask layer; the hard mask layer is removed; a temperature-sensitive material layer is filled in the second hollow portions of the casting layer; the casting layer is removed to form a plurality of third hollow portions in situ at the casting layer; the temperature-sensitive material layer is heated to form a plurality of fourth hollow portions in situ at the third hollow portions; a plurality of fifth hollow portions are formed on the target layer by means of the temperature-sensitive material layer; and the temperature-sensitive material layer is removed.

In one or more embodiments of the present disclosure, the width of each of the fourth hollow portions is greater than the width of each of the third hollow portions.

In one or more embodiments of the present disclosure, the width of each of the fifth hollow portions is the same as the width of each of the fourth hollow portions.

In one or more embodiments of the present disclosure, the material of the temperature sensitive material layer is a negative thermal expansion material.

In one or more embodiments of the present disclosure, the step of heating the temperature-sensitive material layer is performed before the step of forming a fifth hollow portion on the target layer through the temperature-sensitive material layer.

In summary, in the manufacturing method of the semiconductor element disclosed in the present invention, since the temperature-sensitive material layer can be isotropically contracted with temperature changes, the complicated step of precisely adjusting the etching pattern of the patterned etching mask can be omitted. In the manufacturing method of the semiconductor element disclosed in the present invention, since the temperature-sensitive material layer that can produce a volume change with temperature is configured as a patterned mask of the target layer, the pattern of the target layer can meet satisfactory requirements. The manufacturing method of the semiconductor element disclosed in the present invention not only greatly improves the process window, but also improves the electrical performance of the semiconductor element.

The above description is only used to explain the problem to be solved by the present disclosure, the technical means for solving the problem, and the effects produced, etc. The specific details of the present disclosure will be introduced in detail in the following implementation methods and related drawings.

The following will disclose multiple embodiments of the present disclosure with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner. The same reference numerals will be used to represent the same or similar components in all drawings.

Please refer to FIG. 1. FIG. 1 is a flow chart of a method M1 for manufacturing the semiconductor device 100 shown in FIG. 8 according to an embodiment of the present disclosure. The method M1 shown in FIG. 1 includes step S101, step S102, step S103, step S104, step S105, step S106, step S107 and step S108. For a better understanding of step S101, please refer to FIG. 1 and FIG. 2. For a better understanding of step S102, please refer to FIG. 1 and FIG. 3. For a better understanding of step S103, please refer to FIG. 1 and FIG. 4. For a better understanding of step S104, please refer to FIG. 1 and FIG. 5. For a better understanding of step S105, please refer to FIG. 1 and FIG. 6. For a better understanding of step S106, please refer to FIG. 1 and FIG. 7. For a better understanding of step S107 and step S108, please refer to FIG. 1 and FIG. 8.

The following describes step S101, step S102, step S103, step S104, step S105, step S106, step S107, and step S108 in detail.

In step S101 , a substrate SUB, a target layer 110 , a hard mask layer 120 , and a temperature sensitive material layer 130 are sequentially formed.

Please refer to Figure 1 and Figure 2. Figure 2 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in Figure 2, a substrate SUB is provided in this embodiment. A target layer 110 is formed on the substrate SUB. A hard mask layer 120 is formed on the target layer 110. A temperature-sensitive material layer 130 is formed on the hard mask layer 120. As shown in Figure 2, the temperature-sensitive material layer 130 is located above the substrate SUB. The target layer 110 is located between the substrate SUB and the hard mask layer 120. The hard mask layer 120 is located between the target layer 110 and the temperature-sensitive material layer 130. As shown in Figure 2, in this embodiment, a patterned etching mask 140 is provided and located on the temperature-sensitive material layer 130. The patterned etch mask 140 has an etch pattern PT1. In some embodiments, the etch pattern PT1 penetrates the patterned etch mask 140. In some embodiments, the patterned etch mask 140 having the etch pattern PT1 exposes the temperature sensitive material layer 130.

In some embodiments, the substrate SUB may include materials such as silicon-based materials and pad oxides. However, any suitable material may be used.

In some embodiments, the substrate SUB may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to be limited to the method of forming the substrate SUB.

In some implementations, the target layer 110 may include, for example, polysilicon. However, any suitable material may be used.

In some embodiments, the target layer 110 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to limit the method for forming the target layer 110.

In some implementations, the hard mask layer 120 may include, for example, a nitride material such as silicon nitride (Si _x N _y ) or titanium nitride (Tix _{N y} ). However, any suitable material may be used.

In some embodiments, the hard mask layer 120 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to be limited to the method of forming the hard mask layer 120.

In some embodiments, the temperature sensitive material layer 130 may be, for example, a temperature sensitive material, such as a thermal expansion material or a negative thermal expansion material (NTE). However, any suitable temperature sensitive material may be used.

In some embodiments, the temperature sensitive material layer 130 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to limit the method for forming the temperature sensitive material layer 130.

In some embodiments, the patterned etch mask 140 may be a material such as photoresist (PR) or quartz glass. However, any suitable material may be used.

In some embodiments, the patterned etch mask 140 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to be limited to the method of forming the patterned etch mask 140.

In some implementations, the etching pattern PT1 may have a plurality of hollowed portions.

In some embodiments, the etching pattern PT1 can be formed by any suitable method, such as photolithography or the like. The present disclosure is not intended to limit the method for forming the etching pattern PT1.

In step S102 , a plurality of hollow portions HP1 are formed on the temperature sensitive material layer 130 by patterning the etching mask 140 .

Please refer to FIG. 1 and FIG. 3. FIG. 3 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in FIG. 3, in this embodiment, a plurality of hollow portions HP1 are formed on the temperature-sensitive material layer 130. Specifically, the hollow portions HP1 penetrate the temperature-sensitive material layer 130, so that the hard mask layer 120 is exposed. As shown in FIG. 3, in some embodiments, the temperature-sensitive material layer 130 is subjected to an etching process EH1, so that the etching pattern PT1 of the patterned etching mask 140 is transferred to the temperature-sensitive material layer 130 to form a plurality of hollow portions HP1. In some implementations, each of the hollow portions HP1 formed by performing the etching process EH1 has a width W _HP1 .

In some implementations, the etching process EH1 may be, for example, wet etching, dry etching, a lithography process or other suitable methods.

In step S103, the patterned etching mask 140 is removed.

Please refer to FIG. 1 and FIG. 4. FIG. 4 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. As shown in FIG. 4, in this embodiment, the patterned etching mask 140 located on the temperature sensitive material layer 130 is removed by performing an etching process EH2. In some embodiments, since each hollow portion HP1 has a width W _HP1 by the etching process EH1 in step S102, the remaining portion of the temperature sensitive material layer 130 has a critical size CD1 accordingly.

In some implementations, the etching process EH2 may be, for example, wet etching, dry etching, a lithography process, or other suitable methods.

In step S104, the temperature sensitive material layer 130 is heated to form a plurality of hollow portions HP2.

Please refer to FIG. 1 and FIG. 5. FIG. 5 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in FIG. 5, in this embodiment, a hollow portion HP2 is formed on a temperature-sensitive material layer 130. Specifically, the hollow portion HP2 penetrates the temperature-sensitive material layer 130, so that the hard mask layer 120 is exposed. As shown in FIG. 5, in some embodiments, the temperature-sensitive material layer 130 is formed into a plurality of hollow portions HP2 by performing a temperature control process HT1. Specifically, when the temperature control process HT1 is performed, the temperature sensitive material layer 130 is deformed as the temperature changes, so that the hollow portion HP2 is formed in situ at the hollow portion HP1.

In some embodiments, each hollow portion HP2 formed by performing the temperature control process HT1 has a width W _HP2 .

In some embodiments, since each hollow portion HP2 has a width W _HP2 through the temperature control process HT1 in step S104 , the remaining portion of the temperature sensitive material layer 130 correspondingly has a critical dimension CD2 .

In some embodiments where the temperature sensitive material layer 130 is a negative thermal expansion material, the temperature control process HT1 may be a process of temperature rise (e.g., heating), and the temperature sensitive material layer 130 is heated and shrinks, so that the width W _HP2 of each hollow portion HP2 is greater than the width W _HP1 of each hollow portion HP1 (i.e., the critical dimension CD2 of the temperature sensitive material layer 130 is less than the critical dimension CD1 of the temperature sensitive material layer 130), but the present disclosure is not limited thereto. In some embodiments where the temperature sensitive material layer 130 is a positive thermal expansion material (Positive Thermal Expansion Material), the temperature control process HT1 may be a process of temperature drop, which also falls within the spirit and scope of the present case.

In step S105 , a plurality of hollow portions HP3 are formed on the hard mask layer 120 by using the temperature sensitive material layer 130 .

Please refer to FIG. 1 and FIG. 6. FIG. 6 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in FIG. 6, in this embodiment, a plurality of hollow portions HP3 are formed on the hard mask layer 120. Specifically, the hollow portions HP3 penetrate the hard mask layer 120, so that the target layer 110 is exposed. As shown in FIG. 6, in some embodiments, the hard mask layer 120 is formed by performing an etching process EH3 and forming a plurality of hollow portions HP3 on the hard mask layer 120 through a plurality of hollow portions HP2 of a temperature-sensitive material layer 130. In some embodiments, each hollow portion HP3 formed by performing the etching process EH3 has a width W _HP3 .

In some implementations, the etching process EH3 may be, for example, wet etching, dry etching, a lithography process, or other suitable methods.

In some embodiments, the width W _HP3 of each hollow portion HP3 is equal to the width W _HP2 of each hollow portion HP2.

In step S106, the temperature sensitive material layer 130 is removed.

Please refer to Figure 1 and Figure 7. Figure 7 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. As shown in Figure 7, in this embodiment, the temperature sensitive material layer 130 located on the hard mask layer 120 is removed by performing an etching process EH4.

In some implementations, the etching process EH4 may be, for example, wet etching, dry etching, a lithography process or other suitable methods.

In step S107 , a plurality of hollow portions HP4 are formed on the target layer 110 by means of the hard mask layer 120 .

Please refer to FIG. 1 and FIG. 8. FIG. 8 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in FIG. 8, in this embodiment, a plurality of hollow portions HP4 are formed on a target layer 110. Specifically, the hollow portions HP4 penetrate the target layer 110, so that the substrate SUB is exposed. As shown in FIG. 8, in some embodiments, the target layer 110 is formed by performing an etching process EH5 and forming a plurality of hollow portions HP4 on the target layer 110 through a plurality of hollow portions HP3 of a hard mask layer 120. Specifically, the hard mask layer 120 is configured as a patterned mask for patterning the target layer 110. In some implementations, each of the hollow portions HP4 formed by performing the etching process EH5 has a width W _HP4 .

In some implementations, the etching process EH5 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In some embodiments, the width W _HP4 of each hollow portion HP4 is equal to the width W _HP3 of each hollow portion HP3.

In step S108, the hard mask layer 120 is removed.

Please refer to FIG. 1 and FIG. 8 again. As shown in FIG. 8, in this embodiment, the hard mask layer 120 on the target layer 110 is removed by performing an additional etching process, thereby forming the semiconductor device 100. As shown in FIG. 8, by sequentially performing steps S101 to S108, the semiconductor device 100 including the substrate SUB and the target layer 110 having a plurality of hollow portions HP4 can be manufactured.

In some embodiments, the width W _HP4 of each hollow portion HP4 is greater than the width W _HP1 of each hollow portion HP1. This means that the manufacturer does not need to define an etching pattern on the patterning etching mask 140 that is difficult to control in the patterning process of the prior art. Instead, the manufacturer can use the etching pattern PT1 that can maintain quality in the prior art, and then use the temperature-sensitive material layer 130 that can isotropically shrink with temperature changes as a patterning mask to pattern the target layer 110, thereby manufacturing a semiconductor device 100 including a satisfactory patterned target layer 110.

The following will describe in detail a method M2 for manufacturing a semiconductor device 200 according to another embodiment of the present disclosure.

Please refer to FIG. 9. FIG. 9 is a flow chart of a method M2 for manufacturing the semiconductor device 200 shown in FIG. 17 according to another embodiment of the present disclosure. The method M2 shown in FIG. 9 includes steps S201, S202, S203, S204, S205, S206, S207, S208, S209, and S210. For a better understanding of step S201, please refer to FIG. 9 and FIG. 10. For a better understanding of step S202 and step S203, please refer to FIG. 9 and FIG. 11. For a better understanding of step S204, please refer to FIG. 9 and FIG. 12. For a better understanding of step S205, please refer to FIG. 9 and FIG. 13. For a better understanding of step S206, please refer to FIG. 9 and FIG. 14. For a better understanding of step S207, please refer to FIG. 9 and FIG. 15. For a better understanding of step S208, please refer to FIG. 9 and FIG. 16. For a better understanding of step S209 and step S210, please refer to FIG. 9 and FIG. 17.

Step S201, step S202, step S203, step S204, step S205, step S206, step S207, step S208, step S209 and step S210 are described in detail below.

In step S201, a substrate SUB, a target layer 210, a mold layer 220, and a hard mask layer 230 are sequentially formed.

Please refer to FIG. 9 and FIG. 10. FIG. 10 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 200 according to another embodiment of the present disclosure. As shown in FIG. 10, a substrate SUB is provided in the present embodiment. A target layer 210 is formed on the substrate SUB. A mold layer 220 is formed on the target layer 210. A hard mask layer 230 is formed on the mold layer 220. As shown in FIG. 10, the hard mask layer 230 is located above the substrate SUB. The target layer 210 is located between the substrate SUB and the mold layer 220. The mold layer 220 is located between the target layer 210 and the hard mask layer 230. As shown in FIG. 2 , in this embodiment, a patterned etch mask 240 is provided on the hard mask layer 230. The patterned etch mask 240 has an etch pattern PT2. In some embodiments, the etch pattern PT2 penetrates the patterned etch mask 240. In some embodiments, the patterned etch mask 240 having the etch pattern PT2 exposes the hard mask layer 230.

In some embodiments, the target layer 210 may include, for example, polysilicon. However, any suitable material may be used.

In some embodiments, the target layer 210 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to be limited to the method of forming the target layer 210.

In some embodiments, the mold layer 220 may include, for example, a nitride material such as silicon nitride (SiO ₂ ) or titanium nitride (TiO ₂ ). However, any suitable material may be used.

In some embodiments, the casting layer 220 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to limit the method of forming the casting layer 220.

In some implementations, the hard mask layer 230 may include, for example, a nitride material such as silicon nitride (Si _x N _y ) or titanium nitride (Tix _{N y} ). However, any suitable material may be used.

In some embodiments, the hard mask layer 230 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to be limited to the method of forming the hard mask layer 230.

In some embodiments, the patterned etch mask 240 may be a material such as photoresist (PR) or quartz glass. However, any suitable material may be used.

In some embodiments, the patterned etch mask 240 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to be limited to the method of forming the patterned etch mask 240.

In some implementations, the etching pattern PT2 may have a plurality of hollowed portions.

In some embodiments, the etching pattern PT2 can be formed by any suitable method, such as photolithography or the like. The present disclosure is not intended to limit the method for forming the etching pattern PT2.

In step S202 , a plurality of hollow portions HP5 are formed on the hard mask layer 230 by patterning the etching mask 240 .

Please refer to FIG. 9 and FIG. 11. FIG. 11 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 200 according to another embodiment of the present disclosure. As shown in FIG. 11, in this embodiment, a plurality of hollow portions HP5 are formed on the hard mask layer 230. Specifically, the hollow portions HP5 penetrate the hard mask layer 230, so that the casting layer 220 is exposed. As shown in FIG. 11, in some embodiments, the hard mask layer 230 is subjected to an etching process EH6 so that the etching pattern PT2 of the patterned etching mask 240 is transferred to the hard mask layer 230 to form a plurality of hollow portions HP5. In some implementations, each hollow portion HP5 formed by performing the etching process EH6 has a width W _HP5 .

In some implementations, the etching process EH6 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In step S203, the patterned etching mask 240 is removed.

Please continue to refer to FIG. 9 and FIG. 11. As shown in FIG. 11, in this embodiment, the patterned etching mask 240 on the hard mask layer 230 is removed by performing an additional etching process.

In step S204 , a plurality of hollow portions HP6 are formed on the casting layer 220 by means of the hard mask layer 230 .

Please refer to FIG. 9 and FIG. 12. FIG. 12 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 200 according to another embodiment of the present disclosure. As shown in FIG. 12, in this embodiment, a plurality of hollow portions HP6 are formed on the mold layer 220. Specifically, the hollow portions HP6 penetrate the mold layer 220, so that the target layer 210 is exposed. As shown in FIG. 12, in some embodiments, the mold layer 220 is formed by performing an etching process EH7 and forming a plurality of hollow portions HP6 on the mold layer 220 through a plurality of hollow portions HP5 of a hard mask layer 230. In some implementations, each hollow portion HP6 formed by performing the etching process EH7 has a width W _HP6 .

In some implementations, the etching process EH7 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In some embodiments, the width W _HP6 of each hollow portion HP6 is equal to the width W _HP5 of each hollow portion HP5.

In step S205, the hard mask layer 230 is removed.

Please refer to Figure 9 and Figure 13. Figure 13 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 200 according to another embodiment of the present disclosure. As shown in Figure 13, in this embodiment, the hard mask layer 230 located on the mold layer 220 is removed by performing an etching process EH8.

In some implementations, the etching process EH8 may be, for example, wet etching, dry etching, a lithography process, or other suitable methods.

In step S206 , the temperature sensitive material layer 250 is filled into the plurality of hollow portions HP6 of the casting layer 220 .

Please refer to FIG. 9 and FIG. 14. FIG. 14 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 200 according to another embodiment of the present disclosure. As shown in FIG. 14, in this embodiment, after the mold layer 220 forms a plurality of hollow portions HP6, the temperature-sensitive material layer 250 is filled in the plurality of hollow portions HP6, so that the hollow portions HP6 are backfilled. As shown in FIG. 14, in some embodiments, the temperature-sensitive material layer 250 is filled with the plurality of hollow portions HP6 by performing a filling process RF.

In some embodiments, the temperature sensitive material layer 250 may be, for example, a temperature sensitive material, such as a thermal expansion material or a negative thermal expansion material (NTE). However, any suitable temperature sensitive material may be used.

In some embodiments, the temperature sensitive material layer 250 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to limit the method of forming the temperature sensitive material layer 250.

In step S207 , the casting layer 220 is removed to form a plurality of hollow portions HP7 in the casting layer 220 .

Please refer to FIG. 9 and FIG. 15. FIG. 15 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 200 according to another embodiment of the present disclosure. As shown in FIG. 15, in this embodiment, the mold layer 220 is removed and the temperature-sensitive material layer 250 is left. Specifically, the mold layer 220 is removed by performing an etching process EH9, and the temperature-sensitive material layer 250 is left unremoved, so that a plurality of hollow portions HP7 are formed in situ where the mold layer 220 was originally located. In some embodiments, the hollow portion HP7 is defined by the temperature-sensitive material layer 250 and causes the target layer 210 to be exposed.

In some embodiments, each hollow portion HP7 formed by performing the etching process EH9 has a width W _HP7 , but the present disclosure is not limited thereto.

In some embodiments, since each hollow portion HP7 has a width W _HP7 through the etching process EH9 in step S207 , the temperature sensitive material layer 250 correspondingly has a critical dimension CD3 .

In some embodiments, the width W _HP7 of each hollow portion HP7 is greater than the width W _HP6 of each hollow portion HP6.

In step S208, the temperature sensitive material layer 250 is heated to form a plurality of hollow portions HP8.

Please refer to FIG. 9 and FIG. 16 again. FIG. 16 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 200 according to another embodiment of the present disclosure. As shown in FIG. 16, in this embodiment, a hollow portion HP8 is formed on the temperature-sensitive material layer 250. Specifically, the hollow portion HP8 penetrates the temperature-sensitive material layer 250, so that the target layer 210 is exposed. As shown in FIG. 16, in some embodiments, the temperature-sensitive material layer 250 is formed into a plurality of hollow portions HP8 by performing a temperature control process HT2. Specifically, when the temperature control process HT2 is performed, the temperature sensitive material layer 250 is deformed as the temperature changes, so that the hollow portion HP8 is formed in situ at the hollow portion HP7.

In some embodiments, each hollow portion HP8 formed by performing the temperature control process HT2 has a width W _HP8 .

In some embodiments, since each hollow portion HP8 has a width W _HP8 through the temperature control process HT2 in step S208 , the temperature sensitive material layer 250 correspondingly has a critical dimension CD4 .

In some embodiments where the temperature sensitive material layer 250 is a negative thermal expansion material, the temperature control process HT2 may be a process of temperature rise (e.g., heating), and the temperature sensitive material layer 250 is heated and shrinks, so that the width W _HP8 of each hollow portion HP8 is greater than the width W _HP7 of each hollow portion HP7 (i.e., the critical dimension CD4 of the temperature sensitive material layer 250 is less than the critical dimension CD3 of the temperature sensitive material layer 250), but the present disclosure is not limited thereto. In some embodiments where the temperature sensitive material layer 250 is a positive thermal expansion material (Positive Thermal Expansion Material), the temperature control process HT2 may be a process of temperature drop, which also falls within the spirit and scope of the present case.

In step S209 , a plurality of hollow portions HP9 are formed on the target layer 210 by using the temperature sensitive material layer 250 .

Please refer to FIG. 9 and FIG. 17. FIG. 17 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in FIG. 17, in this embodiment, a plurality of hollow portions HP9 are formed on a target layer 210. Specifically, the hollow portion HP9 penetrates the target layer 210, so that the substrate SUB is exposed. As shown in FIG. 17, in some embodiments, the target layer 210 is formed by performing an etching process EH10, and a plurality of hollow portions HP9 are formed on the target layer 210 through a plurality of hollow portions HP8 defined by a temperature-sensitive material layer 250. Specifically, the temperature-sensitive material layer 250 is configured as a patterned mask for patterning the target layer 210. In some implementations, each hollow portion HP9 formed by performing the etching process EH10 has a width W _HP9 .

In some implementations, the etching process EH10 may be, for example, wet etching, dry etching, lithography, or other suitable methods.

In some embodiments, the width W _HP9 of each hollow portion HP9 is equal to the width W _HP8 of each hollow portion HP8.

In step S210, the temperature sensitive material layer 250 is removed.

Please refer to FIG. 9 and FIG. 17 again. As shown in FIG. 17, in this embodiment, the temperature sensitive material layer 250 on the target layer 210 is removed by performing an additional etching process, thereby forming the semiconductor device 200. As shown in FIG. 17, by sequentially performing steps S201 to S210, a semiconductor device 200 including a substrate SUB and a target layer 210 having a plurality of hollow portions HP9 can be manufactured.

In some embodiments, the width W _HP9 of each hollow portion HP9 is greater than the width W _HP5 of each hollow portion HP5. This means that the manufacturer does not need to define an etching pattern on the patterning etching mask 240 that is difficult to control in the patterning process of the prior art, but can use the etching pattern PT2 that can maintain quality in the prior art, and then use the temperature-sensitive material layer 250 that can isotropically shrink with temperature changes as a patterning mask to pattern the target layer 210, so as to manufacture a semiconductor device 200 including a satisfactory patterned target layer 210.

By executing the method M1 shown in FIG. 1 and the method M2 shown in FIG. 9 of the present disclosure, the semiconductor device 100 and the semiconductor device 200 having better electrical performance can be formed.

From the above detailed description of the specific implementation of the present disclosure, it can be clearly seen that in the manufacturing method of the semiconductor element disclosed in the present disclosure, since the temperature-sensitive material layer can be isotropically contracted with temperature changes, the complicated step of precisely adjusting the etching pattern of the patterned etching mask can be omitted. In the manufacturing method of the semiconductor element disclosed in the present disclosure, since the temperature-sensitive material layer that can produce a volume change with temperature is configured as a patterned mask of the target layer, the pattern of the target layer can meet satisfactory requirements. The manufacturing method of the semiconductor element disclosed in the present disclosure not only greatly improves the process window, but also improves the electrical performance of the semiconductor element.

Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

The above content summarizes the features of several implementation methods so that those familiar with this technology can better understand the state of this case. Those familiar with this technology should understand that without departing from the spirit and scope of this case, the above content can be easily used as a basis for designing or modifying other changes to implement the same purpose and/or achieve the same advantages of the implementation methods introduced in this article. The above content should be understood as an example of this disclosure, and its protection scope should be based on the scope of the patent application.

100,200: semiconductor device 110,210: target layer 120,230: hard mask layer 130,250: temperature sensitive material layer 140,240: patterned etching mask 220: casting layer CD1,CD2,CD3,CD4: critical dimensions EH1,EH2,EH3,EH4,EH5,EH6,EH7,EH8,EH9,EH10: etching process HP1,HP2,HP3,HP4,HP5, HP6, HP7, HP8, HP9: hollowing part HT1, HT2: temperature control process M1, M2: method PT1, PT2: etching pattern RF: filling process S101, S102, S103, S104, S105, S106, S107, S108, S201, S202, S203, S204, S205, S206, S207, S208, S209, S210: step SUB: substrate W _HP1 , W _HP2 , W _HP3 , W _HP4 , W _HP5 , W _HP6 , W _HP7 , W _HP8 , W _HP9 : width

In order to make the above and other purposes, features, advantages and implementation methods of the present disclosure more clearly understandable, the attached drawings are described as follows: FIG. 1 is a flow chart showing a method for manufacturing a semiconductor element according to an implementation method of the present disclosure. FIG. 2 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. FIG. 3 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. FIG. 4 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. FIG. 5 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. FIG. 6 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. FIG. 7 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to one embodiment of the present disclosure. FIG. 8 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to one embodiment of the present disclosure. FIG. 9 is a flow chart showing a method for manufacturing a semiconductor element according to another embodiment of the present disclosure. FIG. 10 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to another embodiment of the present disclosure. FIG. 11 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to another embodiment of the present disclosure. FIG. 12 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to another embodiment of the present disclosure. FIG. 13 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to another embodiment of the present disclosure. FIG. 14 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure. FIG. 15 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure. FIG. 16 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure. FIG. 17 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

M1: Methods

S101, S102, S103, S104, S105, S106, S107, S108: Steps

Claims (10)

A method for manufacturing a semiconductor element comprises: sequentially forming a substrate, a target layer, a hard mask layer and a temperature-sensitive material layer, wherein the temperature-sensitive material layer is located above the substrate, the target layer is located between the substrate and the hard mask layer, and the hard mask layer is located between the target layer and the temperature-sensitive material layer; forming a plurality of first hollow portions on the temperature-sensitive material layer by a patterned etching mask; removing the patterned etching mask; heating the temperature-sensitive material layer to form a plurality of second hollow portions in situ at the first hollow portions; forming a plurality of third hollow portions on the hard mask layer by the temperature-sensitive material layer; removing the temperature-sensitive material layer; Forming a plurality of fourth cutouts on the target layer by using the hard mask layer; and removing the hard mask layer. A method as described in claim 1, wherein a width of each of the second hollow portions is greater than a width of each of the first hollow portions. A method as described in claim 2, wherein a width of each of the third hollow portions and a width of each of the fourth hollow portions are the same as the width of each of the second hollow portions. A method as described in claim 2, wherein one of the materials of the temperature sensitive material layer is a negative thermal expansion material. The method as described in claim 1, wherein the step of heating the temperature-sensitive material layer is performed before the step of forming the fourth hollow portions on the target layer through the hard mask layer. A method for manufacturing a semiconductor element, comprising: Sequentially forming a substrate, a target layer, a mold layer and a hard mask layer, wherein the hard mask layer is located above the substrate, the target layer is located between the substrate and the mold layer, and the mold layer is located between the target layer and the hard mask layer; Forming a plurality of first hollow portions on the hard mask layer by a patterned etching mask; Removing the patterned etching mask; Forming a plurality of second hollow portions on the mold layer by the hard mask layer; Removing the hard mask layer; Filling a temperature-sensitive material layer in the second hollow portions of the mold layer; The casting layer is removed to form a plurality of third hollow portions in situ at the casting layer; The temperature-sensitive material layer is heated to form a plurality of fourth hollow portions in situ at the third hollow portions; A plurality of fifth hollow portions are formed on the target layer by the temperature-sensitive material layer; and The temperature-sensitive material layer is removed. A method as described in claim 6, wherein a width of each of the fourth hollow portions is greater than a width of each of the third hollow portions. A method as described in claim 7, wherein a width of each of the fifth hollow portions is the same as the width of each of the fourth hollow portions. A method as described in claim 7, wherein one material of the temperature sensitive material layer is a negative thermal expansion material. The method as described in claim 6, wherein the step of heating the temperature-sensitive material layer is performed before the step of forming the fifth hollow portions on the target layer through the temperature-sensitive material layer.

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