TWI898351B - Method of forming semiconductor structure - Google Patents

Abstract

A semiconductor structure includes a semiconductor substrate, and a heat dissipating component disposed on a surface of the semiconductor substrate. The heat dissipating component includes a plurality of protrusions. Each of the protrusions includes a plurality of first sections and a plurality of second sections, wherein a dimension of the first sections is different from a dimension of the second sections. A method of forming the semiconductor structure is also disclosed.

Description

Method for manufacturing semiconductor structure

This disclosure relates to a semiconductor structure and a method for manufacturing the same.

High performance, high power, high density, and high reliability are the development trends of electronic devices. However, as the energy consumption of electronic devices increases, the heat energy they generate also increases accordingly. Therefore, how to improve the heat dissipation capacity of electronic devices has become a topic of discussion.

According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising a semiconductor substrate and a heat sink disposed on a surface of the semiconductor substrate. The heat sink comprises protrusions, each of which comprises a first section and a second section, wherein the dimensions of the first section are different from the dimensions of the second section.

In some embodiments, the semiconductor structure further includes an interpad silicon oxide layer disposed on a surface of the semiconductor substrate, and a seed layer disposed on the interpad silicon oxide layer, wherein the bottoms of the protrusions are connected through the seed layer.

In some embodiments, the protrusions are directly disposed on the surface of the semiconductor substrate, and the bottoms of the protrusions are separated from each other.

In some embodiments, the bottom of the protrusion is embedded in the surface of the semiconductor substrate.

In some embodiments, the semiconductor structure further includes a through-hole disposed in the semiconductor substrate, wherein the through-hole is connected to one or more of the protrusions.

According to another embodiment of the present disclosure, a semiconductor structure is provided, comprising a first semiconductor substrate, a second semiconductor substrate, and a heat sink. The first semiconductor substrate comprises a front surface and a back surface, and the second semiconductor substrate comprises a front surface and a back surface, wherein the front surface of the second semiconductor substrate is bonded to the front surface of the second semiconductor substrate. The heat sink is disposed on the back surface of the first semiconductor substrate and comprises a protrusion, the protrusion comprising a first section and a second section, wherein the dimensions of the first section are different from the dimensions of the second section.

In some embodiments, the first semiconductor substrate is a CMOS substrate and the second semiconductor substrate is an array substrate, or the first semiconductor substrate is an array substrate and the second semiconductor substrate is a CMOS substrate.

According to another embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: forming a sacrificial layer stack on a surface of a semiconductor substrate, wherein the sacrificial layer stack comprises a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately and repeatedly, and the material of the first sacrificial layers is different from the material of the second sacrificial layers; performing an anisotropic etching process on the sacrificial layer stack to form A trench is formed between a sacrificial layer structure, the sacrificial layer structure comprising a first sacrificial layer and a second sacrificial layer; an isotropic etching process is performed on the sacrificial layer structure to form a cavity between the first sacrificial layer and the second sacrificial layer; the trench and the cavity are filled with a thermally conductive material; and the sacrificial layer structure is removed, wherein the remaining portion of the thermally conductive material becomes a protrusion in a heat sink located on a surface of a semiconductor substrate.

In some embodiments, the sacrificial layer stack includes a plurality of third sacrificial layers, and the material of the third sacrificial layer is different from the material of the first sacrificial layer, and the material of the third sacrificial layer is different from the material of the second sacrificial layer.

In some embodiments, the method for fabricating a semiconductor structure further includes: forming an inter-pad silicon oxide layer on a surface of a semiconductor substrate; and forming a seed layer on the inter-pad silicon oxide layer, wherein the step of filling the trenches and cavities with a thermally conductive material includes performing an electroplating process.

This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate and a heat sink disposed on the semiconductor substrate. The heat sink is fabricated using a semiconductor process and has a plurality of protrusions. Each protrusion has a corrugated side surface, thereby increasing the surface area of the protrusion and thereby improving the heat dissipation efficiency of the heat sink.

100:Semiconductor structure

110: Semiconductor substrate

110a: First semiconductor substrate

110b: Second semiconductor substrate

110c: Wafer

110d: Chip

110e: First chip

110f: Second chip

120: Inner pad silicon oxide layer

130:Seed layer

140: Sacrificial Layer Stacking

142: The First Sacrificial Layer

144: Second Sacrificial Layer

146: Sacrificial Layer Structure

148: The Third Sacrificial Layer

150: Groove

152: Cavity

154: Depression

160: Thermal conductive material

200: Heat dissipation element

210: Protrusion

212: First paragraph

214: Second paragraph

216: Third paragraph

220: Through hole

222: Adhesive layer

224: Conductor Core

230:Connection pad

S10, S12, S14, S16, S18, S20, S22, S30, S32, S34, S36, S38, S40, S42, S44: Steps

Lx: Width

Ly: Length

H: Height

S: Spacing

FS: Front

BS: Back

To make the purpose, features, advantages and embodiments of this disclosure more clearly understood, the attached drawings are described in detail as follows:

Figure 1 is a perspective view of some embodiments of the semiconductor structure according to the present disclosure.

Figure 2 is a top view of the semiconductor structure in Figure 1.

Figure 3 is a cross-sectional view of the semiconductor structure in Figure 1.

Figures 4 to 10 are cross-sectional views of some embodiments of the semiconductor structure fabrication method disclosed herein at different stages.

Figures 11 to 15 are cross-sectional views of some embodiments of the semiconductor structure fabrication method disclosed herein at different stages.

Figures 16 to 18 are cross-sectional views of some embodiments of the semiconductor structure fabrication method disclosed herein at different stages.

Figures 19A to 19E are schematic top views of different embodiments of the protrusions of the heat sink in the semiconductor structure according to the present disclosure.

Figures 20A and 20B are schematic top views of different embodiments of the protrusions of the heat sink in the semiconductor structure according to the present disclosure.

Figure 21 is a cross-sectional view of some embodiments of the semiconductor structure according to the present disclosure.

Figures 22 and 23 are cross-sectional views of different embodiments of the semiconductor structure according to the present disclosure.

Figure 24 is a schematic top view of some embodiments of the semiconductor structure according to the present disclosure.

Figure 25 is a schematic top view of some embodiments of the semiconductor structure according to the present disclosure.

The following diagrams and detailed descriptions clearly illustrate the spirit of this disclosure. After understanding the preferred embodiments of this disclosure, anyone skilled in the art can make changes and modifications based on the techniques taught by this disclosure without departing from the spirit and scope of this disclosure.

Referring to Figures 1 to 3 , Figure 1 is a perspective view of some embodiments of semiconductor structures according to the present disclosure, Figure 2 is a top view of the semiconductor structure in Figure 1 , and Figure 3 is a cross-sectional view of the semiconductor structure in Figure 1 . The present disclosure provides a semiconductor structure 100 having a heat sink 200 . The semiconductor structure 100 includes a semiconductor substrate 110 , an inter-pad silicon oxide layer 120 disposed on a surface of the semiconductor structure 100 , and a heat sink 200 disposed on the inter-pad silicon oxide layer 120 . The heat sink 200 is made of a material with high thermal conductivity and is integrally formed. More specifically, the heat sink 200 includes a plurality of protrusions 210 standing upright on the seed layer 130 on the inner pad silicon oxide layer 120, wherein the inner pad silicon oxide layer 120 is on the surface of the semiconductor structure 100. Each protrusion 210 has a corrugated side surface to increase the surface area of the protrusion 210, thereby improving the heat exchange efficiency of the heat sink 200.

In some embodiments, the semiconductor substrate 110 may be or include a bulk semiconductor substrate (i.e., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or other suitable substrate materials. In some embodiments, the semiconductor substrate 110 may include one or more doped regions. In some embodiments, the semiconductor substrate 110 may include integrated circuits and/or semiconductor devices. In some embodiments, the semiconductor substrate 110 may be a wafer or a chip.

In some embodiments, the heat sink 200 is fabricated through a series of semiconductor processes, including deposition, lithography, and etching. In some embodiments, the protrusion 210 of each heat sink 200 includes multiple first segments 212 and multiple second segments 214, with the first segments 212 having larger dimensions than the second segments 214. For example, the first segments 212 and the second segments 214 may be rectangular, with the width or length (Lx or Ly) of the first segment 212 being larger than the width or length of the second segment 214.

In some embodiments, to provide better heat dissipation without increasing the space required for the heat sink 200, the height H of each protrusion 210 is in the range of 100 μm to 5000 μm, the spacing S between adjacent protrusions 210 is in the range of 50 μm to 500 μm, and the width Lx or length Ly of each protrusion 210 is in the range of 50 μm to 50 mm.

The spacing S between adjacent protrusions 210 can be considered a flow channel for a medium to pass through and exchange heat with the corrugated side surfaces of the protrusions 210 of the heat sink 200. In some embodiments, the heat sink 200 is an air-cooled heat sink, and the medium passing through the spacing S is air. In some embodiments, the heat sink 200 is a water-cooled heat sink, and the medium passing through the spacing S is fluid.

Refer to Figures 4 to 10, which are cross-sectional views of some embodiments of the method for manufacturing a semiconductor structure disclosed herein at different stages. The method for manufacturing a semiconductor structure begins with step S10, providing a semiconductor substrate 110. The semiconductor substrate 110 may be or include a bulk semiconductor substrate (i.e., a bulk silicon substrate), a silicon-on-insulator substrate, or other suitable substrate materials. In some embodiments, the semiconductor substrate 110 may include one or more doped regions. In some embodiments, the semiconductor substrate 110 may include an integrated circuit and/or semiconductor elements. In some embodiments, the semiconductor substrate 110 may be a wafer or a chip. In some embodiments, a thinning process may be performed on the semiconductor substrate 110 to reduce the thickness of the semiconductor substrate 110.

In step S10, an inter-pad silicon oxide layer 120 is deposited on the surface of the semiconductor substrate 110. Then, a seed layer 130 is further deposited on the inter-pad silicon oxide layer 120. In some embodiments, the inter-pad silicon oxide layer 120 is made of silicon dioxide, and the seed layer 130 is made of a metal, such as copper. The inter-pad silicon oxide layer 120 serves as a blanket layer to prevent the copper in the seed layer 130 from diffusing into the semiconductor substrate 110. In some embodiments, the seed layer 130 can be a single layer or a multi-layer structure, and the seed layer 130 has good adhesion to the semiconductor substrate 110.

Referring to FIG. 5 , in step S12, a sacrificial layer stack 140 is formed on the seed layer 130. The sacrificial layer stack 140 includes a plurality of first sacrificial layers 142 and a plurality of second sacrificial layers 144, wherein the first sacrificial layers 142 and the second sacrificial layers 144 are alternately and repeatedly stacked. In some embodiments, the first sacrificial layers 142 and the second sacrificial layers 144 can be formed by multiple cycles of deposition processes, and the thickness of the first sacrificial layers 142 and the second sacrificial layers 144 ranges from tens of nanometers to tens of millimeters. In some embodiments, the thicknesses of the first sacrificial layer 142 and the second sacrificial layer 144 may be the same or different.

The first sacrificial layer 142 and the second sacrificial layer 144 are made of a dielectric material. The material of the first sacrificial layer 142 is different from the material of the second sacrificial layer 144 to provide sufficient etching selectivity between the first sacrificial layer 142 and the second sacrificial layer 144. For example, the material of the first sacrificial layer 142 can be an oxide, such as silicon dioxide, and the material of the second sacrificial layer 144 can be a nitride, such as silicon nitride.

Referring to FIG. 6 , in step S14 , an anisotropic etching process is performed to pattern the sacrificial layer stack 140 . The anisotropic etching process is directional and has substantially the same etching rate for the first sacrificial layer 142 and the second sacrificial layer 144 . The anisotropic etching process stops at the seed layer 130 . In some embodiments, the anisotropic etching process removes a portion of the sacrificial layer stack 140 . The removed portion of the sacrificial layer stack 140 may be in a grid-like or linear pattern, thereby forming grid-like or linear trenches 150 in the sacrificial layer stack 140 . After the anisotropic etching process is performed, a plurality of sacrificial layer structures 146 are formed on the seed layer 130. Trenches 150 are formed between the sacrificial layer structures 146. The side surfaces of the first sacrificial layer 142 and the second sacrificial layer 144 of the sacrificial layer structures 146 are exposed through the trenches 150.

Referring to FIG. 7 , in step S16 , an isotropic etching process is performed. The etchant used in the isotropic etching process has an etching selectivity between the first sacrificial layer 142 and the second sacrificial layer 144 . For example, in some embodiments, the etchant used in the isotropic etching process may be hot phosphoric acid, which has a much higher etching rate for silicon nitride than for silicon dioxide. Therefore, after the isotropic etching process, the second sacrificial layer 144 is recessed relative to the first sacrificial layer 142 , forming a cavity 152 between the first and second sacrificial layers 142 , 144 .

In some other embodiments, the etchant used in the isotropic etching process may be a buffered oxide etchant (BOE), which has a much higher etching rate for silicon dioxide than for silicon nitride. Therefore, after the isotropic etching process, the first sacrificial layer 142 is recessed relative to the second sacrificial layer 144.

Preferably, the topmost layer in the sacrificial structure 146 is recessed relative to the underlying layers. For example, if the topmost layer in the sacrificial structure 146 is the first sacrificial layer 142 (i.e., silicon dioxide), the etchant used in the isotropic etching process is a buffer oxide etchant. If the topmost layer in the sacrificial structure 146 is the second sacrificial layer 144 (i.e., silicon nitride), the etchant used in the isotropic etching process is hot phosphoric acid.

After performing the isotropic etching process, the side surfaces of the first sacrificial layer 142 and the second sacrificial layer 144 can be flat, convex, or concave, depending on the conditions of the isotropic etching process.

Referring to FIG. 8 , in step S18 , a thermally conductive material 160 is provided to fill the trenches 150 (shown in FIG. 7 ) between the sacrificial layer structures 146 and the cavity 152 (shown in FIG. 7 ) between the first sacrificial layer 142 and the second sacrificial layer 144 . The thermally conductive material 160 covers the upper surface of the sacrificial layer structures 146 .

In some embodiments, the thermally conductive material 160 is made of metal. For example, the thermally conductive material 160 may include silver, copper, gold, aluminum, or tungsten. The thermally conductive material 160 may be formed on the seed layer 130 through an electroplating process.

Referring to FIG. 9 , in step S20 , a planarization process, such as a chemical mechanical polishing process, is performed to remove a portion of the thermally conductive material 160 . After the planarization process is completed, the upper surface of the sacrificial layer structure 146 is exposed by the thermally conductive material 160 .

Referring to FIG. 10 , in step S22 , a removal process is performed to remove the sacrificial layer structure 146 (shown in FIG. 9 ). The remaining thermally conductive material 160 (shown in FIG. 9 ) becomes the protrusion 210 of the heat sink 200 . The bottoms of the protrusions 210 of the heat sink 200 are connected together through the seed layer 130 . The removal process includes removing the first sacrificial layer 142 using a first isotropic etch process and removing the second sacrificial layer 144 using a second isotropic etch process.

Each protrusion 210 includes alternating first segments 212 and second segments 214, wherein the dimensions of the first segments 212 are different from the dimensions of the second segments 214. More specifically, the first segments 212 and the second segments 214 are defined by the contours of the isotropically etched first and second sacrificial layers 142 and 144 (as shown in FIG. 7 ).

In some other embodiments, the heat sink 200 can be made of a non-metallic thermally conductive material, and thus the inner pad silicon oxide layer and the seed layer can be omitted.

Referring to Figures 11 to 15 , they are cross-sectional views of various stages of some embodiments of the semiconductor structure fabrication method disclosed herein. As shown in Figure 11 , the semiconductor structure fabrication method begins with step S30, wherein a sacrificial layer stack 140 is formed directly on a semiconductor substrate 110. The sacrificial layer stack 140 includes a first sacrificial layer 142 and a second sacrificial layer 144, with the first sacrificial layer 142 and the second sacrificial layer 144 being stacked in an alternating and repeated arrangement. The material of the first sacrificial layer 142 is different from the material of the second sacrificial layer 144 to provide a sufficient etching selectivity between the first sacrificial layer 142 and the second sacrificial layer 144. For example, the material of the first sacrificial layer 142 can be an oxide, such as silicon dioxide, and the material of the second sacrificial layer 144 can be a nitride, such as silicon nitride.

Referring to FIG. 12 , in step S32 , an anisotropic etching process is performed to pattern the sacrificial layer stack 140 . After the anisotropic etching process is completed, trenches 150 are formed between the sacrificial layer structures 146 . In some embodiments, the anisotropic etching process stops at the semiconductor substrate 110 . Therefore, after the anisotropic etching process is completed, a plurality of recesses 154 are formed on the top surface of the semiconductor substrate 110 .

Referring to FIG. 13 , in step S34 , an isotropic etching process is performed. The etchant used in the isotropic etching process has an etching selectivity between the first sacrificial layer 142 and the second sacrificial layer 144 . For example, in some embodiments, the etchant used in the isotropic etching process may be hot phosphoric acid, which has a much higher etching rate for silicon nitride than for silicon dioxide. Therefore, after the isotropic etching process, the second sacrificial layer 144 is recessed relative to the first sacrificial layer 142 , forming a cavity 152 between the first and second sacrificial layers 142 , 144 .

In some other embodiments, the etchant used in the isotropic etching process may be a buffered oxide etchant, which has a much higher etching rate for silicon dioxide than for silicon nitride. Therefore, after the isotropic etching process, the first sacrificial layer 142 is recessed relative to the second sacrificial layer 144.

Referring to FIG. 14 , in step S36 , a thermally conductive material 160 is provided to fill the trenches 150 between the sacrificial layer structures 146 (as shown in FIG. 13 ) and the cavities 152 between the first sacrificial layer 142 and the second sacrificial layer 144 (as shown in FIG. 13 ). The thermally conductive material 160 further fills the recess 154 on the top surface of the semiconductor substrate 110 (as shown in FIG. 13 ).

In some embodiments, thermally conductive material 160 may be made of a graphite sheet. In some embodiments, thermally conductive material 160 may be made of a phase change material. In some embodiments, thermally conductive material 160 may be made of a metal paste. In some embodiments, thermally conductive material 160 may be made of a heat sink or thermal paste. In some embodiments, thermally conductive material 160 may be made of aluminum nitride. Thermally conductive material 160 may be formed by deposition, filling, or any other suitable process.

Referring to FIG. 15 , in step S38 , a planarization process is performed to remove a portion of the thermally conductive material 160 , exposing the upper surface of the sacrificial layer structure 146 (shown in FIG. 14 ) from the thermally conductive material 160 . A removal process is then performed to remove the sacrificial layer structure 146 . The heat sink 200 having protrusions 210 is formed directly on the semiconductor substrate 110 . Each protrusion 210 includes alternating first segments 212 and second segments 214 , wherein the dimensions of the first segments 212 are different from those of the second segments 214 . The bottoms of the protrusions 210 are separated from each other and embedded in the semiconductor substrate 110 . The bottoms of these protrusions 210 embedded in the semiconductor substrate 110 can provide more contact area between the semiconductor substrate 110 and the protrusions 210, thereby increasing the heat exchange area between the semiconductor substrate 110 and the protrusions 210.

In some other embodiments, by changing the composition of the sacrificial layer stack 140, the side surface of the protrusion 210 of the heat sink 200 can become more irregular.

Referring to Figures 16 to 18 , which are cross-sectional views of various stages of a method for fabricating a semiconductor structure according to the present disclosure, as shown in Figure 16 , the method for fabricating a semiconductor structure begins with step S40 , wherein a sacrificial layer stack 140 is formed directly on the semiconductor substrate 110 or on the seed layer 130 (if any). The sacrificial layer stack 140 includes a plurality of first sacrificial layers 142 , a plurality of second sacrificial layers 144 , and a plurality of third sacrificial layers 148 , although only one second sacrificial layer 144 and one third sacrificial layer 148 are shown in the figure. The first sacrificial layer 142, the second sacrificial layer 144, and the third sacrificial layer 148 are made of different materials. For example, the first sacrificial layer 142, the second sacrificial layer 144, and the third sacrificial layer 148 can be made of _SiO2 , SiN, SiON, SiCN, or other materials that can provide a suitable etching selectivity.

In some embodiments, the number and order of the first sacrificial layer 142, the second sacrificial layer 144, and the third sacrificial layer 148 can be varied as needed, and the thicknesses of the first sacrificial layer 142, the second sacrificial layer 144, and the third sacrificial layer 148 can also vary. Thus, the variety of sacrificial layer stacks 140 can be further increased.

Referring to FIG. 17 , in step S42 , the sacrificial layer stack 140 is patterned through a series of anisotropic and isotropic etching processes. Due to the etching selectivity between the materials of the first, second, and third sacrificial layers 142, 144, and 148 in the sacrificial layer stack 140, the shape of the sacrificial layer structure 146 can be more irregular, and the spacing between the first, second, and third sacrificial layers 142, 144, and 148 in the sacrificial layer structure 146 also becomes more non-uniform.

Referring to FIG. 18 , in step S44 , a plurality of protrusions 210 defined by the sacrificial layer structure 146 are formed on the semiconductor substrate 110 or the seed layer 130 (if any). The protrusions 210 include a plurality of first segments 212 , a plurality of second segments 214 , and a plurality of third segments 216 , although only one second segment 214 and one third segment 216 are shown. The thickness and/or dimensions of the first, second, and third segments 212 , 214 , 216 may vary. Each protrusion 210 of the heat sink 200 has an increased lateral surface area, thereby enhancing the heat dissipation efficiency of the heat sink 200 .

Referring to Figures 19A to 19E , they are top views of various embodiments of the protrusion of the heat sink in the semiconductor structure according to the present disclosure. In some embodiments, the top cross-sectional shape of the protrusion 210 of the heat sink 200 is not limited to a rectangle or a square. In some embodiments, the protrusion 210 of the heat sink 200 may be misaligned or asymmetric with respect to the X-axis or Y-axis of the heat sink 200. For example, the top cross-sectional shape of the protrusion 210 of the heat sink 200 may be circular (as shown in Figure 19A ), triangular (as shown in Figure 19B ), polygonal (as shown in Figure 19C ), parallelogram (as shown in Figure 19D ), or rhombus (as shown in Figure 19E ).

Referring to FIG. 20A and FIG. 20B , they are top views of different embodiments of the protrusion of a heat sink in a semiconductor structure according to the present disclosure. In some embodiments, the protrusion 210 of the heat sink 200 may be in the shape of an elongated strip (as shown in FIG. 20A ) or a fin (as shown in FIG. 20B ).

Refer to FIG. 21 , which is a cross-sectional view of some embodiments of a semiconductor structure according to the present disclosure. In some embodiments, the semiconductor structure 100 further includes a plurality of vias 220 disposed in the semiconductor substrate 110 and connected to the heat sink 200. Each via 220 can be connected to one or more protrusions 210 of the heat sink 200. Each via 220 can include a conductive core 224 and an adhesive layer 222 disposed between the conductive core 224 and the semiconductor substrate 110. The vias 220 are virtual vias that do not provide electrical connection or conduction. The vias 220 in the semiconductor substrate 110 can provide additional heat exchange paths, thereby enhancing the heat dissipation efficiency of the semiconductor structure 100.

Referring to Figures 22 and 23 , which are cross-sectional views of different embodiments of semiconductor structures according to the present disclosure, the semiconductor structure 100 includes a first semiconductor substrate 110a and a second semiconductor substrate 110b , wherein the front surface FS of the first semiconductor substrate 110a is bonded to the front surface FS of the second semiconductor substrate 110b . In some embodiments, the first semiconductor substrate 110a may be a CMOS wafer containing multiple CMOS devices, while the second semiconductor substrate 110b may be an array wafer containing a staircase interconnect structure. Therefore, the semiconductor structure 100 may also be referred to as a CMOS bonding array (CbA) structure.

As shown in FIG. 22 , in some embodiments, the heat sink 200 can be disposed on the back surface BS of the first semiconductor substrate 110 a (i.e., the CMOS wafer), while the connection pads 230 of the semiconductor structure 100 can be disposed on the back surface BS of the second semiconductor substrate 110 b (i.e., the array wafer).

As shown in FIG. 23 , in some embodiments, the heat sink 200 can be disposed on the back surface BS of the second semiconductor substrate 110 b (i.e., the array wafer), while the connection pads 230 of the semiconductor structure 100 can be disposed on the back surface BS of the first semiconductor substrate 110 a (i.e., the CMOS wafer).

Referring to FIG. 24 , which is a schematic top view of some embodiments of a semiconductor structure according to the present disclosure, in some embodiments, semiconductor structure 100 may be a wafer-to-die structure, comprising a wafer 110c and a plurality of dies 110d bonded to wafer 110c. The aforementioned heat sink (not shown) may be disposed on the semiconductor substrate of wafer 110c or dies 110d.

Referring to FIG. 25 , which is a schematic top view of some embodiments of a semiconductor structure according to the present disclosure, in some embodiments, the semiconductor structure 100 may be a chip-on-chip structure, comprising a first chip 110e and a second chip 110f bonded to the first chip 110e. The aforementioned heat sink (not shown) may be disposed on the semiconductor substrate of either the first chip 110e or the second chip 110f.

This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate and a heat sink disposed on the semiconductor substrate. The heat sink is fabricated using a semiconductor process and has a plurality of protrusions. Each protrusion has a corrugated side surface, thereby increasing the surface area of the protrusion and thereby improving the heat dissipation efficiency of the heat sink.

Although the present disclosure has been disclosed above through embodiments, they are not intended to limit the present disclosure. Anyone skilled in the art may make various modifications and improvements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of the attached patent application.

100: Semiconductor structure 110: Semiconductor substrate 120: Inter-pad silicon oxide layer 130: Seed layer 200: Heat sink 210: Protrusion 212: First section 214: Second section

Claims (10)

A method for fabricating a semiconductor structure comprises: forming a sacrificial layer stack on a surface of a semiconductor substrate, the sacrificial layer stack comprising a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately and repeatedly, wherein the first sacrificial layers are made of a material different from that of the second sacrificial layers; performing an anisotropic etching process on the sacrificial layer stack to form a plurality of trenches between the plurality of sacrificial layer structures, the plurality of sacrificial layer structures comprising the first sacrificial layers and the second sacrificial layers; Performing an isotropic etching process on the sacrificial layer structures to form a plurality of cavities between the first sacrificial layers and the second sacrificial layers; Filling the trenches and the cavities with a thermally conductive material, wherein the step of filling the trenches and the cavities with the thermally conductive material comprises performing an electroplating process; and Removing the sacrificial layer structures to form a heat sink on the surface of the semiconductor substrate, the heat sink comprising a plurality of protrusions, each of the protrusions comprising a plurality of first segments and a plurality of second segments, wherein the dimensions of the first segments are different from the dimensions of the second segments. The method for manufacturing a semiconductor structure as described in claim 1, wherein the material of the protrusions includes silver, copper, gold, aluminum or tungsten. A method for manufacturing a semiconductor structure as described in claim 1, wherein the first segments and the second segments are arranged alternately. A method for manufacturing a semiconductor structure as described in claim 1, wherein the protrusions further include a plurality of third segments, wherein the dimensions of the third segments are different from the dimensions of the first segments or the second segments. The method for manufacturing a semiconductor structure as described in claim 1 further includes forming a through hole in the semiconductor substrate, wherein the through hole is connected to one or more of the protrusions. A method for fabricating a semiconductor structure comprises: forming an inter-pad silicon oxide layer on a back surface of a first semiconductor substrate; forming a seed layer on the inter-pad silicon oxide layer; forming a sacrificial layer stack on the seed layer, the sacrificial layer stack comprising a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately and repeatedly, wherein the materials of the first sacrificial layers are different from the materials of the second sacrificial layers; Performing an anisotropic etching process on the sacrificial layer stack to form a plurality of trenches between a plurality of sacrificial layer structures, the sacrificial layer structures comprising the first sacrificial layers and the second sacrificial layers; Performing an isotropic etching process on the sacrificial layer structures to form a plurality of cavities between the first sacrificial layers and the second sacrificial layers; Filling the trenches and the cavities with a thermally conductive material, wherein the step of filling the trenches and the cavities with the thermally conductive material comprises performing an electroplating process; The sacrificial layer structures are removed to form a heat sink disposed on the back surface of the first semiconductor substrate. The heat sink comprises a plurality of protrusions, each of which comprises a plurality of first segments and a plurality of second segments, wherein the dimensions of the first segments are different from the dimensions of the second segments. Furthermore, a front surface of the first semiconductor substrate is bonded to a front surface of a second semiconductor substrate. A method for manufacturing a semiconductor structure as described in claim 6, wherein the first semiconductor substrate is a CMOS substrate and the second semiconductor substrate is an array substrate, or the first semiconductor substrate is an array substrate and the second semiconductor substrate is a CMOS substrate. A method for fabricating a semiconductor structure comprises: forming an inter-pad silicon oxide layer on a surface of a semiconductor substrate; forming a seed layer on the inter-pad silicon oxide layer; forming a sacrificial layer stack on the seed layer, the sacrificial layer stack comprising a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately and repeatedly, wherein the materials of the first sacrificial layers are different from the materials of the second sacrificial layers; Performing an anisotropic etching process on the sacrificial layer stack to form a plurality of trenches between a plurality of sacrificial layer structures, the sacrificial layer structures comprising the first sacrificial layers and the second sacrificial layers; Performing an isotropic etching process on the sacrificial layer structures to form a plurality of cavities between the first sacrificial layers and the second sacrificial layers; Filling the trenches and the cavities with a thermally conductive material, wherein the step of filling the trenches and the cavities with the thermally conductive material comprises performing an electroplating process; and The sacrificial layer structures are removed, wherein the remaining portion of the thermally conductive material becomes a plurality of protrusions in a heat sink located on the surface of the semiconductor substrate, and the bottoms of the protrusions are connected through the seed layer. The method for manufacturing a semiconductor structure as described in claim 8, wherein the sacrificial layer stack includes a plurality of third sacrificial layers, and the material of the third sacrificial layers is different from the material of the first sacrificial layers, and the material of the third sacrificial layers is different from the material of the second sacrificial layers. The method for manufacturing a semiconductor structure as described in claim 8 further comprises: Thinning the semiconductor substrate.