CN109935568A - Semiconductor devices and preparation method thereof - Google Patents

Abstract

The present application discloses semiconductor devices and fabrication methods thereof. The first bonding layer and the second bonding layer of the semiconductor device are in contact with each other to provide the first wafer and the second wafer are bonded to each other, the contact surface of the first bonding layer and the second bonding layer is a bonding surface, the first conductive channel and The second conductive vias are connected to each other to provide electrical connection between the first wafer and the second wafer, the first wafer further including first dummy vias extending through the first bonding layer, and the second wafer further including second dummy vias extending through the second bonding layer The dummy vias, the first dummy vias and the second dummy vias are in contact with each other to improve the mechanical connection bonding force between the first wafer and the second wafer. In the semiconductor device, dummy vias connected to each other are formed in the bonding layers of the first wafer and the second wafer to improve the pattern distribution of the bonding surfaces of the two, thereby improving the bonding strength and reliability.

Description

Semiconductor device and method of making the same

technical field

The present invention relates to semiconductor technology, and more particularly, to semiconductor devices and methods of fabricating the same.

Background technique

The development direction of semiconductor technology is the reduction of feature size and the improvement of integration. For memory devices, the improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature sizes of semiconductor manufacturing processes are getting smaller and smaller, the storage density of memory devices is getting higher and higher.

In order to further increase the storage density, three-dimensionally structured storage devices (ie, 3D storage devices) have been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, and the integration degree can be doubled on a wafer per unit area, and the cost can be reduced. Further, semiconductor devices have been developed in which 3D memory device chips and driving circuit chips are bonded together. The semiconductor device can provide the read and write speed of the memory device, and can improve the integration level, reduce the cost of the device and improve the reliability.

In the above-described semiconductor device, the surfaces of the wafers in contact with each other are bonding surfaces. After the bonding surface of the wafer is cleaned and activated, it is clean and flat. The bonding surfaces of at least two wafers are in contact with each other, and under certain temperature and pressure conditions, the wafers are bonded together by van der Waals force, molecular force or even atomic force.

1 and 2 show schematic cross-sectional views of a semiconductor device according to the prior art. Semiconductor device 100 includes wafers 110 and 120 . The wafer 110 includes a semiconductor substrate 111 , and a functional layer 112 and a bonding layer 113 sequentially stacked on the semiconductor substrate 111 . The wafer 120 includes a semiconductor substrate 121 , and a functional layer 122 and a bonding layer 123 sequentially stacked on the semiconductor substrate 121 . Among them, the semiconductor substrate and the functional layer are collectively referred to as the substrate. The bonding layer 113 of the wafer 110 and the bonding layer 123 of the wafer 120 are respectively a dielectric layer, for example, composed of silicon dioxide. FIG. 1 shows a dielectric layer bonding process, and the bonding layers of the wafers 110 and 120 are bonded to each other by, for example, thermocompression bonding to form an integrated structure. FIG. 2 shows a hybrid bonding process, the wafers 110 and 120 respectively include conductive channels 114 and 124 aligned with each other, the bonding layers of the wafers 110 and 120 are bonded to each other to form an integral structure, for example, by thermocompression bonding, and the conductive channels are bonded by metal bonding. electrically connected to each other.

However, in the above-mentioned semiconductor devices, due to the complex structure of the 3D memory device chip, there is a problem of poor bonding strength and reliability, and it is expected to further improve the wafer bonding process to improve the bonding strength and reliability.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor device and a manufacturing method thereof, wherein dummy vias connected to each other are formed in the bonding layers of the first wafer and the second wafer to improve the pattern distribution of the bonding surfaces of the two, thereby improving the bonding strength and reliability.

According to an aspect of the present invention, a semiconductor device is provided, comprising:

A first wafer includes a first substrate and a first bonding layer on the surface of the first substrate, and a first conductive channel and a first dummy channel penetrating the first bonding layer, the first conductive channel and the the interconnect structure of the first substrate is electrically connected; and

A second wafer includes a second substrate and a second bonding layer on the surface of the second substrate, and a second conductive via and a second dummy via penetrating the second bonding layer, the second conductive via and the The interconnect structure of the second substrate is electrically connected;

Wherein, the first bonding layer and the second bonding layer are combined,

The first and second conductive vias combine to provide electrical and mechanical connections between the first and second wafers, the first and second dummy vias to each other contacting to improve the mechanical connection bond between the first wafer and the second wafer.

Preferably, the first substrate includes a first semiconductor substrate and a first functional layer located on the first semiconductor substrate, and the second substrate includes a second semiconductor substrate and a first functional layer located on the second semiconductor substrate on the second functional layer.

Preferably, the number and location of the first conductive vias and the second conductive vias are set according to the circuit interconnection of the first wafer and the second wafer, according to the first wafer and the second wafer The number and positions of the first dummy channels and the second dummy channels are set in the metal density distribution of the bonding surfaces between, so that the metal density distribution of the bonding surfaces is uniform.

Preferably, the cross-sectional shapes of the first conductive channel, the second conductive channel, the first dummy channel and the second dummy channel are respectively any one selected from the following shapes: rectangle, square, triangle , circle, ellipse and polygon.

Preferably, the first dummy via and the second dummy via each comprise a first group of dummy vias and a second group of dummy vias, the first group of dummy vias dividing the bonding surface into a plurality of substantially equal areas regions, the second set of dummy vias are distributed in a plurality of regions, such that in each region of the plurality of regions, the second set of dummy vias is associated with the first conductive via and the second conductive via The total metal density distribution of the corresponding conductive channels in the is uniform.

Preferably, the cross-sectional shapes of the first conductive channel, the second conductive channel, and the second group of dummy channels exposed on the bonding surface are respectively any one selected from the following shapes: rectangle, square, triangle , a circle, an ellipse, and a polygon, and the cross-sectional shape of the first group of dummy channels exposed on the bonding surface is any one selected from the following shapes: a line shape and a box shape.

Preferably, the first conductive channel, the second conductive channel, the first dummy channel and the second dummy channel are respectively composed of metals or alloys selected from copper, aluminum, silver, and platinum.

Preferably, the first wafer and the second wafer include: a 3D memory device chip and a driving circuit chip.

Preferably, at least one of the first wafer and the second wafer is a 3D memory device chip, and the corresponding functional layers in the first functional layer and the second functional layer include: a gate stack structure, a trench a channel pillar, an interlayer insulating layer and a first conductive channel, the gate stack structure includes a plurality of gate conductor layers and an isolation layer between adjacent gate conductor layers, the channel pillar penetrates the gate stack structure.

Preferably, at least one of the first wafer and the second wafer is a driving circuit chip, and the corresponding functional layers in the first functional layer and the second functional layer include: a gate stack structure, an interlayer an insulating layer and a first conductive channel, the gate stack structure includes a gate conductor layer.

According to another aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising:

A first wafer is formed, including a first substrate and a first bonding layer on the surface of the first substrate, and a first conductive via and a first dummy via penetrating the first bonding layer, the first conductive via and the the interconnection structure of the first substrate is electrically connected;

A second wafer is formed, including a second substrate and a second bonding layer on the surface of the second substrate, and a second conductive via and a second dummy via penetrating the second bonding layer, the second conductive via and the the interconnect structure of the second substrate is electrically connected; and

The first wafer and the second wafer are bonded to each other, the first bonding layer and the second bonding layer are in contact with each other, and the contact surface of the first bonding layer and the second bonding layer is a bond face,

wherein, in the bonding step, the first conductive via and the second conductive via are connected to each other to provide electrical and mechanical connections between the first wafer and the second wafer, the first A dummy via and the second dummy via are in contact with each other to improve the mechanical bonding force between the first wafer and the second wafer.

Preferably, the number and location of the first conductive vias and the second conductive vias are set according to the circuit interconnection of the first wafer and the second wafer, according to the first wafer and the second wafer The number and positions of the first dummy channels and the second dummy channels are set in the metal density distribution of the bonding surfaces between, so that the metal density distribution of the bonding surfaces is uniform.

Preferably, the cross-sectional shapes of the first conductive via, the second conductive via, the first dummy via and the second dummy via exposed on the bonding surface are any one selected from the following shapes respectively : Rectangle, Square, Triangle, Circle, Ellipse, and Polygon.

Preferably, the cross-sectional shape of the first group of dummy channels exposed on the bonding surface of the second dummy channel is any one selected from the following shapes: a line shape and a square shape, the first conductive channel, the The cross-sectional shape of the second conductive channel and the second group of dummy channels of the second dummy channel exposed on the bonding surface are respectively any one selected from the following shapes: rectangle, square, triangle, circle, ellipse and polygons.

Preferably, the first conductive via and the first dummy via are formed by a common metal filling process, the second conductive via and the second dummy via are formed by a common metal filling process, and the metal filling process include:

forming through openings in respective ones of the first bonding layer and the second bonding layer;

filling the opening with a metal layer; and

Chemical mechanical planarization is used to remove the portion of the metal layer on the surface of the corresponding bonding layer.

According to the semiconductor device of the embodiment of the present invention, not only conductive vias for electrical connection to each other but also dummy vias for mechanical connection to each other are formed in the bonding layers of the first wafer and the second wafer. Conductive vias in the semiconductor device provide electrical connections between the first and second wafers, and dummy vias provide mechanical connections between the first and second wafers.

The dummy channel in the semiconductor device increases the metal density of the bonding surface, so that the ratio of metal bonds to molecular bonds is also increased. The dummy channel formed of metal material has good ductility, and even if the connection end of the dummy channel is uneven, or there is wafer warpage, a good mechanical connection can be achieved, so that the bonding strength of the hybrid bonding can be improved. In addition, as the metal density of the bonding surface increases, the heat dissipation characteristics of the semiconductor device can be improved.

Further, the dummy channel of the semiconductor device makes the metal density distribution uniform, so that a smooth and flat bonding surface can be obtained in the chemical mechanical planarization step, thereby increasing the contact area in the subsequent bonding step, thereby improving the bonding strength. and reliability.

Therefore, the semiconductor device according to the embodiment of the present invention improves product yield and reliability.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.

1 and 2 show schematic cross-sectional views of a semiconductor device according to the prior art.

3 to 7 respectively illustrate schematic cross-sectional views of different steps of a method for fabricating a semiconductor device according to an embodiment of the present invention.

8a and 8b respectively illustrate schematic plan views of bonding surfaces of a semiconductor device according to an embodiment of the present invention.

Detailed ways

The present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are designated by like reference numerals. For the sake of clarity, various parts in the figures have not been drawn to scale. Additionally, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be depicted in one figure.

It will be understood that, in describing the structure of a device, when a layer or region is referred to as being "on" or "over" another layer or region, it can be directly on the other layer or region, or Other layers or regions are also included between it and another layer, another region. And, if the device is turned over, the layer, one region, will be "under" or "under" another layer, another region.

In order to describe the situation directly above another layer, another area, the expression "directly on" or "on and adjacent to" will be used herein.

Numerous specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques and techniques, in order to provide a clearer understanding of the present invention. However, as can be understood by one skilled in the art, the present invention may be practiced without these specific details.

In this application, the term "semiconductor structure" refers collectively to the entire semiconductor structure formed during the various steps of fabricating a memory device, including all layers or regions that have already been formed. Hereinafter, unless otherwise specified, "semiconductor structure" refers to an intermediate structure including a wafer and a gate stack structure formed thereon.

The inventors of the present application found that the application of the existing semiconductor device to a 3D memory device chip has the following problems. The dielectric layer bonding process requires that the flatness of the bonding surface is high, for example, less than 0.3 to 0.5 nanometers. However, the area of 3D memory device chips is large, and the existence of wafer warpage seriously affects the bonding quality. The hybrid bonding process also realizes the electrical connection between the wafers while forming the wafer interconnect structure, so the application in 3D memory device chips is more attractive. However, in the hybrid bonding process, a conductive channel pattern exists on the bonding surface, and the conductive channel forms a convex portion or a concave portion on the bonding surface, which makes it difficult to match the dielectric layer or the conductive channel, resulting in a decrease in the bonding strength. The wafers bonded to each other in the semiconductor device have poor bonding strength and even fall off easily, which greatly affects the product yield.

The inventors of the present application have noticed that the above-mentioned prior art only designs the conductive channel pattern according to the circuit structure of the wafer, but does not design the conductive channel pattern according to the bonding characteristics of at least two wafers, and therefore proposes a further improved bonding process, wherein, in the No. Dummy channels connected to each other are formed in the bonding layers of the first wafer and the second wafer to improve the pattern distribution of the bonding surfaces of the two wafers, thereby improving the bonding strength and reliability.

The invention may be embodied in various forms, some examples of which will be described below.

3 to 7 respectively illustrate schematic cross-sectional views of different steps of a method for fabricating a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 3, the method begins with a wafer 210 on which primary device structures have been formed.

The wafer 210 includes a semiconductor substrate 211 , and a functional layer 212 and a bonding layer 213 sequentially stacked on the semiconductor substrate 211 . The semiconductor substrate 211 is, for example, a silicon substrate. The functional layer 212 is, for example, a multi-layer structure including a gate stack structure, an interlayer insulating layer, and a conductive channel. The bonding layer 213 is a dielectric layer, for example, composed of silicon oxide. In the embodiment shown in FIG. 3, functional layer 212 includes conductive vias 216 therethrough. The semiconductor substrate 211 and the functional layer 212 stacked on the semiconductor substrate 211 are collectively referred to as a base.

The internal structure of the functional layers of the wafer 210 is related to the chip type. The functional layer provides at least part of the structure of the transistor. For example, the source region and the drain region of the transistor are formed in the semiconductor substrate 211 of the wafer 210 , and the gate stack structure of the transistor is formed in the functional layer 212 . In the case where the wafer 210 is a 3D memory device chip, the gate stack structure in the functional layer 212 includes a plurality of levels of gate conductor layers and a plurality of interlayer insulating layers for separating adjacent gate conductor layers, and through the channel pillars of the gate stack structure. In the case where the wafer 210 is a driving circuit chip, the gate stack structure in the functional layer 212 includes, for example, a single-level gate conductor layer.

The resist layer 201 is formed on the surface of the bonding layer 213 . A plurality of openings 202 are formed in the resist layer 201 using a photolithography process, thereby forming a mask. The plurality of openings 202 in the resist layer 201 include not only first openings that are aligned with the conductive vias 216 , but also second openings that are not aligned with the conductive vias 216 . As described below, the first openings will be used to form conductive vias that provide electrical connections, and the second openings will be used to form dummy vias that improve pattern distribution.

Then, etching is performed using the resist layer 201 as a mask to form a plurality of openings 203 in the bonding layer 213, so that the pattern of the resist layer 201 is transferred into the bonding layer 213, as shown in FIG. 4 .

This step, for example, employs a dry etching (eg reactive ion etching) or wet etching process. The etchant used in dry etching is, for example, an etching gas, and the etchant used in wet etching is, for example, an etching solution. During etching, the etchant reaches the surface of the bonding layer 213 via the openings 202 in the resist layer 201 , gradually removing the exposed portions of the bonding layer 213 . Etching can be stopped at the top surface of the conductive channel 216 due to etchant selectivity, or by controlling the etch time. Then, the resist layer 201 is removed by ashing or solvent dissolution.

Then, a metal layer 204 is deposited on the bonding layer 213 as shown in FIG. 5 .

In this step, the metal layer 204 is formed by, for example, magnetron sputtering. The metal layer consists, for example, of a metal or alloy selected from platinum, silver, copper, aluminum, preferably copper. The metal layer 204 fills the plurality of openings 203 in the bonding layer 213 and extends laterally across the surface of the bonding layer 213 .

Then, a chemical mechanical planarization process is used to remove the portion of the metal layer 204 located on the surface of the bonding layer 213 to form a conductive channel 214 and a dummy channel 215, as shown in FIG. 6 .

The chemical mechanical planarization process used in this step uses the bonding layer 213 as a stop layer, so that the part of the metal layer 204 located on the surface of the bonding layer 213 can be completely removed. Portions of the metal layer 204 located in the first openings of the plurality of openings 203 form conductive vias 214 , and portions of the metal layer 204 located in the second openings of the plurality of openings 203 form dummy vias 215 .

The conductive channels 214 in the bonding layer 213 and the conductive channels 216 in the functional layer 212 form continuous conductive paths, and the dummy channels 215 in the bonding layer 213 are used to improve pattern distribution without forming conductive paths.

Then, conductive vias 224 and dummy vias 225 are formed in wafer 220 in alignment with and identical to each other with wafer 210 , and the bonding layers of wafers 210 and 220 are contacted to each other to form semiconductor device 200 , as shown in FIG. 7 .

The wafer 220 includes a semiconductor substrate 221 , and a functional layer 222 and a bonding layer 223 sequentially stacked on the semiconductor substrate 221 . The semiconductor substrate 221 is, for example, a silicon substrate. The functional layer 222 is, for example, a multi-layer structure including a gate stack structure, an interlayer insulating layer, and a conductive channel. The bonding layer 223 is a dielectric layer, for example, composed of silicon oxide. In the embodiment shown in FIG. 7, functional layer 222 includes conductive vias 226 therethrough.

The conductive channels in the bonding layer 223 and the conductive channels 226 in the functional layer 222 form continuous conductive paths, and the dummy channels 225 in the bonding layer 223 are used to improve pattern distribution without forming conductive paths. Thus, during the bonding process, the conductive vias 214 of the wafer 210 and the conductive vias 224 of the wafer 220 are in contact with each other and metal-bonded, thereby providing electrical connections between the wafers 210 and 220 , the dummy vias 215 of the wafer 210 and the wafer 220 Dummy vias 225 are in contact with each other and are metal-bonded to provide a mechanical connection between wafers 210 and 220 .

8a and 8b respectively illustrate schematic plan views of bonding surfaces of a semiconductor device according to an embodiment of the present invention. In the embodiment of the present invention, the bonding surface of the semiconductor device is the free surface of the bonding layer. The bonding surface pattern distributions of the wafers 210 and 220 in the semiconductor device 200 are approximately the same. A schematic plan view of wafer 210 viewed along line AA in FIG. 7 is shown in the figure.

As shown in FIGS. 8 a and 8 b , the surface of the bonding layer 213 of the wafer 210 is a bonding surface. A plurality of conductive vias 214 and a plurality of dummy vias 215 are distributed on the bonding surface. The number and location of conductive vias 214 are designed in accordance with the circuit interconnections of wafers 210 and 220 to provide electrical connection of internal circuits via bond surfaces. The number and location of the dummy vias 215 are designed according to the metal density distribution of the wafer 210 . In this embodiment, due to the introduction of the dummy channel 215, the distribution of metal density on the bonding surface can be improved, that is, the ratio of the total metal pattern area of the conductive channel and the dummy channel to the surface area of the bonding surface, on the bonding surface roughly equal in different regions.

In the embodiment shown in FIG. 8 a , the cross-sectional shape of the dummy via 215 is substantially the same as the cross-sectional shape of the plurality of conductive vias 214 , and both are rectangular. In alternative embodiments, the cross-sectional shape may be any of a rectangle, a square, a triangle, a circle, an ellipse, and a polygon. The plurality of dummy vias 215 fill empty areas around the plurality of conductive vias 214 to improve the distribution of metal density.

In the embodiment shown in Figure 8b, the dummy channel 215 includes a first set of dummy channels 215a and a second set of dummy channels 215b. The cross-sectional shape of the first group of dummy vias 215a is linear or square, and is used to divide the bonding surface of the wafer 210 into a plurality of regions with substantially equal areas. In each area, the cross-sectional shape of the dummy via 215b is substantially the same as the cross-sectional shape of the plurality of conductive vias 214, and both are rectangular. In alternative embodiments, the cross-sectional shape may be any of a rectangle, a square, a triangle, a circle, an ellipse, and a polygon. The plurality of dummy vias 215b fill empty areas around the plurality of conductive vias 214 .

According to the semiconductor device of the embodiment of the present invention, not only conductive vias for electrical connection but also dummy vias for improving metal distribution are formed in the bonding layer. The conductive vias and the dummy vias of the first wafer and the second wafer are aligned, respectively, wherein only the conductive vias are electrically connected to the internal circuit, and the dummy vias do not form conductive paths. The semiconductor device can improve bonding strength and reliability, thereby improving product yield.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present invention have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims (15)

1. a kind of semiconductor devices, comprising:

First chip, including the first substrate and positioned at the first binder course of first substrate surface and through described first The first conductive channel and the first pseudo-channel of binder course, first conductive channel and the interconnection structure of first substrate are electrically connected It connects；And

Second chip, including the second substrate and positioned at the second binder course of second substrate surface and through described second The second conductive channel and the second pseudo-channel of binder course, second conductive channel and the interconnection structure of second substrate are electrically connected It connects；

Wherein, first binder course and second binder course combine,

First conductive channel and second conductive channel in conjunction with provide first chip and second chip it Between electrically and mechanically, first pseudo-channel and second pseudo-channel are in contact with each other to improve first chip Mechanical connection binding force between second chip.

2. semiconductor devices according to claim 1, wherein first substrate includes the first semiconductor substrate and is located at The first functional layer in first semiconductor substrate, second substrate is including the second semiconductor substrate and positioned at described second The second functional layer in semiconductor substrate.

3. semiconductor devices according to claim 1, wherein according to the circuit of first chip and second chip Quantity and the position of interconnection setting first conductive channel and second conductive channel, according to first chip and described Quantity and the position of density metal distribution setting first pseudo-channel and second pseudo-channel of bonding face between second chip It sets, so that the density metal of the bonding face is evenly distributed.

4. semiconductor devices according to claim 3, wherein first conductive channel, second conductive channel, institute The cross-sectional shape for stating the first pseudo-channel and second pseudo-channel is respectively any one for being selected from following shape: rectangle, side Shape, triangle, circle, ellipse and polygon.

5. semiconductor devices according to claim 3, wherein first pseudo-channel and second pseudo-channel are respectively wrapped Include first group of pseudo-channel and second group of pseudo-channel, the bonding face is divided into roughly equal more of area by first group of pseudo-channel A region, second group of pseudo-channel are distributed in multiple regions, so that in each region in the multiple region, described Two groups of pseudo-channels density metal total to the corresponding conductive channel in first conductive channel and second conductive channel It is evenly distributed.

6. semiconductor devices according to claim 4, wherein first conductive channel, second conductive channel, institute It is respectively any one for being selected from following shape: rectangle, side that second group of pseudo-channel, which is stated, in the cross sectional shape of bonding face exposure Shape, triangle, circle, ellipse and polygon, cross sectional shape difference of the first group of pseudo-channel in bonding face exposure For any one selected from following shape: linear and square frame-shaped.

7. semiconductor devices according to claim 1, wherein first conductive channel, second conductive channel, institute The first pseudo-channel and second pseudo-channel is stated to be made of the metal or alloy selected from copper, aluminium, silver, platinum respectively.

8. semiconductor devices according to claim 1, wherein first chip and second chip include: that 3D is deposited Memory device chip and drive circuit chip.

9. the semiconductor devices according to claim 2 or 8, wherein in first chip and second chip extremely Few one is 3D memory device chip, and the corresponding function layer in first functional layer and second functional layer includes: that grid are folded Layer structure, channel column, interlayer insulating film and the first conductive channel, the rhythmic structure of the fence include multiple gate conductor layers and adjacent Separation layer between gate conductor layer, the channel column run through the rhythmic structure of the fence.

10. semiconductor devices according to claim 8, wherein in first chip and second chip at least One is drive circuit chip, and the corresponding function layer in first functional layer and second functional layer includes: gate stack knot Structure, interlayer insulating film and the first conductive channel, the rhythmic structure of the fence include gate conductor layer.

11. a kind of production method of semiconductor devices, comprising:

The first chip is formed, including the first substrate and positioned at the first binder course of first substrate surface and through described The first conductive channel and the first pseudo-channel of first binder course, the interconnection structure of first conductive channel and first substrate Electrical connection；

The second chip is formed, including the second substrate and positioned at the second binder course of second substrate surface and through described The second conductive channel and the second pseudo-channel of second binder course, the interconnection structure of second conductive channel and second substrate Electrical connection；And

First chip and second chip are bonded together, first binder course and second binder course connect each other The contact surface of touching, first binder course and second binder course is bonding face,

Wherein, in the bonding steps, first conductive channel and second conductive channel are connected to each other to provide It states between the first chip and second chip electrically and mechanically, first pseudo-channel and second pseudo-channel It is in contact with each other to improve the mechanical connection binding force between first chip and second chip.

12. production method according to claim 11, wherein according to the circuit of first chip and second chip Quantity and the position of interconnection setting first conductive channel and second conductive channel, according to first chip and described Quantity and the position of density metal distribution setting first pseudo-channel and second pseudo-channel of bonding face between second chip It sets, so that the density metal of the bonding face is evenly distributed.

13. production method according to claim 12, wherein first conductive channel, second conductive channel, institute It is respectively to be selected from appointing for following shape that the first pseudo-channel and second pseudo-channel, which are stated, in the cross sectional shape of bonding face exposure It anticipates one kind: rectangle, rectangular, triangle, circle, ellipse and polygon.

14. production method according to claim 13, wherein first group of pseudo-channel of second pseudo-channel is in the key Conjunction face exposure cross sectional shape be respectively be selected from following shape any one: linear and square frame-shaped, first conductive channel, Second conductive channel, second pseudo-channel second group of pseudo-channel the bonding face exposure cross sectional shape be respectively Any one selected from following shape: rectangle, rectangular, triangle, circle, ellipse and polygon.

15. production method according to claim 11, wherein first conductive channel and first pseudo-channel use Common metal filling processes are formed, and second conductive channel and second pseudo-channel use common metal filling processes It is formed, the metal filling processes include:

Perforative opening is formed in the corresponding binder course in first binder course and second binder course；

The opening is filled using metal layer；And

The metal layer is removed using chemical-mechanical planarization and is located at the corresponding part in conjunction with layer surface.