TWI898281B - System and method for testing memory - Google Patents

Abstract

A system for testing memory is provided. The system includes a memory device and a tester. The memory device includes a dummy bit line, a first voltage terminal, a first switch, a voltage supply circuit and a second voltage terminal. The first switch is coupled between the dummy bit line and the first voltage terminal. The voltage supply circuit outputs a first voltage to the first voltage terminal and output a voltage level of the first voltage terminal through a data line. The second voltage terminal is operatively coupled to the dummy bit line and receives a second voltage different from the first terminal. The tester is operatively coupled to the memory device and executes: generating a test command to control the voltage supply circuit to stop outputting the first voltage; turning on the first switch; and generating a test result according to the voltage level.

Description

System and method for testing memory

The present disclosure relates to a system and method for testing a memory, and more particularly to a system and method for testing a voltage level of a memory.

With the rapid advancement of memory process technology, memory size is shrinking while the density of memory circuits is increasing. While higher circuit density benefits memory speed and performance, it also leads to higher error rates and manufacturing difficulties. To ensure product reliability and yield, effective memory testing is crucial.

The present disclosure provides a system for testing a memory. The system includes a memory device and a tester. The memory device includes a virtual bit line, a first voltage terminal, a first switch, a voltage supply circuit, and a second voltage terminal. The first switch is coupled between the virtual bit line and the first voltage terminal. The voltage supply circuit outputs a first voltage to the first voltage terminal and outputs the voltage level of the first voltage terminal via a data line. The second voltage terminal is operatively coupled to the virtual bit line and receives a second voltage different from the first voltage. The tester is operatively coupled to the memory device and performs the following operations: generating a test instruction to control the voltage supply circuit to stop outputting a first voltage; turning on the first switch; and generating a test result according to the voltage level.

In some embodiments, the memory device further includes a second switch coupled between the dummy bit line and the second voltage terminal and turned on in response to a first command from the tester.

In some embodiments, after outputting the first command, the tester compares the second voltage with the measured voltage to determine whether the memory device passes the test.

In some embodiments, the memory device further includes a third voltage terminal and a third switch. The third voltage terminal receives a third voltage that is different from the first voltage and the second voltage. The third switch is coupled between the virtual bit line and the third voltage terminal and is turned on in response to a second command from the tester. The second switch is turned off in response to the second command.

In some embodiments, the second voltage is an operating voltage of the memory device, and the third voltage is a ground voltage.

In some embodiments, the voltage supply circuit includes a bit line precharge circuit, the first voltage is a bit line precharge voltage, and the memory device floats the voltage supply terminal of the bit line precharge circuit in response to the test command.

The present disclosure provides a method for testing a memory device. The method includes: applying a first voltage to a first voltage terminal of a memory device; generating a first command to the memory device to turn on a first switch, wherein the first switch is coupled between a virtual bit line and the first voltage terminal; controlling a voltage supply circuit of the memory device to stop outputting a second voltage to a second voltage terminal; turning on a second switch, wherein the second switch is coupled between the virtual bit line and the second voltage terminal; and measuring a data line to obtain a measurement voltage, and generating a test result based on the measurement voltage, wherein the data line is coupled to the voltage supply circuit.

In some embodiments, the method further includes comparing the measured voltage to the first voltage to determine whether the memory device passes the test.

In some embodiments, generating the first instruction includes generating the first instruction to the memory device to turn off a third switch, the third switch being coupled between the virtual bit line and a third voltage terminal, the third voltage terminal receiving a third voltage different from the first voltage.

In some embodiments, the first voltage is equal to a high logic voltage when a memory cell of the memory device stores a high logic value, and the third voltage is equal to a low logic voltage when the memory cell stores a low logic value.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify one embodiment of the present invention. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat component symbols or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, specify a relationship between the various embodiments or configurations discussed.

The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples in this specification, including examples of any term discussed herein, is illustrative only and in no way limits the scope or meaning of one embodiment of this disclosure or any exemplified term. Similarly, one embodiment of this disclosure is not limited to the various embodiments given in this specification.

Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "beneath," "above," and "above" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, "approximately," "about," "approximately," or "substantially" shall generally refer to any approximation of a given value or range, which may vary depending on the various fields involved, and its scope shall be consistent with the broadest interpretation understood by those skilled in the art to encompass all such modifications and similar structures. In some embodiments, it shall generally refer to within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. The numerical values given herein are approximate, meaning that if not explicitly stated, the term "approximately," "about," "approximately," or "substantially" can be inferred, or other approximate values can be meant.

Referring to FIG. 1 , FIG. 1 is a schematic diagram of a system 100 for testing memory according to some embodiments of the present disclosure. Specifically, the system 100 includes a memory device 110 and a tester 120 . In some embodiments, the memory device 110 is operatively coupled to the tester 120 .

According to some embodiments, tester 120 is a memory tester, such as a dynamic random-access memory (DRAM) or static random-access memory (SRAM) tester. In some embodiments, tester 120 is a programmable tester. As shown in FIG. 1 , in some embodiments, tester 120 includes a processor 121.

Depending on the embodiment, the processor 121 is a central processing unit (CPU), or other programmable general-purpose or special-purpose micro control unit (MCU), microprocessor, digital signal processor (DSP), programmable controller, application specific integrated circuit (ASIC), graphics processing unit (GPU), arithmetic logic unit (ALU), complex programmable logic device (CPLD), field programmable gate array (FPGA), or other similar components or combinations of the above components.

In some embodiments, memory device 110 is a memory device such as a single in-line memory module (SIMM), a dual in-line memory module (SIMM), a DRAM chip, or an SRAM chip. In some embodiments, memory device 110 is a fifth-generation double data rate synchronous dynamic random-access memory (DDR5 SDRAM) chip.

As shown in FIG. 1 , in some embodiments, memory device 110 includes a memory array 111 and a control circuit 112. Memory array 111 includes a plurality of memory cells (storage circuits) 113. Memory cells 113 are arranged in a two-dimensional memory array. Depending on the embodiment, memory cells 113 may include volatile memory cells, non-volatile memory cells, or a combination thereof.

In practice, memory array 111 further includes a plurality of word lines WL and a plurality of bit lines BL. In some embodiments, these word lines WL and bit lines BL comprise conductive structures, such as metal wires. In some embodiments, as shown in FIG. 1 , each column in memory array 111 is coupled to a corresponding word line WL, and each row in memory array 111 is coupled to a corresponding bit line BL.

According to some embodiments of the present disclosure, control circuit 112 performs operations, such as read operations or write operations, on memory array 111 by controlling and/or sensing signals on word lines WL and bit lines BL. In some embodiments, control circuit 112 performs operations on memory array 111 based on commands, such as commands generated by tester 120. For example, tester 120 generates a read command corresponding to a memory address to memory device 110, and control circuit 112 retrieves data from corresponding memory cell 113 based on the memory address. In some embodiments, the control circuit 112 includes a column address decoder, a row address decoder, and a sense amplifier.

The configuration of FIG. 1 is provided for illustrative purposes. Various implementations of FIG. 1 are within the contemplated scope of the present invention. For example, in some embodiments, the memory array 111 is a three-dimensional memory array.

Refer to FIG. 2 . According to some embodiments of the present disclosure, FIG. 2 is a schematic diagram illustrating a layout perspective of memory array 111 corresponding to FIG. For ease of understanding, similar components in FIG. 2 are labeled with the same reference numbers as those in FIG. For the sake of brevity, the detailed operations of similar components discussed in detail above are omitted herein unless they are necessary to explain their cooperative relationship with the components shown in FIG. 2 .

To illustrate, in one layout perspective, memory row 111 is divided into multiple segments S0-SN along direction x. According to some embodiments of the present disclosure, each bit line BL of memory row 111 is disposed between two adjacent segments (e.g., segment S0 and segment S1). In other words, one bit line BL is disposed between every two adjacent segments. In some embodiments, each bit line BL extends along direction y, perpendicular to direction x, and includes multiple branches extending along direction x. In some embodiments, each bit line BL's multiple branches extend into each of the two adjacent segments.

As shown in FIG. 2 , memory array 111 further includes a plurality of dummy bit lines DBL, distinct from bit lines BL. According to some embodiments, bit lines BL are used to transmit data to perform operations on memory array 111, while dummy bit lines DBL are not used for data transmission. Specifically, control circuit 112 is used to transmit data signals to memory cells 113 via bit lines BL to change the data (logical state) stored in memory cells 113 without using signals on dummy bit lines DBL. In other words, memory cells 113 do not change the data stored in memory cells 113 based on signals on dummy bit lines DBL.

In some embodiments, dummy bit lines DBL are used to maintain pattern uniformity of bit lines BL. For example, dummy bit lines DBL are formed at the periphery of the memory array 111 (surrounding bit lines BL) so that the outermost bit lines BL have similar external conditions to the other bit lines BL.

In some embodiments, the multiple dummy bit lines DBL of the memory array 111 include two dummy bit lines DBL located at opposite ends of the memory array 111 (e.g., at opposite ends in direction x), such as the dummy bit line DBL on the left side of segment S0 and the dummy bit line DBL on the right side of segment SN in FIG. According to some embodiments of the present disclosure, the dummy bit lines DBL located at opposite ends of the memory array 111 extend along direction y and have multiple branches extending into adjacent segments (e.g., segment S0 and segment SN). In some embodiments, the outermost branches of the dummy bit lines DBL at both ends of the memory array 111 in the direction y are located on the edges of adjacent segments (e.g., segment S0 and segment SN). Furthermore, the branches of adjacent bit lines BL in the direction y are located between the outermost branches in the direction y. For example, as shown in FIG. 2 , the branch of the bit line BL in segment S0 between segments S0 and S1 is located within the two outermost branches of the dummy bit line DBL on the left side of segment S0 in the direction y.

In some embodiments, some dummy bit lines DBL are arranged between segments of the memory array 111. According to some embodiments, a dummy bit line DBL is arranged between every three segments in the memory array 111. For example, in the embodiment shown in FIG. 2 , along direction x, a dummy bit line DBL is arranged after segments S0 and S1, a dummy bit line DBL is arranged after segments S3 and S4, and so on.

As shown in FIG. 2 , the inter-segment dummy bit line DBL (e.g., the dummy bit line DBL between segments S1 and S2) has multiple branches. In some embodiments, the inter-segment dummy bit line DBL has four branches, located at the edge of the memory array 111 and extending into adjacent segments. According to some embodiments, the branches of the dummy bit line DBL are located outside the branches of the bit lines BL. For example, in a segment (e.g., segment S0), the branches of the dummy bit line DBL surround all the branches of the bit lines BL in the direction y.

The configuration of FIG. 2 is provided for illustrative purposes. Various implementations of FIG. 2 are contemplated within the scope of the present disclosure. For example, in some embodiments, portions of bit lines BL and dummy bit lines DBL between segments (e.g., bit lines BL and dummy bit lines DBL between segments S1 and S2) extending along direction y overlap in terms of layout perspective.

Referring to FIG. 3 and FIG. 4 together, according to some embodiments of the present disclosure, FIG. 3 is a circuit diagram of an exemplary portion 110 a of the memory device 110 after the memory device 110 receives a command. FIG. 4 is a circuit diagram of an exemplary portion 110 a of the memory device 110 after the memory device 110 receives a command different from that shown in FIG. For ease of understanding, similar components in FIG. 3 and FIG. 4 are labeled with the same reference numerals as those in the embodiments of FIG. 1 and FIG. 2 .

To illustrate, portion 110a of memory device 110 includes voltage terminal 301, voltage terminal 302, voltage terminal 304, switch sw1, switch sw2, switch sw3, data line/pad DQ, voltage supply circuit 310, and voltage supply circuit 320. In some embodiments, memory device 110 includes multiple portions 110a. Specifically, according to some embodiments, each dummy bit line DBL corresponds to a portion 110a.

As shown in FIG3 , switch sw1 is coupled between dummy bit line DBL and voltage terminal 301. Switch sw2 is coupled between dummy bit line DBL and voltage terminal 302. Switch sw3 is coupled between dummy bit line DBL and voltage terminal 303. Voltage terminal 301 is coupled to voltage supply circuit 310. Data line/pad DQ is coupled to voltage supply circuit 310. In some embodiments, data line/pad DQ is used to output the voltage of node N1. In some embodiments, data line/pad DQ is used to transmit data into or out of memory device 110.

In some embodiments, the voltage supply circuit 320 is coupled to the voltage terminal 301 and the voltage supply circuit 310. The voltage supply circuit 320 is configured to provide a voltage to the voltage terminal 301 and the voltage supply circuit 310. In some embodiments, the voltage supply circuit 320 provides a voltage VARY.

The voltage supply circuit 310 is used to generate a voltage VBLP to the voltage terminal 301. In some embodiments, the voltage supply circuit 310 includes a bit line precharge circuit, and the voltage VBLP is the bit line precharge voltage of the memory device 110. In some embodiments, the voltage supply circuit 310 further includes a voltage regulator.

According to some embodiments of the present disclosure, voltage terminal 302 is configured to receive voltage VARY, and voltage terminal 303 is configured to receive voltage VSS. In some embodiments, voltage VARY is an operating voltage for memory array 111, and voltage VSS is a reference voltage or ground voltage for memory array 111. In some embodiments, voltage VARY has a high voltage level (e.g., 1.1 volts) corresponding to a high logic state of a memory cell, while voltage VSS has a low voltage level (e.g., 0 volts) corresponding to a low logic state of a memory cell. In some embodiments, the voltage VARY is equal to a high logic voltage when the memory cell 113 stores a high logic value, and the voltage VSS is equal to a low logic voltage when the memory cell 113 stores a low logic value.

According to some embodiments, voltage VARY is greater than voltage VBLP, which is greater than voltage VSS. In some embodiments, voltage VBLP is half the voltage VARY.

In operation, memory device 110 changes the voltage level on virtual bit line DBL to avoid or reduce interference with bit line BL. For example, memory device 110 applies voltage VARY or voltage VSS to virtual bit line DBL to prevent capacitive coupling from interfering with adjacent bit line BL. In some embodiments, voltages VARY and VSS are provided to virtual bit line DBL by control circuit 112. In some embodiments, control circuit 112 controls switches sw2 and sw3 to apply voltage VARY or voltage VSS to virtual bit line DBL.

In some embodiments, memory device 110 controls switches sw2 and sw3 based on a received instruction (e.g., an instruction received from tester 120) or an operation currently being performed on the memory array. According to some embodiments, during operation, memory device 110 turns on only one of switches sw2 and sw3. To illustrate, in the embodiment shown in FIG. 3 , memory device 110 turns on switch sw2 and turns off switch sw3 in response to one instruction. Conversely, in the embodiment shown in FIG. 4 , memory device 110 turns off switch sw2 and turns on switch sw3 in response to another instruction.

In some applications, the tester 120 is used to measure the voltage level on the dummy bit line DBL. In some embodiments, the tester 120 determines the voltage level on the dummy bit line DBL based on the voltage level on the data line/pad DQ. In some embodiments, to measure the voltage level on the dummy bit line DBL, the tester 120 transmits a test command to the memory device 110. In response to the test command, the memory device 110 floats the input terminal IN or the output terminal/voltage supply terminal of the voltage supply circuit 310. In other words, in response to the test command, the voltage supply circuit 310 stops outputting the voltage VBLP to the voltage terminal 301, and the node N1 has a floating potential.

Next, memory device 110 turns on switch sw1 in response to the test command. In some embodiments, when voltage supply circuit 310 stops outputting voltage to voltage terminal 301 (node N1) and switch sw1 turns on, the voltage level at node N1 equals the voltage level on dummy bit line DBL. Memory device 110 then outputs the voltage at node N1 via data line/pad DQ (at this point, the voltage level of data line/pad DQ equals the voltage level at node N1). In some embodiments, the tester 120 measures the voltage level of the data line/pad DQ to determine the voltage level of the node N1, and further determines the voltage level of the dummy bit line DBL.

The configurations of FIG3 and FIG4 are provided for illustrative purposes. Various implementations of FIG3 and FIG4 are within the contemplated scope of the present invention. For example, in some embodiments, multiple dummy bit lines DBL share a voltage supply circuit 310 and/or a voltage supply circuit 320.

According to some embodiments, the tester 120 is further configured to perform a test on the memory device 110. During this test, the tester 120 first generates a command to control the memory device 110 to apply the voltage VARY or the voltage VSS to the dummy bit line DBL. The tester 120 then measures the voltage level on the dummy bit line DBL and generates a test result based on this voltage level. The test result indicates whether the memory device 110 correctly applies the voltage VARY or the voltage VSS to the dummy bit line DBL according to the command. Details of the test method will be described in the following paragraphs with reference to FIG. 5.

Referring now to FIG. 5 , FIG. 5 is a flow chart of a method 500 for testing a memory device according to some embodiments of the present disclosure. Method 500 includes operations (or steps) 501 - 505 . At least some of the operations in method 500 may be used to test memory device 110 .

1 to 4 , in operation 501 , the memory device 110 applies a voltage VARY to the voltage terminal 302 and/or applies a voltage VSS to the voltage terminal 303 .

In operation 502 , the tester 120 generates a command (eg, a write command or a read command) to the memory device 110 to control the memory device 110 to turn on the switch sw2 or the switch sw3 .

In some embodiments, the tester 120 generates the instruction to the memory device 110 in operation 502 to control the memory device 110 to turn on switch sw2 and turn off switch sw3. In other embodiments, the tester 120 generates the instruction to the memory device 110 in operation 502 to control the memory device 110 to turn on switch sw3 and turn off switch sw2.

In operation 503, the tester 120 controls the voltage supply circuit 310 to stop outputting the voltage VBLP to the voltage terminal 301. In some embodiments, the memory device 110 floats the input terminal/voltage supply terminal of the voltage supply circuit 310 in response to the test command described in operation 502.

In operation 504, the test engine 120 generates a test command to the memory device 110, and the memory device 110 turns on the switch sw1 in response to the test command.

In operation 505, the tester 120 measures the voltage on the data line/pad DQ as a measurement voltage and generates a test result of the memory device 110 based on the measurement voltage.

In some embodiments, when the instruction generated by the tester 120 in operation 504 is to control the memory device 110 to turn on the switch sw2, the processor 121 compares the measured voltage with the voltage VARY to generate a test result for the memory device 110. When the measured voltage is equal to the voltage VARY, the processor 121 determines that the memory device 110 has passed the test. In other words, the memory device 110 has correctly applied the voltage VARY to the dummy bit line DBL according to the instruction. Conversely, when the measured voltage is not equal to the voltage VARY, the processor 121 determines that the memory device 110 has failed the test.

Similarly, when the instruction generated by the tester 120 in operation 504 is to control the memory device 110 to turn on the switch sw3, the processor 121 compares the measured voltage with the voltage VSS to generate a test result for the memory device 110. If the measured voltage is equal to the voltage VSS, the processor 121 determines that the memory device 110 has passed the test. In other words, the memory device 110 has correctly applied the voltage VSS to the dummy bit line DBL according to the instruction. Conversely, if the measured voltage is not equal to the voltage VSS, the processor 121 determines that the memory device 110 has failed the test.

Method 500 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that more operations may be provided before, during, or after method 500 in FIG. 5 . Some operations in method 500 may be replaced or removed. Furthermore, it is contemplated that the operations of method 500 may be performed in an order other than that shown in FIG. 5 . For example, according to some embodiments, operation 501 may be performed after operation 504.

In some embodiments, the tester 120 determines the voltage on the current dummy bit line DBL by measuring the current consumption of a voltage supply circuit 320 . For example, when switch sw2 is on, switches sw1 and sw3 are off, and voltage VARY is applied to virtual bit line DBL, the current consumption of voltage supply circuit 320 is the highest. When switch sw1 is on, switches sw2 and sw3 are off, and voltage VBLP is applied to virtual bit line DBL, the current consumption of voltage supply circuit 320 is medium. When switch sw3 is on, switches sw1 and sw2 are off, and voltage VSS is applied to virtual bit line DBL, the current consumption of voltage supply circuit 320 is the lowest. In some embodiments, the processor 121 determines the voltage level on the dummy bit line DBL by comparing the current consumption of the voltage supply circuit 320 after the memory device 110 receives the current command with the current consumption of the voltage supply circuit 320 after the memory device 110 previously received other commands.

In some embodiments, tester 120 performs an incomplete data test on memory device 110 to determine the voltage level on dummy set bit line DBL. Specifically, tester 120 writes an incomplete low logic value to a bit line BL adjacent to dummy set bit line DBL. Then, tester 120 reads the data on bit line BL. If the data read by tester 120 is a high logic value, tester 120 determines that the voltage on dummy set bit line DBL is voltage VARY.

For example, the voltage level of voltage VARY (complete high logic value) is 1.1 volts, and the voltage level of voltage VSS (complete low logic value) is 0 volts. Tester 120 writes an incomplete low logic value (voltage level of 0.45 volts) to bit line BL adjacent to dummy bit line DBL. Tester 120 then reads the data on bit line BL. If the read data is a high logic value, it can be determined that the data flipped to a high logic value due to the capacitive coupling effect generated by the high voltage on dummy bit line DBL. Tester 120 determines that the voltage on dummy bit line DBL is voltage VARY.

Similarly, the tester 120 writes an incomplete high logic value to the bit line BL adjacent to the dummy bit line DBL and reads the data on the bit line BL to determine the voltage level of the dummy bit line DBL. When the data read by the tester 120 is a low logic value, the tester 120 determines that the voltage on the dummy bit line DBL is VSS.

For example, the voltage level of VARY (a complete high logic value) is 1.1 volts, and the voltage level of VSS (a complete low logic value) is 0 volts. The tester 120 writes an incomplete high logic value (a voltage level of 0.55 volts) to the bit line BL adjacent to the dummy bit line DBL. The tester 120 then reads the data on the bit line BL. If the read data is a low logic value, it can be determined that the data flipped to a low logic value due to the capacitive coupling effect generated by the low voltage on the dummy bit line DBL. The tester 120 then determines that the voltage on the dummy bit line DBL is VSS.

In some embodiments, the method 500 is executed by the tester 120 and is combined with the current consumption measurement of the voltage supply circuit 320 and the incomplete data test to fully verify the voltage level of the dummy bit line DBL.

In summary, the present disclosure provides a system and method for testing a memory device. The system and method provide a test mode for measuring the voltage level of a virtual bit line. Measuring the voltage level of the virtual bit line helps avoid detection failures caused by the virtual bit line voltage being different from the expected voltage. In the disclosed method, by bridging a precharge voltage terminal to the virtual bit line, the voltage level of the virtual bit line can be measured directly from the data line/pad DQ of the memory device.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of one embodiment of the present invention. Those skilled in the art will appreciate that one embodiment of the present invention can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and/or advantages as the embodiment described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of one embodiment of the present invention, and that various changes, substitutions, and modifications may be made in one embodiment of the present invention without departing from the spirit and scope of one embodiment of the present invention.

100: System 110: Memory device 110a: Portion 111: Memory array 112: Control circuit 113: Memory cell 120: Tester 121: Processor 301: Voltage terminal 302: Voltage terminal 303: Voltage terminal 310: Voltage supply circuit 320: Voltage supply circuit 500: Method 501: Operation 502: Operation 503: Operation 504: Operation 505: Operation BL: Bit line DBL: Dummy bit line IN: Input terminal N1: Node DQ: Data line/pad S0: Segment S1: Segment S2: Segment S3: Segment S4: Segment SN: Segment sw1: Switch sw2: Switch sw3: Switch VBLP: Voltage VARY: Voltage VSS: Voltage WL: Word Line x: Direction y: Direction

Aspects of one embodiment of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG1 is a schematic diagram of a system for testing memory according to some embodiments; FIG2 is a schematic diagram of a layout view of a memory array corresponding to FIG1 according to some embodiments; FIG3 is a circuit diagram of an example portion of a memory device after receiving an instruction according to some embodiments; FIG4 is a circuit diagram of an example portion of a memory device after receiving an instruction different from that shown in FIG3 according to some embodiments; and FIG5 is a flow chart of a method for testing memory according to some embodiments.

Domestic Storage Information (Please enter in order by institution, date, and number) None International Storage Information (Please enter in order by country, institution, date, and number) None

110a: Partial

301: Voltage terminal

302: Voltage terminal

303: Voltage terminal

310: Voltage supply circuit

320: Voltage supply circuit

DBL: Dummy bit line

IN: Input terminal

N1: Node

DQ: Data line/pad

sw1: switch

sw2: switch

sw3: switch

VBLP: Voltage

VARY: Voltage

VSS: voltage

Claims (9)

A system for testing a memory device comprises: A memory device comprising: A virtual bit line; A first switch coupled to the virtual bit line; A first voltage terminal, wherein the first switch is coupled between the virtual bit line and the first voltage terminal; A voltage supply circuit for outputting a first voltage to the first voltage terminal; and A second voltage terminal operatively coupled to the virtual bit line and for receiving a second voltage different from the first voltage; and A tester operatively coupled to the memory device and for performing: Generate a test command to control the voltage supply circuit to stop outputting any voltage to the first voltage terminal; and When the voltage supply circuit stops outputting any voltage to the first voltage terminal, the first switch is turned on and a test result is generated based on a voltage level of the first voltage terminal output by the voltage supply circuit through a data line. The system of claim 1, wherein the memory device further comprises: A second switch coupled between the dummy bit line and the second voltage terminal and configured to turn on in response to a first command from the tester. The system of claim 2, wherein the tester is further configured to compare the second voltage with the voltage level after outputting the first command to determine whether the memory device passes a test. The system of claim 2, wherein the memory device further comprises: a third voltage terminal for receiving a third voltage, the third voltage being different from the first voltage and the second voltage; and a third switch coupled between the dummy bit line and the third voltage terminal and configured to turn on in response to a second command from the tester, wherein the second switch turns off in response to the second command. The system of claim 4, wherein the second voltage is an operating voltage of the memory device, and the third voltage is a ground voltage. The system of claim 1, wherein the voltage supply circuit includes a bit line precharge circuit, the first voltage is a bit line precharge voltage, and wherein the memory device floats a voltage supply terminal of the bit line precharge circuit in response to the test command. A method for testing a memory device comprises: Applying a first voltage to a first voltage terminal of a memory device; Generating a first command to the memory device to turn on a first switch, wherein the first switch is coupled between a virtual bit line and the first voltage terminal; Controlling a voltage supply circuit of the memory device to stop outputting any voltage to a second voltage terminal; When the voltage supply circuit stops outputting any voltage to the second voltage terminal, turning on a second switch and measuring a data line to obtain a measurement voltage, wherein the second switch is coupled between the virtual bit line and the second voltage terminal, and the data line is coupled to the voltage supply circuit; and Based on the measured voltage being equal to the first voltage, it is determined that the memory device has passed a test. The method of claim 7, wherein generating the first command comprises: Generating the first command to the memory device to close a third switch, wherein the third switch is coupled between the virtual bit line and a third voltage terminal, wherein the third voltage terminal receives a third voltage different from the first voltage. The method of claim 8, wherein the first voltage is equal to a high logic voltage when a memory cell of the memory device stores a high logic value, and the third voltage is equal to a low logic voltage when the memory cell stores a low logic value.