TWI897775B - Transparent display device and tiled display device - Google Patents

Abstract

A transparent display device includes a circuit substrate, a micro light-emitting diode, a protective layer and a water-blocking structure. The circuit substrate has a transmissive area and a non- transmissive area. Micro light-emitting diodes are disposed on the non- transmissive area and bonded to the circuit substrate. The protective layer is disposed on the non-transmissive area and covers a top surface and a sidewall of the micro light-emitting diode. The micro light emitting diode and the water-blocking structure are separated by the protective layer, and the water-blocking structure includes an opening that overlaps the top surface of the micro light emitting diode.

Description

Transparent display device and spliced display device

The present invention relates to a transparent display device and a spliced display device.

Light-emitting diode (LED) displays are a high-efficiency light source technology widely used in displays, lighting, and multimedia devices. Their structure typically consists of an array of multiple micro-LEDs (micro-LEDs), with each micro-LED controlled by a driver circuit to produce high-resolution and high-brightness displays. To enhance device stability and lifespan, packaging technology is often used to isolate the device from moisture and impurities in the external environment.

However, when moisture intrudes into display devices, it can cause a variety of problems, such as corrosion of metal electrodes and reduced luminous efficiency. These issues not only affect display quality but can also shorten the lifespan of the device. Therefore, moisture barrier technology has become a key design consideration.

The present invention provides a transparent display device and a spliced display device.

At least one embodiment of the present invention provides a transparent display device comprising a circuit substrate, a micro-LED, a protective layer, and a water-blocking structure. The circuit substrate has a transmissive region and a non-transmissive region. The micro-LED is disposed on the non-transmissive region and bonded to the circuit substrate. The protective layer is disposed on the non-transmissive region and covers the top surface and sidewalls of the micro-LED. The micro-LED is separated from the water-blocking structure by the protective layer, and the water-blocking structure includes an opening overlapping the top surface of the micro-LED.

At least one embodiment of the present invention provides a spliced display device comprising two or more transparent display devices spliced together.

10A, 10B, 10C, 10D, 10E: Transparent display device

100: Circuit board

110:Transparent substrate

112: Buffer layer

113: First Insulation Layer

114: Second insulation layer

115: First buffer layer

116: Second buffer layer

117: Third buffer layer

118: Fourth buffer layer

119: Passivation layer

120: Semiconductor layer

130: First conductive pattern layer

131: Gate

132: Conductive characteristics

140: Second conductive pattern layer

150: Third conductive pattern layer

151: First source/drain

152: Second source/drain

153: Conductive characteristics

160: Fourth conductive pattern layer

170: Fifth conductive pattern layer

180: Sixth conductive pattern layer

181,182: Pad

191: The third insulating layer

192: Fourth Insulation Layer

193: Fifth Insulation Layer

200: Micro LED

200s, 300s: Sidewall

200t, 300t: Top

210: Contact

300: Protective layer

400: Water-blocking structure

400H: Open

410: Oxide layer

420: Nitride layer

500: Packaging layer

600: Conductive layer

600H: Through hole

BM: Black Matrix

S1, S2, S3, S4, S5, S6: Steps

T: Active element

TR: Penetration Zone

NTR: Non-penetrating zone

Figure 1 is a partial cross-sectional schematic diagram of a transparent display device according to an embodiment of the present invention.

Figure 2 is a partial cross-sectional schematic diagram of a transparent display device according to an embodiment of the present invention.

Figure 3 is a partial cross-sectional schematic diagram of a transparent display device according to an embodiment of the present invention.

Figures 4A to 4C are schematic cross-sectional views of some stages of a method for manufacturing the transparent display device of Figure 1.

Figure 5 is a partial cross-sectional schematic diagram of a transparent display device according to an embodiment of the present invention.

Figure 6 is a partial cross-sectional schematic diagram of a transparent display device according to an embodiment of the present invention.

Figure 7 is a top-down schematic diagram of a micro-LED and a conductive layer of a transparent display device according to an embodiment of the present invention.

Figure 8 is a top-down schematic diagram of a micro-LED and a conductive layer of a transparent display device according to an embodiment of the present invention.

Figure 9 is a flow chart of a method for manufacturing a transparent display device according to some embodiments of the present invention.

Figure 10A is a top view schematic diagram of a spliced display device according to one embodiment of the present invention.

Figure 10B is a schematic cross-sectional view taken along line A-A' of Figure 10A.

FIG1 is a partial cross-sectional schematic diagram of a transparent display device 10A according to an embodiment of the present invention. Referring to FIG1 , the transparent display device 10A includes a circuit substrate 100, a micro-LED 200, a protective layer 300, a water-blocking structure 400, and an encapsulation layer 500.

The circuit substrate 100 has a transmissive region TR and a non-transmissive region NTR. In some embodiments, the transmissive region TR of the circuit substrate 100 is made of a transparent material, allowing light to pass through the transmissive region TR; while the non-transmissive region NTR of the circuit substrate 100 includes a non-transmissive material (e.g., a metal material, a semiconductor material, etc.).

In some embodiments, circuit substrate 100 includes a transparent substrate 110. Transparent substrate 110 may be made of glass, organic materials, or other suitable materials. Transparent substrate 110 may be a rigid substrate, a flexible substrate, or a stretchable substrate. In some embodiments, a buffer layer 112 is disposed on a surface of transparent substrate 110.

In this embodiment, the circuit substrate 100 includes multiple conductive pattern layers and multiple insulating layers. For example, the circuit substrate 100 includes a semiconductor layer 120, a first insulating layer 113, a first conductive pattern layer 130, a second insulating layer 114, a second conductive pattern layer 140, a third insulating layer 191, a third conductive pattern layer 150, a fourth insulating layer 192, a first buffer layer 115, a fourth conductive pattern layer 160, a fifth insulating layer 193, a second buffer layer 116, a fifth conductive pattern layer 170, a third buffer layer 117, a black matrix (BM), a fourth buffer layer 118, a sixth conductive pattern layer 180, and a passivation layer 119. In some embodiments, the number of semiconductor layers, conductive pattern layers, insulation layers, and buffer layers in the circuit substrate 100 can be adjusted as needed.

Semiconductor layer 120 is located on buffer layer 112. In some embodiments, semiconductor layer 120 is a single-layer or multi-layer structure, and includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single-crystalline silicon, an organic semiconductor material, an oxide semiconductor material (e.g., indium zinc oxide, indium gallium zinc oxide, or other suitable materials or combinations thereof), or other suitable materials or combinations thereof. In this embodiment, semiconductor layer 120 includes a channel region and doped regions located on both sides of the channel region. In some embodiments, the doped regions include lightly doped regions and heavily doped regions.

The first insulating layer 113 is located on the semiconductor layer 120.

The first conductive pattern layer 130 is located on the first insulating layer 113 and includes a gate 131 and a conductive feature 132. The gate 131 overlaps the channel region of the semiconductor layer 120. The conductive feature 132 is, for example, a signal line or other conductive structure.

The second insulating layer 114 is located on the first conductive pattern layer 130. The second conductive pattern layer 140 is located on the second insulating layer 114. The second conductive pattern layer 140 may include, for example, signal lines or other conductive structures. In some embodiments, the second insulating layer 114 and the second conductive pattern layer 140 may be omitted.

The third insulating layer 191 is located on the second conductive pattern layer 140 and the second insulating layer 114. In some embodiments, the third insulating layer 191 may also be referred to as an interlayer dielectric layer.

The third conductive pattern layer 150 is located on the third insulating layer 191 and includes a first source/drain 151, a second source/drain 152, and a conductive feature 153. The first source/drain 151 and the second source/drain 152 pass through the third insulating layer 191, the second insulating layer 114, and the first insulating layer 113 and connect to the doped region of the semiconductor layer 120. The conductive feature 153 is, for example, a signal line or other conductive structure.

In this embodiment, the active device T is located on the transparent substrate 110 and includes a semiconductor layer 120, a gate 131, a first source/drain 151, and a second source/drain 152. In this embodiment, the active device T is exemplified by a top-gate thin-film transistor, but the present invention is not limited thereto. In other embodiments, the active device T may also be a bottom-gate thin-film transistor, a double-gate thin-film transistor, or other types of thin-film transistors.

The fourth insulating layer 192 is located on the third conductive pattern layer 150. In some embodiments, the fourth insulating layer 192 may also be referred to as a planarization layer.

First buffer layer 115 is located on fourth insulating layer 192. Fourth conductive pattern layer 160 is located on first buffer layer 115. Portions of fourth conductive pattern layer 160 form conductive vias that penetrate fourth insulating layer 192 and connect to third conductive pattern layer 150. In this embodiment, first buffer layer 115 is located only on the top surface of fourth insulating layer 192 and between the top surface of fourth insulating layer 192 and fourth conductive pattern layer 160. In other embodiments, in addition to being located on the top surface of the fourth insulating layer 192, the first buffer layer 115 also fills the through holes of the fourth insulating layer 192 and laterally surrounds the fourth conductive pattern layer 160 to connect to the conductive vias of the third conductive pattern layer 150.

The fifth insulating layer 193 is located on the fourth conductive pattern layer 160. In some embodiments, the fifth insulating layer 193 may also be referred to as a planarization layer.

The second buffer layer 116 is located on the fifth insulating layer 193. The fifth conductive pattern layer 170 is located on the second buffer layer 116. A portion of the fifth conductive pattern layer 170 forms a conductive via that passes through the fifth insulating layer 193 and connects to the fourth conductive pattern layer 160. In this embodiment, the second buffer layer 116 is located only on the top surface of the fifth insulating layer 193 and between the top surface of the fifth insulating layer 193 and the fifth conductive pattern layer 170. In other embodiments, in addition to being located on the top surface of the fifth insulating layer 193, the second buffer layer 116 also fills the through holes of the fifth insulating layer 193 and laterally surrounds the fifth conductive pattern layer 170 to connect to the conductive vias of the fourth conductive pattern layer 160.

The third buffer layer 117 is located on the fifth conductive pattern layer 170. The black matrix BM is located on the third buffer layer 117.

The fourth buffer layer 118 is located on the black matrix BM. The sixth conductive pattern layer 180 is located on the fourth buffer layer 118 and includes a plurality of pads 181 and 182. In this embodiment, the pad 181 is electrically connected to the first source/drain 151 of the active device T via the fifth conductive pattern layer 170 and the fourth conductive pattern layer 160.

The passivation layer 119 overlies the pads 181 and 182. In some embodiments, the material of the passivation layer 119 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials.

In this embodiment, the semiconductor layer 120 , the first conductive pattern layer 130 , the second conductive pattern layer 140 , the third conductive pattern layer 150 , the fourth conductive pattern layer 160 , the fifth conductive pattern layer 170 , the black matrix BM, and the sixth conductive pattern layer 180 are distributed in the non-transmitting region NTR of the circuit substrate 100 . The first insulating layer 113, the second insulating layer 114, the third insulating layer 191, the fourth insulating layer 192, the first buffer layer 115, the fifth insulating layer 193, the second buffer layer 116, the third buffer layer 117, the fourth buffer layer 118, and the passivation layer 119 are disposed in the non-transmitting region NTR, and at least a portion of these layers extends from the non-transmitting region NTR to the transmitting region TR. For example, the first insulating layer 113, the second insulating layer 114, the third insulating layer 191, the fourth insulating layer 192, the fifth insulating layer 193, the third buffer layer 117, the fourth buffer layer 118, and the passivation layer 119 extend from the non-transmitting region NTR to the transmitting region TR, while the first buffer layer 115 and the second buffer layer 116 are only provided in the non-transmitting region NTR and do not extend to the transmitting region TR. By removing the first buffer layer 115 and the second buffer layer 116 from the transmitting region TR, the transmittance of the transmitting region TR can be improved.

The micro-LEDs 200 are disposed on the non-transmissive region NTR of the circuit substrate 100. In this embodiment, the micro-LEDs 200 include horizontal LEDs, but the present disclosure is not limited thereto. In other embodiments, the micro-LEDs 200 include vertical LEDs or other types of LEDs. The black matrix (BM) is located above the transparent substrate 110 and surrounds the micro-LEDs 200. In some embodiments, the black matrix (BM) does not overlap the micro-LEDs 200.

The microLED 200 is bonded to the circuit substrate 100. For example, the microLED 200 is bonded to the pads 181 and 182, and the joints 210 between the microLED 200 and the pads 181 and 182 include solder, conductive glue, or other suitable conductive structures. The joints 210 pass through the passivation layer 119, and the passivation layer 119 surrounds the joints 210.

The protective layer 300 is disposed on the non-transmitting region NTR of the circuit substrate 100 and covers the top surface 200t and sidewalls 200s of the micro-LED. In some embodiments, the protective layer 300 is formed on the passivation layer 119 and fills the gap between the micro-LED 200 and the passivation layer 119. In some embodiments, the protective layer 300 surrounds the micro-LED 200 and the contacts 210 between the micro-LED 200 and the pads 181 and 182 to protect the micro-LED 200 and the contacts 210. In some embodiments, the protective layer 300 includes photoresist, transparent optical adhesive, or other suitable materials and has a structure that is narrow at the top and wide at the bottom.

The water-blocking structure 400 is located on the protective layer 300, and the micro-LED 200 is separated from the water-blocking structure 400 by the protective layer 300. The water-blocking structure 400 extends from the top surface 300t of the protective layer 300 along the sidewalls 300s of the protective layer 300 to the passivation layer 119, covering the boundary between the protective layer 300 and the passivation layer 119, preventing moisture from diffusing from the interface between the protective layer 300 and the passivation layer 119 to the micro-LED 200.

In some embodiments, water-blocking structure 400 includes a multi-layer structure, such as an oxide layer 410 (e.g., comprising silicon oxide or other suitable oxides) and a nitride layer 420 (e.g., comprising silicon nitride or other suitable nitrides) overlapping oxide layer 410. In some embodiments, water-blocking structure 400 may further include more insulating layers.

The water-blocking structure 400 includes an opening 400H that overlaps the top surface 200t of the micro-LED 200, thereby reducing interference (e.g., refraction) caused by the water-blocking structure 400 with light emitted by the micro-LED 200. In this embodiment, the shapes of the oxide layer 410 and the nitride layer 420 are defined using the same mask pattern. Therefore, the vertical projection of the oxide layer 410 on the transparent substrate 110 is substantially equal to the vertical projection of the nitride layer 420 on the transparent substrate 110, and the sidewalls of the oxide layer 410 and the sidewalls of the nitride layer 420 are aligned. However, in other embodiments, the shapes of the oxide layer 410 and the nitride layer 420 may be defined by different mask patterns, such that the vertical projection of the oxide layer 410 on the transparent substrate 110 is different from the vertical projection of the nitride layer 420 on the transparent substrate 110, as shown in the transparent display device 10B of FIG. 2 . In the transparent display device 10B, the nitride layer 420 may cover the sidewalls of the oxide layer 410.

Returning to Figure 1 , in this embodiment, the water-blocking structure 400 is disposed on the non-transmission region NTR and does not overlap the transmission region TR, thereby increasing the transmittance of the transmission region TR. However, in other embodiments, the water-blocking structure 400 overlaps the transmission region TR, as shown in the transparent display device 10C of Figure 3 .

Returning to Figure 1 , encapsulation layer 500 covers water-blocking structure 400 and protective layer 300 . In this embodiment, encapsulation layer 500 fills opening 400H in water-blocking structure 400 and contacts protective layer 300 through opening 400H. In some embodiments, encapsulation layer 500 is made of transparent resin, transparent adhesive, transparent silicone, or other suitable materials.

Figures 4A to 4C are cross-sectional schematic diagrams illustrating certain stages of a method for manufacturing the transparent display device 10A of Figure 1 . Referring to Figure 4A , a micro-LED 200 is bonded to pads 181 and 182 of a circuit substrate 100 . For example, the micro-LED 200 is transferred from a growth substrate or an interposer to the circuit substrate 100 via a mass transfer process. The micro-LED 200 is then connected to the circuit substrate 100 via solder, conductive adhesive, or other connecting structures.

Referring to FIG. 4B , a protective layer 300 is formed on the micro-LEDs 200 . For example, a photoresist material is coated on the circuit substrate 100 , and then an exposure process and a development process are performed to form the protective layer 300 covering the micro-LEDs 200 . In some embodiments, each protective layer 300 covers one or more micro-LEDs 200 .

Referring to Figure 4C , a water-blocking structure 400 is formed on the protective layer 300 . For example, an oxide material layer and a nitride material layer are sequentially deposited, and then etched using a mask pattern to form an oxide layer 410 and a nitride layer 420 . Because the oxide layer 410 and the nitride layer 420 are defined using the same mask pattern, the oxide layer 410 and the nitride layer 420 have the same vertical projection shape, and the sidewalls of the oxide layer 410 are aligned with the sidewalls of the nitride layer 420 .

In other embodiments, the oxide material layer and the nitride material layer may be defined using different mask patterns. For example, after depositing the oxide material layer, the oxide material layer is etched using a first mask pattern to obtain an oxide layer 410. A nitride material layer is then deposited on the oxide layer 410. A second mask pattern is then used to etch the nitride material layer to obtain a nitride layer 420, resulting in the water-blocking structure 400 shown in FIG. 2 .

Finally, a packaging layer 500 is formed on the water-blocking structure 400 and the protective layer 300, as shown in Figure 1.

Figure 5 is a partial cross-sectional schematic diagram of a transparent display device 10D according to an embodiment of the present invention. It should be noted that the embodiment of Figure 5 retains the same component numbers and some details as the embodiment of Figure 1 , with identical or similar reference numbers used to represent identical or similar components, and descriptions of identical technical details omitted. For descriptions of omitted sections, please refer to the aforementioned embodiments and will not be repeated here.

The difference between the transparent display device 10D in FIG5 and the display device 10A in FIG1 is that the transparent display device 10D further includes a conductive layer 600.

The conductive layer 600 is sandwiched between the protective layer 300 and the water-blocking structure 400 and is located between the sidewalls 200s of the micro-LED 200 and the water-blocking structure 400. The conductive layer 600 extends from the top surface 300t of the protective layer 300 along the sidewalls 300s of the protective layer 300 to the passivation layer 119. In some embodiments, the conductive layer 600 is formed by evaporation, coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes.

In this embodiment, the conductive layer 600 is located on the non-transmitting region NTR and does not overlap the transmitting region TR. The conductive layer 600 serves as an anti-static structure, reducing damage to components caused by static electricity. Because the anti-static structure is positioned around the micro-LEDs 200, it is unnecessary to provide additional anti-static structures (such as anti-static rings) around the perimeter of the transparent display device 10D. This reduces the size of the bezel of the transparent display device 10D. In some embodiments, the conductive layer 600 is connected to ground or another DC voltage.

In some embodiments, the conductive layer 600 includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or other suitable materials. In embodiments where the conductive layer 600 includes a transparent conductive material, the conductive layer 600 may extend from the non-transmitting region NTR to the transmitting region TR and overlap the transmitting region TR.

In some embodiments, the conductive layer 600 has a through hole 600H that overlaps the top surface 200t of the micro-LED 200. In this embodiment, the conductive layer 600 and the oxide layer 410 and nitride layer 420 of the water-blocking structure 400 are defined using the same mask pattern. Therefore, the conductive layer 600, the oxide layer 410, and the nitride layer 420 have the same vertical projection shape on the transparent substrate 110, and the sidewalls of the through hole 600H are aligned with the sidewalls of the opening 400H. However, in other embodiments, the conductive layer 600 and the water-blocking structure 400 can be defined using different mask patterns. For example, a conductive material layer is first etched using a mask pattern to obtain a conductive layer 600 including a through-hole 600H. The water-blocking structure 400 is then formed on the conductive layer 600. In this case, the vertical projection of the conductive layer 600 on the transparent substrate 110 can be different from the vertical projection of the oxide layer 410 on the transparent substrate 110 and the vertical projection of the nitride layer 420 on the transparent substrate 110, as shown in the transparent display device 10E of FIG6 .

The encapsulation layer 500 covers the water-blocking structure 400 and the protective layer 300 , fills the opening 400H of the water-blocking structure 400 and the through-hole 600H of the shielding structure 600 , and contacts the protective layer 300 .

Figure 7 is a top-down schematic diagram of a micro-LED 200 and a conductive layer 600 in a transparent display device according to an embodiment of the present invention. It should be noted that the embodiment of Figure 7 retains the same component numbers and some details as the embodiment of Figure 6 , with identical or similar reference numbers used to represent identical or similar components, and descriptions of identical technical details omitted. For descriptions of omitted sections, please refer to the aforementioned embodiments and will not be repeated here.

Referring to FIG. 7 , in this embodiment, each pixel includes a plurality of micro-LEDs 200. For example, three adjacent micro-LEDs 200 constitute a pixel, and are respectively a red micro-LED, a green micro-LED, and a blue micro-LED. The micro-LEDs 200 are bonded to pads 181 and 182.

The conductive layer 600, as seen from above, includes a mesh structure 610 and a shielding structure 620. The mesh structure 610 overlaps the non-transmitting region NTR, and beneath the mesh structure 610 are a black matrix, multiple signal lines, and other conductive features (not shown in FIG7 , see FIG5 ). The shielding structure 620 extends from the mesh structure 610 toward the micro-LEDs 200 and has through-holes 600H that overlap the top surfaces of the micro-LEDs 200. The water-blocking structure 400 (not shown in FIG7 , see FIG5 ) is formed on the shielding structure 620, with the through-holes 600H of the shielding structure 620 overlapping the openings 400H of the water-blocking structure 400.

In this embodiment, each shielding structure 620 is stacked on one micro-LED 200, but the present disclosure is not limited thereto. In other embodiments, a single micro-LED 200 is stacked on multiple micro-LEDs 200, as shown in FIG8 .

FIG9 is a flow chart of a method for manufacturing a transparent display device according to some embodiments of the present invention. Referring to FIG9 , in step S1, a micro-LED is bonded to a circuit substrate, as shown in FIG4A .

Optionally, in step S2, the micro-LEDs are tested and any faulty micro-LEDs are repaired.

In step S3, a protective layer is formed to cover the micro-LEDs, as shown in FIG4B . In some embodiments, the micro-LEDs covered by the protective layer may be repaired micro-LEDs or unrepaired micro-LEDs.

Optionally, in step S4, a conductive layer is formed. The transparent display device including the conductive layer is shown in FIG5 or FIG6.

In step S5, a water-blocking structure is formed, as shown in FIG4C .

Finally, in step S6, a packaging layer is formed, as shown in Figure 1.

Figure 10A is a schematic top view of a spliced display device according to one embodiment of the present invention. Figure 10B is a schematic cross-sectional view taken along line A-A' in Figure 10A. Referring to Figures 10A and 10B, in this embodiment, two or more transparent display devices 10A are spliced together to form a spliced display device. In this embodiment, the transparent display device 10A described in Figure 1 and the related paragraphs is used as an example, but the present invention is not limited thereto. In other embodiments, multiple transparent display devices described in other embodiments are spliced together to form a spliced display device.

In this embodiment, the protective layer 300 and the water-blocking structure 400 prevent moisture from entering from the edge of the transparent display device 10A and damaging the micro-LEDs 200. Therefore, the micro-LEDs 200 can be placed very close to the edge of the transparent display device 10A, thereby achieving a narrow bezel or seamless splicing.

10A: Transparent display device

100: Circuit board

110:Transparent substrate

112: Buffer layer

113: First Insulation Layer

114: Second insulation layer

115: First buffer layer

116: Second buffer layer

117: Third buffer layer

118: Fourth buffer layer

119: Passivation layer

120: Semiconductor layer

130: First conductive pattern layer

131: Gate

132: Conductive characteristics

140: Second conductive pattern layer

150: Third conductive pattern layer

151: First source/drain

152: Second source/drain

153: Conductive characteristics

160: Fourth conductive pattern layer

170: Fifth conductive pattern layer

180: Sixth conductive pattern layer

181,182: Pad

191: The third insulating layer

192: Fourth Insulation Layer

193: Fifth Insulation Layer

200: Micro LED

200s, 300s: Sidewall

200t, 300t: Top

210: Contact

300: Protective layer

400: Water-blocking structure

400H: Open

410: Oxide layer

420: Nitride layer

500: Packaging layer

BM: Black Matrix

T: Active element

TR: Penetration Zone

NTR: Non-penetrating zone

Claims (10)

A transparent display device comprises: a circuit substrate having a transmissive region and a non-transmissive region; a micro-LED disposed on the non-transmissive region and bonded to the circuit substrate; a protective layer disposed on the non-transmissive region and covering the top surface and sidewalls of the micro-LED; and a water-blocking structure, wherein the micro-LED is separated from the water-blocking structure by the protective layer, and the water-blocking structure includes an opening overlapping the top surface of the micro-LED. A transparent display device as described in claim 1, wherein the water-blocking structure does not overlap with the penetration area. A transparent display device as described in claim 1, wherein the water-blocking structure overlaps the penetration area. The transparent display device of claim 1 further comprises: A conductive layer sandwiched between the protective layer and the water-blocking structure, and the conductive layer is located between the sidewall of the micro-LED and the water-blocking structure, wherein the conductive layer comprises a mesh structure in a top view. The transparent display device of claim 4, wherein the conductive layer is connected to a ground voltage. The transparent display device of claim 1, wherein the protective layer comprises photoresist or transparent optical adhesive and surrounds the contact between the micro light-emitting diode and the circuit substrate. The transparent display device as described in claim 1, wherein the water-blocking structure includes a multi-layer structure. The transparent display device of claim 1, wherein the circuit substrate comprises: a transparent substrate; a black matrix located above the transparent substrate and surrounding the micro-LED; a pad located above the transparent substrate, wherein the micro-LED is bonded to the pad; a passivation layer overlying the pad and surrounding the contact between the micro-LED and the pad, wherein the protective layer is formed on the passivation layer and surrounds the micro-LED and the contact, wherein the water-blocking structure extends from the top surface of the protective layer along the side surface of the protective layer to the passivation layer, wherein the water-blocking structure includes an oxide layer and a nitride layer overlapping the oxide layer, and the vertical projection shape of the oxide layer on the transparent substrate is substantially equal to the vertical projection shape of the nitride layer on the transparent substrate; and A packaging layer covers the water-blocking structure and the protective layer, wherein the packaging layer fills the opening of the water-blocking structure and contacts the protective layer. The transparent display device of any one of claims 1 to 8, wherein the circuit substrate comprises: a transparent substrate; a black matrix located above the transparent substrate and surrounding the micro-LED; a pad located above the transparent substrate, wherein the micro-LED is bonded to the pad; a passivation layer overlying the pad and surrounding a connection between the micro-LED and the pad, wherein the protective layer is formed on the passivation layer and surrounding the micro-LED and the connection; a conductive layer extending from a top surface of the protective layer along a side surface of the protective layer to the passivation layer, and comprising: A mesh structure overlying the non-penetrating region; A shielding structure extending from the mesh structure toward the micro-LED and having a through hole overlying the top surface of the micro-LED, wherein the water-blocking structure is formed on the shielding structure, and the through hole of the shielding structure overlies the opening of the water-blocking structure; and An encapsulation layer covering the water-blocking structure and the protective layer, wherein the encapsulation layer fills the opening of the water-blocking structure and the through hole of the shielding structure and contacts the protective layer. A spliced display device comprising: Two or more transparent display devices as described in claim 1 spliced together.