CN120548006A - Transparent display device and spliced display device - Google Patents

Abstract

A transparent display device includes a circuit substrate, a micro-LED, a protective layer, and a water-blocking structure. The circuit substrate has a transmissive region and a non-transmissive region. The micro-LED is disposed on the non-transmissive region and bonded to the circuit substrate. The protective layer is disposed on the non-transmissive region and covers the top surface and sidewalls of the micro-LED. The micro-LED is separated from the water-blocking structure by the protective layer, and the water-blocking structure includes an opening that overlaps the top surface of the micro-LED.

Description

Transparent display device and spliced display device

Technical Field

The invention relates to a transparent display device and a spliced display device.

Background

A light emitting diode (LIGHT EMITTING diode, LED) display device is a high-performance light source technology, and is widely used in displays, lighting and multimedia devices. The structure of the display device generally comprises an array formed by arranging a plurality of micro light emitting diodes (micro LEDs), and the light emitting state of each micro light emitting diode is controlled by a driving circuit so as to display the display effect with high resolution and high brightness. In order to improve the stability and lifetime of the device, packaging technology is generally used to isolate moisture and impurities in the external environment.

However, when the display device is subjected to moisture intrusion, various problems such as corrosion of the metal electrode, a decrease in luminous efficiency, and the like may be caused. These problems not only affect the display quality, but may also shorten the service life of the device. Therefore, moisture shielding technology is a critical design consideration.

Disclosure of Invention

The invention provides a transparent display device and a spliced display device.

At least one embodiment of the present invention provides a transparent display device, which includes a circuit substrate, a micro light emitting diode, a protective layer, and a water blocking structure. The circuit substrate is provided with a penetrating area and a non-penetrating area. The micro light emitting diode is arranged on the non-penetrating area and is bonded to the circuit substrate. The protective layer is arranged on the non-penetrating area and covers the top surface and the side wall of the miniature light emitting diode. The micro light emitting diode is separated from the water blocking structure by the protective layer, and the water blocking structure comprises an opening overlapped on the top surface of the micro light emitting diode.

At least one embodiment of the present invention provides a tiled display device, which includes more than two transparent display devices tiled together.

Drawings

Fig. 1 is a schematic partial cross-sectional view of a transparent display device according to an embodiment of the invention.

Fig. 2 is a schematic partial cross-sectional view of a transparent display device according to an embodiment of the invention.

Fig. 3 is a schematic partial cross-sectional view of a transparent display device according to an embodiment of the invention.

Fig. 4A to 4C are schematic cross-sectional views of some stages of a manufacturing method of manufacturing the transparent display device of fig. 1.

Fig. 5 is a schematic partial cross-sectional view of a transparent display device according to an embodiment of the invention.

Fig. 6 is a schematic partial cross-sectional view of a transparent display device according to an embodiment of the invention.

Fig. 7 is a schematic top view of a micro light emitting diode and a conductive layer of a transparent display device according to an embodiment of the invention.

Fig. 8 is a schematic top view of a micro led and a conductive layer of a transparent display device according to an embodiment of the invention.

Fig. 9 is a flowchart of a method of manufacturing a transparent display device according to some embodiments of the present invention.

Fig. 10A is a schematic top view of a tiled display device according to an embodiment of the invention.

Fig. 10B is a schematic cross-sectional view along line A-A' of fig. 10A.

Wherein the reference numerals are as follows:

10A,10B,10C,10D,10E: transparent display device

100 Circuit board

110 Transparent substrate

112 Buffer layer

113 First insulating layer

114 Second insulating layer

115 First buffer layer

116 Second buffer layer

117 Third buffer layer

118 Fourth buffer layer

119 Passivation layer

120 Semiconductor layer

130 First conductive pattern layer

131 Grid electrode

132 Conductive features

140 Second conductive pattern layer

150 Third conductive pattern layer

151 First source/drain

152 Second source/drain

153 Conductive features

160 Fourth conductive pattern layer

170 Fifth conductive pattern layer

180 Sixth conductive pattern layer

181,182 Joint pad

191 Third insulating layer

192 Fourth insulating layer

193 Fifth insulating layer

200 Micro light emitting diode

200S,300s sidewall

200T,300t top surface

210 Contact point

300 Protective layer

400 Water-blocking structure

400H opening

410 Oxide layer

420 Nitride layer

500 Packaging layer

600 Conductive layer

600H through hole

BM black matrix

S1, S2, S3, S4, S5, S6 step

T is active element

TR penetration zone

NTR, non-penetrating region.

Detailed Description

Fig. 1 is a schematic partial cross-sectional view of a transparent display device 10A according to an embodiment of the invention. Referring to fig. 1, the transparent display device 10A includes a circuit substrate 100, a micro light emitting diode 200, a protective layer 300, a water blocking structure 400, and an encapsulation layer 500.

The circuit substrate 100 has a penetrating region TR and a non-penetrating region NTR. In some embodiments, the transmissive region TR of the circuit substrate 100 is made of a transparent material so that light can pass through the transmissive region TR of the circuit substrate 100, and the non-transmissive region NTR of the circuit substrate 100 comprises a non-transparent material (e.g., a metal material, a semiconductor material, etc.).

In some embodiments, the circuit substrate 100 includes a transparent substrate 110. The material of the transparent substrate 110 includes glass, an organic material, or other suitable materials. The transparent substrate 110 may be a hard substrate, a flexible substrate, or a stretchable substrate. In some embodiments, the buffer layer 112 is disposed on a surface of the transparent substrate 110.

In the present embodiment, the circuit substrate 100 includes a plurality of conductive pattern layers and a plurality of insulating layers. For example, the circuit substrate 100 includes a semiconductor layer 120, a first insulating layer 113, a first conductive pattern layer 130, a second insulating layer 114, a second conductive pattern layer 140, a third insulating layer 191, a third conductive pattern layer 150, a fourth insulating layer 192, a first buffer layer 115, a fourth conductive pattern layer 160, a fifth insulating layer 193, a second buffer layer 116, a fifth conductive pattern layer 170, a third buffer layer 117, a black matrix BM, a fourth buffer layer 118, a sixth conductive pattern layer 180, and a passivation layer 119. In some embodiments, the number of semiconductor layer conductive pattern layers, insulating layers, and buffer layers in the circuit substrate 100 may be adjusted as desired.

The semiconductor layer 120 is located on the buffer layer 112. In some embodiments, the semiconductor layer 120 is a single-layer or multi-layer structure comprising amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material (e.g., indium zinc oxide, indium gallium zinc oxide, or other suitable material, or a combination thereof), or other suitable material or combination thereof. In this embodiment, the semiconductor layer 120 includes a channel region and doped regions located at two sides of the channel region. In some embodiments, the doped region includes a lightly doped region and a heavily doped region.

The first insulating layer 113 is located on the semiconductor layer 120.

The first conductive pattern layer 130 is located on the first insulating layer 113, and includes a gate 131 and a conductive feature 132. The gate electrode 131 overlaps the channel region of the semiconductor layer 120. The conductive features 132 are, for example, signal lines or other conductive structures.

The second insulating layer 114 is positioned on the first conductive pattern layer 130. The second conductive pattern layer 140 is positioned on the second insulating layer 114. The second conductive pattern layer 140 includes, for example, a signal line or other conductive structure. In some embodiments, the second insulating layer 114 and the second conductive pattern layer 140 may be omitted.

The third insulating layer 191 is positioned on the second conductive pattern layer 140 and the second insulating layer 114. In some embodiments, the third insulating layer 191 may also be referred to as an interlayer dielectric layer.

The third conductive pattern layer 150 is disposed on the third insulating layer 191 and includes a first source/drain 151, a second source/drain 152, and a conductive feature 153. The first source/drain 151 and the second source/drain 152 pass through the third insulating layer 191, the second insulating layer 114, and the first insulating layer 113, and are connected to the doped region of the semiconductor layer 120. The conductive features 153 are, for example, signal lines or other conductive structures.

In the present embodiment, the active device T is disposed on the transparent substrate 110 and includes the semiconductor layer 120, the gate 131, the first source/drain 151 and the second source/drain 152. In the present embodiment, the active device T is exemplified by a top gate type thin film transistor, but the invention is not limited thereto. In other embodiments, the active device T may be a bottom gate type thin film transistor, a dual gate type thin film transistor, or other types of thin film transistors.

The fourth insulating layer 192 is positioned on the third conductive pattern layer 150. In some embodiments, the fourth insulating layer 192 may also be referred to as a planarization layer.

The first buffer layer 115 is positioned on the fourth insulating layer 192. The fourth conductive pattern layer 160 is positioned on the first buffer layer 115. A portion of the fourth conductive pattern layer 160 forms a conductive via through the fourth insulating layer 192 and connected to the third conductive pattern layer 150. In the present embodiment, the first buffer layer 115 is only located on the top surface of the fourth insulating layer 192, and is located between the top surface of the fourth insulating layer 192 and the fourth conductive pattern layer 160. In other embodiments, the first buffer layer 115 may fill the via hole of the fourth insulating layer 192 in addition to being located on the top surface of the fourth insulating layer 192, and laterally surround the conductive via hole of the fourth conductive pattern layer 160 to be connected to the third conductive pattern layer 150.

A fifth insulating layer 193 is positioned on the four conductive pattern layers 160. In some embodiments, the fifth insulating layer 193 may also be referred to as a planarization layer.

The second buffer layer 116 is positioned on the fifth insulating layer 193. The fifth conductive pattern layer 170 is positioned on the second buffer layer 116. A portion of the fifth conductive pattern layer 170 forms a conductive via through the fifth insulating layer 193 and connected to the fourth conductive pattern layer 160. In the present embodiment, the second buffer layer 116 is only located on the top surface of the fifth insulating layer 193, and is located between the top surface of the fifth insulating layer 193 and the fifth conductive pattern layer 170. In other embodiments, the second buffer layer 116 fills the through holes of the fifth insulating layer 193 except on the top surface of the fifth insulating layer 193, and is laterally connected to the conductive through holes of the fourth conductive pattern layer 160 around the fifth conductive pattern layer 170.

The third buffer layer 117 is positioned on the fifth conductive pattern layer 170. The black matrix BM is located on the third buffer layer 117.

The fourth buffer layer 118 is located on the black matrix BM. The sixth conductive pattern layer 180 is disposed on the fourth buffer layer 118 and includes a plurality of pads 181,182. In the present embodiment, the pad 181 is electrically connected to the first source/drain 151 of the active device T through the fifth conductive pattern layer 170 and the fourth conductive pattern layer 160.

Passivation layer 119 overlies bond pads 181,182. In some embodiments, the material of passivation layer 119 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating material.

In the present embodiment, the semiconductor layer 120, the first conductive pattern layer 130, the second conductive pattern layer 140, the third conductive pattern layer 150, the fourth conductive pattern layer 160, the fifth conductive pattern layer 170, the black matrix BM, and the sixth conductive pattern layer 180 are distributed in the non-penetrating region NTR of the circuit substrate 100. The first insulating layer 113, the second insulating layer 114, the third insulating layer 191, the fourth insulating layer 192, the first buffer layer 115, the fifth insulating layer 193, the second buffer layer 116, the third buffer layer 117, the fourth buffer layer 118, and the passivation layer 119 are disposed in the non-penetrating region NTR, and at least a portion of these layers extend from the non-penetrating region NTR to the penetrating region TR. For example, the first insulating layer 113, the second insulating layer 114, the third insulating layer 191, the fourth insulating layer 192, the fifth insulating layer 193, the third buffer layer 117, the fourth buffer layer 118, and the passivation layer 119 extend from the non-penetrating region NTR to the penetrating region TR, and the first buffer layer 115 and the second buffer layer 116 are disposed only in the non-penetrating region NTR and do not extend to the penetrating region TR. By removing the first buffer layer 115 and the second buffer layer 116 in the penetration region TR, the penetration rate of the penetration region TR may be increased.

The micro light emitting diode 200 is disposed on the non-penetrating region NTR of the circuit substrate 100. In the present embodiment, the micro light emitting diode 200 includes a horizontal light emitting diode, but the disclosure is not limited thereto. In other embodiments, the micro light emitting diode 200 comprises a vertical light emitting diode or other type of light emitting diode. The black matrix BM is located above the transparent substrate 110 and around the micro light emitting diode 200. In some embodiments, the black matrix BM does not overlap the micro led 200.

The micro light emitting diode 200 is bonded to the circuit substrate 100. For example, the micro light emitting diode 200 is bonded to the bonding pads 181,182, and the contact 210 between the micro light emitting diode 200 and the bonding pads 181,182 comprises solder, conductive paste, or other suitable conductive structure. The contact 210 passes through the passivation layer 119, and the passivation layer 119 surrounds the contact 210.

The passivation layer 300 is disposed on the non-penetrating region NTR of the circuit substrate 100 and covers the top surface 200t and the sidewalls 200s of the micro light emitting diode. In some embodiments, the protection layer 300 is formed on the passivation layer 119 and fills in between the micro light emitting diode 200 and the passivation layer 119. In some embodiments, the protection layer 300 surrounds the micro light emitting diode 200 and the contact 210 between the micro light emitting diode 200 and the pads 181,182 to protect the micro light emitting diode 200 and the contact 210. In some embodiments, the protective layer 300 includes photoresist, transparent optical glue, or other suitable material, and has a structure with a narrow top and a wide bottom.

The water blocking structure 400 is located on the protection layer 300, and the micro light emitting diode 200 is separated from the water blocking structure 400 by the protection layer 300. The water blocking structure 400 extends from the top surface 300t of the protection layer 300 to the passivation layer 119 along the sidewall 300s of the protection layer 300, and covers the boundary between the protection layer 300 and the passivation layer 119, so as to prevent moisture from diffusing from the interface between the protection layer 300 and the passivation layer 119 to the micro light emitting diode 200.

In some embodiments, the water blocking structure 400 includes a multi-layer structure, for example, including an oxide layer 410 (e.g., including silicon oxide or other suitable oxide) and a nitride layer 420 (e.g., including silicon nitride or other suitable nitride) overlying the oxide layer 410. In some embodiments, the water blocking structure 400 may also include additional insulation layers.

The water blocking structure 400 includes an opening 400H overlapping the top surface 200t of the micro led 200, thereby reducing interference (e.g., refraction) of the light emitted from the micro led 200 by the water blocking structure 400. In the present embodiment, the shapes of the oxide layer 410 and the nitride layer 420 are defined by the same mask pattern, so that the vertical projection shape of the oxide layer 410 on the transparent substrate 110 is substantially equal to the vertical projection shape of the nitride layer 420 on the transparent substrate 110, and the sidewalls of the oxide layer 410 are aligned with the sidewalls of the nitride layer 420. However, in other embodiments, the shapes of the oxide layer 410 and the nitride layer 420 may be defined by different mask patterns, such that the vertical projection shape of the oxide layer 410 on the transparent substrate 110 is not equal to the vertical projection shape of the nitride layer 420 on the transparent substrate 110, as shown in the transparent display device 10B of fig. 2. In the transparent display device 10B, the nitride layer 420 may cover the sidewalls of the oxide layer 410.

Referring back to fig. 1, in the present embodiment, the water blocking structure 400 is disposed on the non-penetrating region NTR and does not overlap the penetrating region TR, thereby increasing the penetrating rate of the penetrating region TR. However, in other embodiments, the water blocking structure 400 overlaps the penetrating region TR, as shown in the transparent display device 10C of fig. 3.

Returning to fig. 1, the encapsulation layer 500 covers the water blocking structure 400 and the protection layer 300. In this embodiment, the encapsulation layer 500 fills the opening 400H of the water blocking structure 400, and the opening 400H passing through contacts the protection layer 300. In some embodiments, the material of encapsulation layer 500 includes transparent resin, transparent adhesive, transparent silicone, or other suitable material.

Fig. 4A to 4C are schematic cross-sectional views of some stages of a manufacturing method of manufacturing the transparent display device 10A of fig. 1. Referring to fig. 4A, the micro light emitting diode 200 is bonded to the pads 181,182 of the circuit substrate 100. For example, the micro light emitting diode 200 is transferred from the growth substrate or the interposer substrate to the circuit substrate 100 through a mass transfer process, and then the micro light emitting diode 200 is connected to the circuit substrate 100 through solder, conductive paste or other connection structures.

Referring to fig. 4B, a passivation layer 300 is formed on the micro light emitting diode 200. For example, a photoresist material is coated on the circuit substrate 100, and then a passivation layer 300 is formed to cover the micro light emitting diode 200 through an exposure process and a development process. In some embodiments, each protective layer 300 covers one or more micro light emitting diodes 200.

Referring to fig. 4C, a water blocking structure 400 is formed on the passivation layer 300. For example, an oxide material layer and a nitride material layer are sequentially deposited, and then the oxide material layer and the nitride material layer are etched with a mask pattern to form an oxide layer 410 and a nitride layer 420. Since the oxide layer 410 and the nitride layer 420 are defined by the same mask pattern, the oxide layer 410 and the nitride layer 420 have the same vertical projection shape, and the sidewalls of the oxide layer 410 are aligned with the sidewalls of the nitride layer 420.

In other embodiments, the oxide material layer and the nitride material layer may be defined by different mask patterns. For example, after depositing the oxide material layer, the oxide material layer is etched using the first mask pattern to obtain the oxide layer 410. A layer of nitride material is then deposited over oxide layer 410. The nitride material layer is then etched using the second mask pattern to obtain the nitride layer 420, resulting in the water blocking structure 400 shown in fig. 2.

Finally, an encapsulation layer 500 is formed on the water blocking structure 400 and the protection layer 300, as shown in fig. 1.

Fig. 5 is a schematic partial cross-sectional view of a transparent display device 10D according to an embodiment of the invention. It should be noted that the embodiment of fig. 5 uses the element numbers and part of the content of the embodiment of fig. 1, where the same or similar numbers are used to denote the same or similar elements, and the description of the same technical content is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.

The transparent display device 10D of fig. 5 differs from the display device of fig. 1, fig. 10A, in that the transparent display device 10D further comprises a conductive layer 600.

The conductive layer 600 is sandwiched between the protective layer 300 and the water blocking structure 400, and is located between the sidewall 200s of the micro light emitting diode 200 and the water blocking structure 400. The conductive layer 600 extends from the top surface 300t of the protective layer 300 along the sidewalls 300s of the protective layer 300 to the passivation layer 119. In some embodiments, the manner in which the conductive layer 600 is formed includes evaporation, coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable process.

In this embodiment, the conductive layer 600 is located on the non-penetrating region NTR and does not overlap the penetrating region TR. The conductive layer 600 may be used as an antistatic structure for reducing the damage of static electricity to the device. Since the anti-static structure is disposed around the micro light emitting diode 200, it is unnecessary to additionally provide other anti-static structures (e.g., anti-static rings) at the peripheral region of the transparent display device 10D, and thus the frame size of the transparent display device 10D can be reduced. In some embodiments, the conductive layer 600 is connected to a ground voltage or other dc voltage.

In some embodiments, the conductive layer 600 includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or other suitable material. In embodiments in which the conductive layer 600 includes a transparent conductive material, the conductive layer 600 may extend from the non-penetrating region NTR to the penetrating region TR and overlap the penetrating region TR.

In some embodiments, the conductive layer 600 has a via hole 600H overlapping the top surface 200t of the micro led 200. In this embodiment, the conductive layer 600 and the oxide layer 410 and the nitride layer 420 of the water blocking structure 400 are defined by using the same mask pattern, so that the conductive layer 600, the oxide layer 410 and the nitride layer 420 have the same vertical projection shape on the transparent substrate 110, and the sidewall of the through hole 600H is aligned to the sidewall of the opening 400H. However, in other embodiments, the conductive layer 600 may be defined using a different mask pattern than the water blocking structure 400. For example, the conductive material layer is etched using a mask pattern to obtain the conductive layer 600 including the via hole 600H. The water blocking structure 400 is then formed on the conductive layer 600. In this case, the vertical projection shape of the conductive layer 600 on the transparent substrate 110 may be different from the vertical projection shape of the oxide layer 410 on the transparent substrate 110 and the vertical projection shape of the nitride layer 420 on the transparent substrate 110, as shown in the transparent display device 10E of fig. 6.

The encapsulation layer 500 covers the water blocking structure 400 and the protection layer 300, and fills the opening 400H of the water blocking structure 400 and the through hole 600H of the shielding structure 600, and contacts the protection layer 300.

Fig. 7 is a schematic top view of the micro led 200 and the conductive layer 600 of a transparent display device according to an embodiment of the invention. It should be noted that the embodiment of fig. 7 uses the element numbers and part of the content of the embodiment of fig. 6, where the same or similar numbers are used to denote the same or similar elements, and the description of the same technical content is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.

Referring to fig. 7, in the present embodiment, each pixel includes a plurality of micro light emitting diodes 200. For example, three adjacent micro light emitting diodes 200 form a pixel, and are respectively red micro light emitting diode, green micro light emitting diode and blue micro light emitting diode. Micro light emitting diode 200 is bonded to bonding pads 181,182.

The conductive layer 600 includes a mesh structure 610 and a shielding structure 620 in a top view. The mesh structure 610 overlaps the non-penetrating region NTR, and the bottom of the mesh structure 610 includes a black matrix, a plurality of signal lines, and other conductive features (not shown in fig. 7, please refer to fig. 5). The shielding structure 620 extends from the mesh structure 610 toward the micro light emitting diode 200 and has a through hole 600H overlapping the top surface of the micro light emitting diode 200. The water blocking structure 400 (not shown in fig. 7, please refer to fig. 5) is formed on the shielding structure 620, and the through hole 600H of the shielding structure 620 overlaps the opening 400H of the water blocking structure 400.

In the present embodiment, each shielding structure 620 overlaps one micro led 200, but the disclosure is not limited thereto. In other embodiments, a single micro led 200 overlaps multiple micro leds 200, as shown in fig. 8.

Fig. 9 is a flowchart of a method of manufacturing a transparent display device according to some embodiments of the present invention. Referring to fig. 9, in step S1, a micro light emitting diode is bonded to a circuit substrate, as shown in fig. 4A.

Optionally, at step S2, the micro light emitting diode is tested and the failed micro light emitting diode is repaired.

In step S3, a protective layer is formed to cover the micro light emitting diode as shown in fig. 4B. In some embodiments, the protective layer covered micro light emitting diode may be a repaired micro light emitting diode or an unrepaired micro light emitting diode.

Optionally, in step S4, a conductive layer is formed. A transparent display device including a conductive layer is shown in fig. 5 or 6.

In step S5, a water blocking structure is formed, as shown in fig. 4C.

Finally, in step S6, an encapsulation layer is formed, as shown in fig. 1.

Fig. 10A is a schematic top view of a tiled display device according to an embodiment of the invention. Fig. 10B is a schematic cross-sectional view along line A-A' of fig. 10A. Referring to fig. 10A and 10B, in the present embodiment, more than two transparent display devices 10A are spliced together to form a tiled display device. In the present embodiment, the transparent display device 10A described in fig. 1 and the related paragraphs is taken as an example, but the invention is not limited thereto. In other embodiments, the transparent display devices described in various other embodiments are tiled together to form a tiled display device.

In the present embodiment, the protection layer 300 and the water blocking structure 400 can prevent the micro light emitting diode 200 from being damaged by moisture entering from the edge of the transparent display device 10A. Therefore, the micro light emitting diode 200 may be disposed close to the edge of the transparent display device 10A, thereby achieving the purpose of narrow bezel or seamless stitching.

Claims (10)

1. A transparent display device, comprising:

a circuit substrate having a penetrating region and a non-penetrating region;

a micro light emitting diode disposed on the non-penetrating region and bonded to the circuit substrate;

A passivation layer disposed on the non-penetrating region and covering the top surface and the side walls of the micro light emitting diode, and

The micro light emitting diode is separated from the water blocking structure by the protective layer, and the water blocking structure comprises an opening overlapped on the top surface of the micro light emitting diode.

2. The transparent display of claim 1, wherein the water blocking structure does not overlap the transmissive region.

3. The transparent display of claim 1, wherein the water blocking structure overlaps the transmissive region.

4. The transparent display device of claim 1, further comprising:

the conductive layer is clamped between the protective layer and the water blocking structure and is positioned between the side wall of the miniature light emitting diode and the water blocking structure, wherein the conductive layer comprises a net-shaped structure in a top view.

5. The transparent display of claim 4, wherein the conductive layer is connected to a ground voltage.

6. The transparent display device of claim 1, wherein the protective layer comprises a photoresist or a transparent optical adhesive surrounding a junction between the micro light emitting diode and the circuit substrate.

7. The transparent display of claim 1, wherein the water blocking structure comprises a multilayer structure.

8. The transparent display device of claim 1, wherein the circuit substrate comprises:

a transparent substrate;

a black matrix above the transparent substrate and around the micro light emitting diode;

A bonding pad over the transparent substrate, wherein the micro light emitting diode is bonded to the bonding pad;

a passivation layer overlying the bonding pad and surrounding the junction between the micro light emitting diode and the bonding pad, wherein the passivation layer is formed on the passivation layer and surrounding the micro light emitting diode and the junction, and wherein the water blocking structure extends from the top surface of the passivation layer to the passivation layer along the side surface of the passivation layer, wherein the water blocking structure comprises an oxide layer and a nitride layer overlapping the oxide layer, and the vertical projection shape of the oxide layer on the transparent substrate is substantially equal to the vertical projection shape of the nitride layer on the transparent substrate, and

And the packaging layer is used for covering the water-blocking structure and the protective layer, wherein the packaging layer is filled into the opening of the water-blocking structure and contacts with the protective layer.

9. The transparent display device of any one of claims 1 to 8, wherein the circuit substrate comprises:

a transparent substrate;

a black matrix above the transparent substrate and around the micro light emitting diode;

A bonding pad over the transparent substrate, wherein the micro light emitting diode is bonded to the bonding pad;

A passivation layer covering the pad and surrounding the junction between the micro light emitting diode and the pad, wherein the passivation layer is formed on the passivation layer and surrounding the micro light emitting diode and the junction;

A conductive layer extending from the top surface of the protective layer to the passivation layer along the side surface of the protective layer, and comprising:

a mesh structure overlapping the non-penetrating region;

A shielding structure extending from the mesh structure to the micro LED and having a through hole overlapping the top surface of the micro LED, wherein the water blocking structure is formed on the shielding structure and the through hole of the shielding structure overlaps the opening of the water blocking structure, and

And the packaging layer is used for covering the water-blocking structure and the protective layer, wherein the packaging layer is filled into the opening of the water-blocking structure and the through hole of the shielding structure and is contacted with the protective layer.

10. A tiled display device, comprising:

More than two transparent display devices according to claim 1 are tiled together.