TWI897771B - Integrated chip with calibration function and method for calibrating chip - Google Patents

Abstract

An integrated chip with a calibration function and a method for calibrating a chip are related to the semiconductor field. The chip includes an analog circuit; a memory module, configured to store a target identifier and target parameters for adjusting the analog circuit, where the target identifier is configured to indicate whether the target parameters pass a CP test and a FT test; and a signal controlling module, arranged in a digital circuit of the integrated chip, and configured to: read the target identifier, compare the target identifier with a preset identifier, determine that the target parameters were obtained through the CP test and the FT test and transmit the target parameters to the analog circuit, in a case that the target identifier is consistent with the preset identifier, and determine that the target parameter were not obtained through the CP test and the FT test and transmit and preset parameters to the analog circuit, in a case that the target identifier is inconsistent with the preset identifier. Both the target parameters and the preset parameters are configured to ensure proper operation of the integrated chip. Accordingly, a yield of chips can be improved in a testing stage.

Description

Integrated chip with calibration function and chip calibration method

The present invention relates to the field of semiconductors, and more particularly to an integrated chip with a calibration function and a chip calibration method.

During the production of integrated circuits, process deviations can occur, leading to parameter shifts in parameters such as the power supply voltage and clock frequency. Therefore, the parameters of the integrated circuits need to be adjusted during the CP test (Chip Probing) and FT test (Final Test) stages to ensure that the integrated circuits can operate within accurate and reliable performance parameters.

Typically, parameters that have passed CP and FT tests are stored in the integrated chip's memory. This allows the chip to be loaded from memory into the chip's actual operating circuitry when powered on, ensuring proper and stable operation. However, some technology vendors store parameters randomly in their integrated chip memory during production without undergoing CP and FT tests. In this case, directly importing these untested parameters into the chip creates the risk of the chip's circuitry malfunctioning, reducing the chip's yield rate. Currently, there is no effective solution to this technical problem.

Therefore, how to improve the yield rate of integrated chips is a technical problem that needs to be solved by those skilled in the art.

In view of this, the purpose of the present invention is to provide an integrated chip with a calibration function and a chip calibration method to solve the problem of low yield of integrated chips in the prior art. The specific solution is as follows:

In order to solve the above technical problems, the present invention provides an integrated chip with a calibration function, comprising: an analog circuit; a storage module for storing a target identifier and a target parameter for adjusting the analog circuit of the integrated chip; wherein the target identifier is used to indicate whether the target parameter has passed the CP test and the FT test; a signal control module, arranged in the digital circuit of the integrated chip, for reading the target identifier and comparing it with a preset value. The target parameter is compared with the preset identifier; when the target identifier is consistent with the preset identifier, it is determined that the target parameter has passed the CP test and the FT test, and the target parameter is sent to the analog circuit; or, when the target identifier is inconsistent with the preset identifier, it is determined that the target parameter has failed the CP test and the FT test, and the preset parameter is sent to the analog circuit; both the target parameter and the preset parameter are used to ensure that the integrated chip operates normally.

Preferably, the signal control module includes: a first signal selector, a second signal selector and a signal control submodule; the signal control submodule is used to determine that the target parameter passes the CP test and the FT test when the target identifier is consistent with the preset identifier, send an enable signal to the signal selection port of the first signal selector, and parse the target parameter to obtain the target parsed parameter; wherein the input of the signal control submodule is The input end is connected to the storage module, the output end of the signal control submodule is respectively connected to the signal selection port of the first signal selector, the output end of the first signal selector is connected to the signal selection port of the second signal selector, and the output end of the second signal selector is connected to the analog circuit; the first input end of the second signal selector is used to receive the preset parameter, and the second input end of the second signal selector is used to receive the target analysis parameter.

Preferably, the signal control submodule includes: a control unit for determining that the target parameter has passed the CP test and the FT test when the target identifier is consistent with the default identifier, sending an enable signal to the signal selection port of the first signal selector, and sending the target parameter to the parsing unit; the parsing unit is used to parse the target parameter to obtain the target parsed parameter.

Preferably, the storage module includes: a first storage unit for storing the target identifier; and a second storage unit for storing the target parameter for adjusting the integrated chip.

Preferably, the system further comprises: a software trigger module, disposed in the digital circuit, for transmitting the target parameter that has undergone the CP test and the FT test to the analog circuit.

Preferably, the software trigger module includes: a third signal selector, an OR gate, and a central processing unit, wherein the central processing unit sends an enable signal to the signal selection port of the third signal selector; wherein the signal output end of the third signal selector is connected to the first input end of the OR gate, and the output end of the first signal selector is connected to the signal selection port of the second signal selector through the OR gate.

Preferably, the CPU is controlled by a software application.

Preferably, this target parameter will provide better debugging than the default parameter.

Preferably, the complexity of the preset identifier is inversely correlated with the probability of failure of the integrated chip.

To address the above-mentioned technical issues, the present invention further provides a chip calibration method, wherein the chip has completed CP testing and FT testing. The calibration method includes the following steps, performed in sequence: Step S201: Determine whether the target identifier of the memory in the integrated chip is consistent with the preset identifier; if so, execute step S202; if not, execute step S204; Step S202: Send target parameters to the analog circuit of the integrated chip; Step S203: Operate the integrated chip according to the target parameters; Step S204: Send instructions to the central processing unit via a software application; Step S205: The CPU controls the analog circuit of the integrated chip to operate within the target parameters. Step S206: The integrated chip operates within the target parameters.

Beneficial effect: In the integrated chip with calibration function provided by the present invention, an analog circuit, a storage module and a digital circuit are set in the integrated chip, and a signal control module is set in the digital circuit. Among them, the storage module is used to store the target identifier and the target parameters for adjusting the integrated chip. The target identifier is used to indicate whether the target parameter has passed the CP test and the FT test. When the signal control module determines that the target identifier in the storage module is consistent with the preset identifier, it means that the target parameter in the storage module has passed the CP test and the FT test. At this time, the signal control module will send the target parameter that has passed the CP test and the FT test to the analog circuit for use by the analog circuit. When the signal control module determines that the target identifier in the storage module is inconsistent with the default identifier, it means that the target parameters in the storage module have not passed the CP test and FT test and are randomly stored parameters. At this time, the signal control module will send the default parameters used to trigger the normal operation of the integrated circuit to the analog circuit, thereby ensuring the normal operation of the integrated circuit.

With this setup, both before and after CP and FT tests, ICs can prevent parameters randomly stored in memory from entering the analog circuit. This ensures the normal and stable operation of ICs, further improving IC yield during the testing phase.

Correspondingly, the present invention provides a chip calibration method that also has the above-mentioned beneficial effects.

The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention, combined with the drawings in the embodiments. Obviously, the described embodiments are only a portion of the embodiments of the present invention, and not all of them. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are also within the scope of protection of the present invention.

Please refer to FIG1 , which is a structural diagram of an integrated chip with a calibration function provided by an embodiment of the present invention. The chip includes an analog circuit 11; a storage module 12 for storing a target identifier and a target parameter for adjusting the analog circuit 11 of the integrated chip; wherein the target identifier is used to indicate whether the target parameter has passed the CP test and the FT test; a signal control module 14, which is set in the digital circuit 13 of the integrated chip, is used to read The target identifier is used to determine the target parameter and compare it with the default identifier. When the target identifier is consistent with the default identifier, it is determined that the target parameter has passed the CP test and the FT test, and the target parameter is sent to the analog circuit 11. Alternatively, when the target identifier is inconsistent with the default identifier, it is determined that the target parameter has failed the CP test and the FT test, and the default parameter is sent to the analog circuit 11. Both the target parameter and the default parameter are used to ensure that the integrated chip operates normally.

In this embodiment, an integrated circuit (IC) with a calibration function is provided to reduce the probability of defective ICs during the testing phase. The IC includes an analog circuit 11, a storage module 12, and a digital circuit 13. A signal control module 14 is also provided within the digital circuit 13.

Specifically, the storage module 12 stores a target identifier and target parameters for adjusting the integrated chip. The storage module 12 can be a storage medium such as Eflash (Embedded Flash) or an OTP (One-Time Programmable) chip. The target identifier is used to indicate whether the target parameters have passed the CP test and the FT test. In other words, if the target identifier matches the preset identifier, it indicates that the target parameters stored in the storage module 12 have passed the CP test and the FT test. If the target identifier is inconsistent with the preset identifier, it means that the target parameters stored in the storage module 12 are randomly generated parameters. When these parameters enter the analog circuit 11 of the integrated chip, the normal and stable operation of the integrated chip cannot be ensured.

When the signal control module 14 determines that the target identifier in the storage module 12 matches the preset identifier, it indicates that the target parameters in the storage module 12 have passed the CP test and the FT test. At this point, the signal control module 14 transmits the target parameters that have passed the CP and FT tests to the analog circuit 11. By using the target parameters that have passed the CP and FT tests, the analog circuit 11 can avoid deviations in parameters such as the power supply voltage and clock frequency in the integrated circuit, thereby ensuring the operational performance of the integrated circuit.

When the signal control module 14 determines that the target identifier in the storage module 12 is inconsistent with the preset identifier, it means that the target parameters in the storage module 12 have not passed the CP test and the FT test and are randomly generated parameters. At this time, the preset parameters used to trigger the normal operation of the integrated circuit can be sent to the analog circuit 11, thereby ensuring the normal operation of the integrated circuit.

It should be noted that the target parameters that have passed the CP test and the FT test can ensure that the integrated chip operates in a more stable and excellent state, while the default parameters are some parameters set in advance. These parameters are generally in the middle value. When the integrated chip process deviation is not particularly large, the default parameters can make the integrated chip work normally, but they are not at the optimal operating parameters.

It should also be noted that the integrated chip of the present invention can be a TPIC (Touch Panel Driver Integrated Circuit) chip or any other type of chip. As long as the parameters stored in the control memory of the integrated chip are imported into the analog circuit 11 of the integrated chip for parameter adjustment during operation, the calibration architecture provided by the present invention can be used.

Obviously, under this configuration, the integrated chip can avoid the parameters randomly stored in the memory from being introduced into the analog circuit 11, whether before or after the CP test and FT test. Therefore, this architecture can ensure that the integrated chip can operate normally and stably, thereby further improving the yield rate of the integrated chip during the test stage.

Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, please refer to Figure 2, which shows the structure of another integrated chip with calibration functionality provided by this embodiment of the present invention. The storage module 12 includes a first storage unit for storing a target identifier and a second storage unit for storing target parameters for adjusting the integrated chip.

In this embodiment, in order to make the execution logic of the signal control module 14 clearer and more orderly, the storage module 12 can be divided into a first storage unit and a second storage unit. The first storage unit is used to store the target identifier, and the second storage unit is used to store the target parameters for adjusting the integrated chip.

In a preferred embodiment, the signal control module 14 includes a first signal selector MUX1, a second signal selector MUX2, and a signal control submodule 100. The signal control submodule 100 is configured to determine that the target parameter has passed the CP test and the FT test when the target identifier matches a preset identifier, send an enable signal to the signal strobe port of the first signal selector MUX1, and parse the target parameter to obtain a target parsed parameter, trim_code.

Among them, the input end of the signal control sub-module 100 is connected to the storage module 12, the output end of the signal control sub-module 100 is respectively connected to the signal selection port of the first signal selector MUX1, the output end of the first signal selector MUX1 is connected to the signal selection port of the second signal selector MUX2, and the output end of the second signal selector MUX2 is connected to the analog circuit 11; the first input end of the second signal selector MUX2 is used to receive the default parameter default_code, and the second input end of the second signal selector MUX2 is used to receive the target parsing parameter trim_code.

In this embodiment, the internal structure of the signal control module 14 is specifically described. The signal control module 14 is provided with a first signal selector MUX1, a second signal selector MUX2, and a signal control sub-module 100.

Assume that storage module 12 is an N-bit register, with the names of these N registers being reg0, reg1, reg2, ..., regN-1, regN. Register reg0 is used to store the target identifier, and the other registers, excluding register reg0, are used to store the target parameters. In this case, register reg0 is the first storage unit, and the other registers, excluding register reg0, are the second storage unit.

If the target identifier stored in the first storage unit is defined as a switch that turns on whether to import the target parameters into the analog circuit 11, and the default identifier is set to 16'h5aa5, then when the target identifier stored in the first storage unit is equal to the default identifier 16'h5aa5, it indicates that the target parameters stored in the second storage unit have passed the CP test and the FT test. At this time, the target parameters stored in the second storage unit can be sent to the analog circuit 11. When the target identifier stored in the first storage unit is not equal to the default identifier 16’h5aa5, it means that the target parameter stored in the second storage unit has not passed the CP test and the FT test. At this time, the target parameter stored in the second storage unit cannot be sent to the analog circuit 11, and only the default parameter default_code can be sent to the analog circuit 11.

Specifically, when the signal control submodule 100 detects that the target identifier stored in the first storage unit in the storage module 12 is consistent with the preset identifier 16'h5aa5, it indicates that the target parameter stored in the first storage unit has passed the CP test and the FT test. At this time, the signal control submodule 100 sends an enable signal to the signal strobe port of the first signal selector MUX1, thereby causing the output signal trimcode_enable_hw of the first signal selector MUX1 to be high. When the output signal trimcode_enable_hw of the first signal selector MUX1 is high, it is equivalent to the first signal selector MUX1 sending an enable signal to the signal strobe port of the second signal selector MUX2. At this time, the second signal selector MUX2 will receive the target parsing parameter trim_code output by the signal control submodule 100, and send the target parsing parameter trim_code to the analog circuit 11 of the integrated chip, so that the integrated chip can use the target parameters that have passed the CP test and the FT test to better tune the parameters of the integrated chip.

When signal control submodule 100 detects that the target identifier stored in the first storage unit of storage module 12 is inconsistent with the default identifier 16'h5aa5, it indicates that the target parameters stored in the first storage unit have failed the CP test and the FT test and are still random parameters. In this case, the second signal selector MUX2 defaults to receiving the default parameter default_code and sends it to the analog circuit 11 of the integrated circuit, thereby ensuring normal operation of the integrated circuit.

As a preferred implementation, the signal control submodule 100 includes a control unit 101, which is used to determine whether the target parameter has passed the CP test and the FT test when the target identifier is consistent with the default identifier, send an enable signal to the signal selection port of the first signal selector MUX1, and send the target parameter to the parsing unit 102; the parsing unit 102 is used to parse the target parameter to obtain the target parsing parameter trim_code.

In this embodiment, a control unit 101 and a parsing unit 102 may also be provided in the signal control submodule 100. When the control unit 101 detects that the target identifier stored in the storage module 12 is consistent with a preset identifier, it indicates that the target parameter stored in the storage module 12 has passed the CP test and the FT test. At this point, the control unit 101 may send an enable signal to the signal select port of the first signal selector MUX1 and send the target parameter that has passed the CP test and the FT test to the parsing unit 102. When the parsing unit 102 receives the target parameter sent by the control unit 101, it parses the target parameter to obtain the target parsing parameter trim_code.

Obviously, through the technical solution provided by this embodiment, the target parameters that have passed the CP test and the FT test can be quickly introduced into the analog circuit 11 of the integrated circuit through hardware methods.

As a preferred embodiment, the calibration device further includes a software trigger module 15, which is disposed in the digital circuit 13 and is used to send the target parameters that have passed the CP test and the FT test to the analog circuit 11.

In practical applications, in addition to using a hardware-based signal control module 14 to input target parameters after CP and FT tests into the analog circuit 11 of the integrated chip, these parameters can also be input into the analog circuit 11 of the integrated chip through software. Specifically, a software trigger module 15 can be provided within the digital circuit 13 of the integrated chip to transmit the target parameters after CP and FT tests to the analog circuit 11 of the integrated chip.

Please refer to Figure 3, which shows the structure of another integrated circuit with calibration function provided by an embodiment of the present invention. As a preferred embodiment, the software trigger module 15 includes a third signal selector MUX3, an OR gate, and a central processing unit 103. The central processing unit 103 sends an enable signal to the signal strobe port of the third signal selector MUX3. The signal output terminal of the third signal selector MUX3 is connected to the first input terminal of the OR gate, and the output terminal of the first signal selector MUX1 is connected to the signal strobe port of the second signal selector MUX2 via the OR gate.

In this embodiment, the software trigger module 15 is specifically described. The software trigger module 15 includes a central processing unit (CPU) 103, a third signal selector MUX3, and an OR gate.

In actual applications, if the target parameters in the storage module 12 have passed the CP test and the FT test, but for some reason these parameters cannot be introduced into the analog circuit 11 of the integrated chip through the hardware signal control module 14, then the target parameters that have passed the CP test and the FT test can be introduced into the analog circuit 11 of the integrated chip through the software trigger module 15.

Specifically, when the target identifier matches the default identifier, the CPU 103 sends an enable signal to the signal selector port of the third signal selector MUX3, causing the output signal trimcode_enable_sw of the third signal selector MUX3 to be high. In this case, the OR gate outputs a high signal, and the second signal selector MUX2 then transmits the target parameters that have passed the CP and FT tests to the analog circuit 11. This allows the integrated circuit to use these target parameters to perform parameter adjustments, thereby ensuring stable and reliable operation of the integrated circuit.

Obviously, through the technical solution provided by this embodiment, the target parameters that pass the CP test and the FT test can be sent to the analog circuit 11 of the integrated chip through the software control method.

In actual applications, the CPU 103 can be controlled by a software application. This software application can be an APP (Application) or a boot application. In this configuration, when the software application is running, the CPU 103 transmits target parameters that have passed the CP and FT tests to the analog circuit 11 of the integrated circuit.

Obviously, the technical solution provided by this embodiment can further improve the convenience of sending adjustment parameters to the analog circuit 11 of the integrated chip.

Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the integrated chip is specifically a TP IC. TP ICs are very common in smartphones, tablets, touch-screen computers, and other touch-sensitive devices. TP ICs are mixed-signal SOC (System on a Chip) chips. Their internal analog circuits primarily control each sensor element on the touchscreen and also provide power, clock, and other signals to the digital circuits, ensuring their normal and stable operation.

Due to process variations during the production of TP IC chips, these variations can cause parameter shifts in the chip's power supply voltage, clock frequency, and other parameters, which in turn affect the chip's operational performance. The TP IC provided by this invention prevents randomly stored parameters from being introduced into the chip's actual operating circuitry, impacting its stable operation.

Furthermore, it should be noted that, in the present invention, the tuning effect of target parameters is superior to that of default parameters. Specifically, default parameters are pre-set parameters that are generally mid-range. If the integrated chip process variation is not particularly large, the default parameters can enable the integrated chip to operate normally, but not at optimal operating parameters. However, once the target parameters pass the CP test and the FT test, they are introduced into the analog circuit 11 of the integrated chip to ensure that the integrated chip operates at its optimal operating state.

Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the complexity of the default identifier is inversely correlated with the probability of integrated chip failure. That is, the higher the complexity of the default identifier, the lower the probability of integrated chip failure. Conversely, the lower the complexity of the default identifier, the higher the probability of integrated chip failure. It is not surprising that if the default identifier is more complex, the target identifier randomly stored in the memory of the integrated chip will almost never match the default identifier. This further reduces the probability of integrated chips being mistakenly judged as good.

Please refer to FIG4, which is a flow chart of an integrated chip with a calibration function performing a calibration function according to an embodiment of the present invention. The integrated chip has passed the CP test and the FT test. This calibration method includes the following steps: Step S201: Determine whether the target identifier of the memory in the integrated chip matches the preset identifier; if so, execute step S202; if not, execute step S204; Step S202: Send target parameters to the analog circuit of the integrated chip; Step S203: The integrated chip operates at the target parameters; Step S204: Send instructions to the central processing unit (CPU) via a software application; Step S205: The CPU controls the analog circuit of the integrated chip to operate at the target parameters; Step S206: The integrated chip operates at the target parameters.

After an integrated chip passes the CP and FT tests, if the target identifier in the memory does not match the preset identifier, this indicates that due to some abnormal reason, the target parameters that have passed the CP and FT tests cannot be sent to the analog circuit 11 of the integrated chip through the hardware signal control module 14. In this case, the parameters that have passed the CP and FT tests can be manually sent to the analog circuit 11 of the integrated chip through software triggering, allowing the integrated chip to be adjusted to the target parameters that passed the CP and FT tests, thereby ensuring stable and reliable operation of the integrated chip.

Furthermore, in existing technologies, to prevent parameters that have not undergone CP and FT testing from being directly introduced into the analog circuit 11 of the integrated chip, potentially causing the integrated chip to malfunction, particularly complex circuit designs are sometimes employed to avoid the aforementioned issues. However, the more complex the circuit structure, the more likely it is that omissions will occur during design. Even with this approach, it is still impossible to completely prevent random parameters from being introduced into the analog circuit 11 of the integrated chip, and thus, the stable and reliable operation of the integrated chip cannot be guaranteed.

The calibration architecture provided by the present invention can avoid importing parameters randomly stored in memory into the analog circuit 11 of the integrated chip using a relatively simple circuit structure. Furthermore, the calibration architecture provided by the present invention can import target parameters that have undergone CP and FT tests into the analog circuit 11 of the integrated chip using hardware methods, or import preset parameters that have undergone CP and FT tests into the analog circuit 11 of the integrated chip using software methods. This can further improve the stability and reliability of the integrated chip during operation.

Obviously, the technical solution provided by this embodiment can reduce the probability of integrated chips being defective due to random parameters being introduced during the test phase, and can also improve the stability and reliability of the integrated chips during operation.

The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and reference can be made to the same or similar parts between the various embodiments.

Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprise," "include," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of more limitations, an element defined by the phrase "comprises a..." does not preclude the presence of other identical elements in the process, method, article, or apparatus that includes such element.

The above describes in detail an integrated chip with a calibration function and a chip calibration method provided by the present invention. Specific examples are used herein to illustrate the principles and implementations of the present invention. The description of the above embodiments is intended only to facilitate understanding of the method and core concepts of the present invention. Furthermore, those skilled in the art will appreciate that the specific implementations and scope of application may vary based on the principles of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

11: Analog circuit 12: Storage module 13: Digital circuit 14: Signal control module 15: Software trigger module 100: Signal control submodule 101: Control unit 102: Analysis unit 103: Central processing unit MUX1: First signal selector MUX2: Second signal selector MUX3: Third signal selector OR: OR gate trimcode_enable_hw: Output signal trimcode_enable_sw: Output signal trim_code: Target analysis parameter default_code: Default parameter 16'h5aa5: Default identifier S201-S206: Steps

To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly describes the figures required for use in the embodiments or descriptions of the prior art. It should be understood that the figures described below represent only embodiments of the present invention. Those skilled in the art can derive other figures from the provided figures without undue effort. Figure 1 is a structural diagram of an integrated chip with a calibration function provided in an embodiment of the present invention. Figure 2 is a structural diagram of another integrated chip with a calibration function provided in an embodiment of the present invention. Figure 3 is a structural diagram of yet another integrated chip with a calibration function provided in an embodiment of the present invention. Figure 4 is a flow chart of a calibration function performed by an integrated chip with a calibration function according to an embodiment of the present invention.

11: Analog Circuit

12: Storage Module

13: Digital Circuits

14: Signal control module

Claims (10)

An integrated chip with a calibration function comprises: an analog circuit; a storage module for storing a target identifier and a target parameter for adjusting the analog circuit of an integrated chip; wherein the target identifier is used to indicate whether the target parameter passes a CP test and a FT test; and A signal control module, disposed within a digital circuit of the integrated chip, is configured to read the target identifier and compare it with a preset identifier. When the target identifier matches the preset identifier, the target parameter is determined to have passed the CP test and the FT test, and the target parameter is sent to the analog circuit. Alternatively, when the target identifier does not match the preset identifier, the target parameter is determined to have failed the CP test and the FT test, and a preset parameter is sent to the analog circuit. Both the target parameter and the preset parameter are used to ensure the normal operation of the integrated chip. The integrated chip with a calibration function as described in claim 1, wherein the signal control module comprises: a first signal selector, a second signal selector, and a signal control sub-module, wherein the signal control sub-module is configured to determine that the target parameter passes the CP test and the FT test when the target identifier matches the preset identifier, send an enable signal to the signal strobe port of the first signal selector, and analyze the target parameter to obtain a target analyzed parameter; The input end of the signal control submodule is connected to the storage module, the output end of the signal control submodule is connected to the signal selection port of the first signal selector, the output end of the first signal selector is connected to the signal selection port of the second signal selector, and the output end of the second signal selector is connected to the analog circuit; the first input end of the second signal selector is used to receive the preset parameter, and the second input end of the second signal selector is used to receive the target analysis parameter. The integrated chip with a calibration function as described in claim 2, wherein the signal control submodule comprises: a control unit for determining that the target parameter has passed the CP test and the FT test when the target identifier matches the preset identifier, sending an enable signal to the signal strobe port of the first signal selector, and sending the target parameter to a parsing unit; and the parsing unit for parsing the target parameter to obtain the target parsed parameter. The integrated chip with calibration function as described in claim 2, wherein the storage module comprises: a first storage unit for storing the target identifier; and a second storage unit for storing the target parameter for adjusting the integrated chip. The integrated chip with calibration function as described in claim 2 further includes: A software trigger module disposed within the digital circuit, configured to transmit the target parameter, which has undergone the CP test and the FT test, to the analog circuit. The integrated chip with a calibration function as described in claim 5, wherein the software trigger module includes: a third signal selector, an OR gate, and a central processing unit, the central processing unit sending an enable signal to a signal strobe port of the third signal selector; The signal output terminal of the third signal selector is connected to the first input terminal of the OR gate, and the output terminal of the first signal selector is connected to the signal strobe port of the second signal selector through the OR gate. The integrated chip with calibration function as described in claim 6, wherein the central processing unit is controlled by a software application. The integrated chip with calibration function as claimed in claim 1, wherein the debugging effect of the target parameter is better than the default parameter. An integrated chip with a calibration function as claimed in any one of claims 1 to 8, wherein the complexity of the preset identifier is inversely correlated with the probability of failure of the integrated chip. A chip calibration method is provided, wherein the chip has completed a CP test and a FT test. The calibration method includes the following steps, performed in sequence: Step S201: Determining whether a target identifier of a memory in an integrated chip is consistent with a preset identifier; if so, executing step S202; if not, executing step S204; Step S202: Sending a target parameter to an analog circuit in the integrated chip; Step S203: Operating the integrated chip at the target parameter; Step S204: Sending instructions to a central processing unit via a software application; Step S205: The CPU controls the analog circuit of the integrated chip to operate at the target parameters; and Step S206: The integrated chip operates at the target parameters.