TWI863099B - Semiconductor device and method for forming the same - Google Patents

Abstract

Embodiments provide a semiconductor device and a method for forming the same. The semiconductor device includes a silicon carbide substrate, an epitaxial layer, at least two well regions, at least two source region, a split-gate structure and conductive feature. The epitaxial layer is disposed on the silicon carbide substrate. The well regions are located in the epitaxial layer. The source regions are located on the well regions. The split-gate structure is disposed on the epitaxial layer. The split-gate structure includes a first gate, a second gate and a gate dielectric layer. The first gate and the second gate partially overlap the source regions. The gate dielectric layer surrounds the first gate and the second gate. The conductive feature is disposed above the epitaxial layer between the well regions and extends to between the first gate and the second gate. A lower surface of the conductive feature between the first gate and the second gate is located on between the top surfaces of the first gate and the second gate and the top surface of the epitaxial layer.

Description

Semiconductor device and method of forming the same

The present invention relates to a semiconductor device and a method for forming the same, and in particular to a power transistor device and a method for forming the same.

High voltage component technology is applied to high voltage and high power integrated circuits. In order to achieve high withstand voltage and high current, the flow of driving current in traditional power transistors has developed from the planar direction to the vertical direction. Currently, vertical bi-diffused metal oxide semiconductor field effect transistors (VDMOSFET) have been developed. However, in high-frequency power transistor applications, the electrical parameters of vertical bi-diffused metal oxide semiconductor field effect transistors such as on-resistance (R _on ), breakdown voltage (BV), gate-drain capacitance (C _gd ) still need to be further improved.

Therefore, it is necessary to seek a vertical double diffused metal oxide semiconductor field effect transistor semiconductor device and its formation method, which can solve or improve the above-mentioned problems.

Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a silicon carbide substrate, an epitaxial layer, at least two well regions, at least two source regions, a separated gate structure, and a conductive component. The silicon carbide substrate has a first conductivity type. The epitaxial layer is disposed on a top surface of the silicon carbide substrate, wherein the epitaxial layer has a first conductivity type. At least two well regions are located in the epitaxial layer, the well regions are separated from each other along a first direction and have a second conductivity type. At least two source regions are respectively located on corresponding well regions and close to the top surface of the epitaxial layer, wherein the source regions have a first conductivity type. The separated gate structure is arranged on the top surface of the epitaxial layer, wherein the separated gate structure includes a first gate and a second gate separated from each other along a first direction and a gate dielectric layer. The first gate and the second gate overlap with the corresponding source region respectively. The gate dielectric layer surrounds the first gate and the second gate. The conductive component is arranged above a portion of the epitaxial layer between the well regions and extends between the first gate and the second gate along a second direction, wherein the lower surface of the portion of the conductive component between the first gate and the second gate is located between multiple top surfaces of the first gate and the second gate and the top surface of the epitaxial layer.

Some embodiments of the present invention provide a method for forming a semiconductor device. The method for forming a semiconductor device includes providing a silicon carbide substrate, the silicon carbide substrate having a first conductivity type; growing an epitaxial layer on the top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; forming at least two well regions in the epitaxial layer, wherein the well regions are separated from each other along a first direction and have a second conductivity type; forming at least two source regions on the corresponding well regions and close to the top surface of the epitaxial layer, wherein the source regions have the first conductivity type; after forming the well regions and the source regions, forming a first gate dielectric material layer, a second gate dielectric material layer, and a gate dielectric material layer located on the first gate dielectric material layer on the top surface of the epitaxial layer. A first gate on a layer and a second gate on a second gate dielectric material layer, wherein the first gate and the second gate overlap with corresponding source regions respectively; a third dielectric material layer is formed on the first gate and the second gate, and the upper surface of a portion of the third dielectric material layer between the first gate and the second gate is located between the multiple top surfaces of the first gate and the second gate and the top surface of the epitaxial layer; a conductive component is formed on the third dielectric material layer, wherein the conductive component contacts the upper surface of the third dielectric material layer; and a source contact is formed on the third dielectric material layer, wherein the source contact is electrically connected to the conductive component.

200: Silicon carbide substrate

200T, 204T, 214-1T, 214-2T, 220P-1T, 220P-2T, 250T: Top

200B,320P1B,320P2B,324B,325B,326B: bottom surface

204: Epitaxial layer

206: Well area

208: Source region

210: Wiring mixed area

212-1,212-2: Gate dielectric material layer

214-1,214-2: Gate

214-1S1,214-1S2,214-2S1,214-2S2,230PS1,230PS2: Side

218,218P-1,218P-2,218PA-1,218PA-2,218PB-1,218PB-2,224,224P,318,318R,318P,318E,322,322E: Dielectric material layer

220: Conductive layer

220P-1,220P-2,220PA-1,220PA-2,220PB-1,220PB-2: Conductive pattern

220P-1B, 220P-2B, 220PA-1B, 220PA-2B, 220PB-1B, 220PB-2B, 230PB: bottom surface

228,328: Gate dielectric layer

230: Source contact

230P,252,252A,252B: Conductive components

240: Drain contact

250: Split gate structure

320,320P1,320P2,320E: Etch stop layer

324,325,326: Open mouth

500A, 500B, 500C, 500D: semiconductor devices

D1,D2,D2A,D2B,D2C,D3:Distance

W1: First width

W2: Second width

T1,T2,T3,T4,T5,T6:Thickness

When read in conjunction with the accompanying drawings, the concepts of the embodiments of the present invention can be better understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

Figure 1 is a schematic top view of a semiconductor device of some embodiments of the present invention.

Figure 2 is a schematic top view of a semiconductor device of some embodiments of the present invention.

Figure 3 is a schematic top view of a semiconductor device of some embodiments of the present invention.

Figure 4 is a schematic top view of a semiconductor device of some embodiments of the present invention.

Figures 5-8A, 9-10 are cross-sectional schematic diagrams of the intermediate stages of forming the semiconductor device of some embodiments of the present invention shown in Figure 1.

FIG. 8B is a schematic cross-sectional view of an intermediate stage of forming a semiconductor device of some embodiments of the present invention shown in FIG. 2.

FIG. 8C is a schematic cross-sectional view of an intermediate stage in forming a semiconductor device of some embodiments of the present invention shown in FIG. 3.

Figures 11-18 are schematic cross-sectional views of intermediate stages of forming the semiconductor device of some embodiments of the present invention shown in Figure 4.

The present disclosure is described more fully below with reference to the drawings of the embodiments of the present invention. However, the present disclosure may be implemented in various different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numbers in the drawings represent the same or similar elements.

Various different embodiments or examples are provided below for implementing different elements of the provided semiconductor structure. If the description mentions that a first component is formed on a second component, it may include an embodiment in which the first and second components are directly in contact, and it may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present invention may use repeated component symbols in many examples. These repetitions are only for the purpose of simplification and clarity, and do not represent a specific relationship between the various embodiments and/or configurations discussed.

FIG. 1 is a cross-sectional schematic diagram of a semiconductor device 500A of some embodiments of the present invention. In some embodiments, the semiconductor device 500A includes a power metal oxide semiconductor field effect transistor (power MOSFET), such as a vertical dual diffused metal oxide semiconductor field effect transistor (VDMOSFET) with a split-gate structure. As shown in FIG. 1, the semiconductor device 500A includes a silicon carbide (SiC) substrate 200, an epitaxial layer 204, at least two well regions 206, at least two source regions 208, a split gate structure 250, and a conductive component 252.

As shown in FIG. 1 , the silicon carbide substrate 200 has a top surface 200T and a bottom surface 200B. In some embodiments, the conductivity type of the silicon carbide substrate 200 may be P-type or N-type according to design requirements. In this embodiment, the silicon carbide substrate 200 may be doped to have a first conductivity type, such as N-type.

The epitaxial layer 204 is disposed on the top surface 200T of the silicon carbide substrate 200. In some embodiments, the epitaxial layer 204 may be doped to have a first conductivity type. For example, when the silicon carbide substrate 200 is an N-type silicon carbide substrate 200, the epitaxial layer 204 is an N-type epitaxial layer 204. Moreover, the doping concentration of the epitaxial layer 204 is less than the doping concentration of the silicon carbide substrate 200. For example, when the silicon carbide substrate 200 is an N-type heavily doped (N+) silicon carbide substrate 200, the epitaxial layer 204 is an N-type lightly doped (N-) epitaxial layer 204 to serve as a drift region of the final semiconductor device 500A. In some embodiments, the epitaxial layer 204 includes silicon carbide.

The two well regions 206 of the semiconductor device 500A are located in the epitaxial layer 204 and close to the top surface 204T of the epitaxial layer 204. As shown in FIG. 1, the well regions 206 are separated from each other along the direction 100 (substantially parallel to the top surface 200T of the silicon carbide substrate 200, which can also be regarded as a lateral direction). In some embodiments, the well region 206 can be doped with a dopant to have a second conductivity type opposite to the first conductivity type. For example, when the silicon carbide substrate 200 is an N-type silicon carbide substrate 200, the well region 206 is a P-type well region 206.

The two source regions 208 of the semiconductor device 500A are respectively located on the corresponding well regions 210 and close to the top surface 204T of the epitaxial layer 204. As shown in FIG. 1, the source regions 208 are respectively surrounded by the corresponding well regions 210. In some embodiments, the source regions 208 may be doped to have a first conductivity type. For example, when the silicon carbide substrate 200 is an N-type silicon carbide substrate 200, the source region 208 is an N-type source region 208. In addition, the doping concentration of the source region 208 is greater than the doping concentration of the epitaxial layer 204. For example, when the epitaxial layer 204 is an N-type lightly doped (N-) epitaxial layer 204, the source region 208 is an N-type heavily doped (N+) source region 208.

The semiconductor device 500A further includes at least two wiring doping regions 210. The wiring doping regions 210 are respectively located on the corresponding well regions 210 and close to the top surface 204T of the epitaxial layer 204. As shown in FIG. 1, the wiring doping regions 210 are adjacent to the corresponding source regions 208 along the direction 100. In some embodiments, the wiring doping regions 210 can be doped with a dopant to have a second conductivity type. For example, when the silicon carbide substrate 200 is an N-type silicon carbide substrate 200, the wiring doping regions 210 are P-type wiring doping regions 210. Furthermore, the doping concentration of the wiring doping region 210 is greater than the doping concentration of the well region 206. For example, when the well region 206 is a P-type well region 206, the wiring doping region 210 is a P-type heavily doped (P+) wiring doping region 210 to serve as the wiring doping region 210 of the well region 206. In some embodiments, the source region 208 is electrically connected to the source contact 230 (to be described below) together with the adjacent wiring doping region 210.

The separated gate structure 250 is disposed on the top surface 200T of the epitaxial layer 204. The separated gate structure 250 extends from the portion of the epitaxial layer 204 between the two well regions 206 along the direction 100 to cover the portions of the well regions 206 and the portions of the source regions 208 on both sides thereof. In some embodiments, the separated gate structure 250 includes gates 214-1, 214-2 and a gate dielectric layer 228. As shown in FIG. 1 , the gates 214-1 and 214-2 are both planar gates, and the gates 214-1 and 214-2 are separated from each other along the direction 100 and overlap with the corresponding portions of the source regions 208, respectively. The gate dielectric layer 228 surrounds the top surface 214-1T, the bottom surface (not shown) and the opposite side surfaces 214-1S1 and 214-1S2 of the gate 214-1. In addition, the gate dielectric layer 228 surrounds the top surface 214-2T, the bottom surface (not shown) and the opposite side surfaces 214-2S1 and 214-2S2 of the gate 214-2. In some embodiments, the material of the gates 214-1 and 214-2 includes polysilicon. In some embodiments, the gate dielectric layer 228 includes a composite layer structure, the material of which includes silicon oxide, silicon nitride, silicon oxynitride, phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or a combination thereof.

The conductive component 252 is disposed on a portion of the epitaxial layer 204 between the two well regions 206 and above the gates 214-1 and 214-2, and extends between the gates 214-1 and 214-2 along the direction 110 (substantially perpendicular to the top surface 200T of the silicon carbide substrate 200 and substantially perpendicular to the direction 100, which can also be regarded as a longitudinal direction). In addition, the conductive component 252 is separated from the gates 214-1 and 214-2 by the gate dielectric layer 228. In some embodiments, the conductive component 252 includes conductive patterns 220P-1 and 220P-2 embedded in the gate dielectric layer 228 and separated from each other along the direction 100. In detail, the conductive pattern 220P-1 extends along the direction 100 to cover the top surface 214-1T of the gate 214-1, and extends along the direction 110 to partially cover the side surface 214-1S1 of the gate 214-1. The conductive pattern 220P-2 extends along the direction 100 to cover the top surface 214-2T of the gate 214-2, and extends along the direction 110 to partially cover the side surface 214-2S1 of the gate 214-2. The side surface 214-1S1 of the gate 214-1 and the side surface 214-2S1 of the gate 214-2 are close to each other so that parts of the conductive patterns 220P-1 and 220P-2 are located between the gates 214-1 and 214-2 along the direction 100. In addition, the conductive patterns 220P-1 and 220P-2 may overlap with the corresponding source regions 208, respectively. In some embodiments, the conductive patterns 220P-1 and 220P-2 include the same material as the gates 214-1 and 214-2, such as polysilicon.

As shown in FIG. 1 , in some embodiments, the conductive patterns 220P-1 and 220P-2 of the conductive component 252 have lower surfaces 220P-1B and 220P-2B and upper surfaces opposite to the lower surfaces 220P-1B and 220P-2B and away from the top surface 204T of the epitaxial layer 204. Furthermore, the upper surfaces of the conductive patterns 220P-1 and 220P-2 are completely located above the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2. In some embodiments, the bottom surfaces 220P-1B and 220P-2B of the partial conductive patterns 220P-1 and 220P-2 between the gates 214-1 and 214-2 are located between the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204. In other words, there is a distance D1 between the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204, and there is a distance D2 between the bottom surfaces 220P-1B and 220P-2B of the conductive patterns 220P-1 and 220P-2 and the top surface 204T of the epitaxial layer 204, and the distance D1 is greater than or equal to the distance D2.

In some embodiments, the conductive patterns 220P-1 and 220P-2 on the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 have a thickness T1 in the direction 110, and a portion of the gate dielectric layer 228 between the conductive pattern 220P-1 and the gate 214-1 and between the conductive pattern 220P-2 and the gate 214-2 along the direction 100 has a thickness T2 in the direction 100. In addition, the gates 214-1 and 214-2 are separated by a distance D3 in the direction 100. In some embodiments, the thickness T1 is less than or equal to the difference between one-half of the distance D3 and the thickness T2. If the thickness T1 is greater than the difference between half of the distance D3 and the thickness T2, the conductive patterns 220P-1 and 220P-2 will be connected to each other along the direction 100, and a larger depletion region will be formed in the current path near the surface of the gates 214-1 and 214-2, causing the on-resistance to increase, affecting the electrical properties of the semiconductor device 500A.

As shown in FIG. 1 , the semiconductor device 500A further includes a source contact 230. The source contact 230 is disposed on the top surface 250T of the separation gate structure 250 and the conductive component 252, and extends to cover and contact the source region 208 and the wiring doping region 210. Furthermore, the source contact 230 electrically connects the source region 208, the wiring doping region 210, and the conductive component 252. In some embodiments, the source contact 230 includes a conductive material such as metal.

As shown in FIG. 1 , the semiconductor device 500A further includes a drain contact 240. The drain contact 240 is disposed on the bottom surface 200B of the silicon carbide substrate 200. The drain contact 240 contacts the bottom surface 200B of the silicon carbide substrate 200 and is electrically connected to the silicon carbide substrate 200 as the drain region of the semiconductor device 500A. In some embodiments, the drain contact 240 includes a conductive material such as metal.

FIG. 2 is a schematic top view of a semiconductor device 500B according to some embodiments of the present invention, wherein the same or similar element symbols as those in FIG. 1 represent the same or similar elements. As shown in FIG. 2, the difference between the semiconductor device 500B and the semiconductor device 500A is that the semiconductor device 500B includes a conductive component 252A. The conductive component 252A includes conductive patterns 220PA-1 and 220PA-2. Specifically, the conductive pattern 220PA-1 extends along the direction 100 to completely cover the top surface 214-1T of the gate 214-1, and extends along the direction 110 to partially cover the opposite side surfaces 214-1S1 and 214-1S2 of the gate 214-1. The conductive pattern 220PA-2 extends along the direction 100 to completely cover the top surface 214-2T of the gate 214-2, and extends along the direction 110 to partially cover the two opposite side surfaces 214-2S1 and 214-2S2 of the gate 214-1. In addition, the portion of the conductive pattern 220PA-1 covering the side surface 214-1S2 of the gate 214-1 and the portion of the conductive pattern 220PA-2 covering the side surface 214-2S2 of the gate 214-2 are located directly above the corresponding source region 208. As shown in FIG. 2 , in some embodiments, the conductive patterns 220PA-1 and 220PA-2 of the conductive component 252A have lower surfaces 220PA-1B and 220PA-2B and upper surfaces opposite to the lower surfaces 220PA-1B and 220PA-2B and away from the top surface 204T of the epitaxial layer 204. Furthermore, the upper surfaces of the conductive patterns 220PA-1 and 220PA-2 are completely located above the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2. In some embodiments, the distance D1 between the top surfaces 214-1T, 214-2T of the gates 214-1, 214-2 and the top surface 204T of the epitaxial layer 204 is greater than or equal to the distance D2A between the bottom surfaces 220PA-1B, 220PA-2B of the conductive patterns 220PA-1, 220PA-2 between the gates 214-1, 214-2 and the top surface 204T of the epitaxial layer 204.

FIG. 3 is a schematic top view of a semiconductor device 500C according to some embodiments of the present invention, wherein the same or similar element symbols as those in FIGS. 1 and 2 represent the same or similar elements. As shown in FIG. 3 , the difference between the semiconductor device 500C and the semiconductor device 500A is that the semiconductor device 500C includes a conductive component 252B. The conductive component 252B includes conductive patterns 220PB-1 and 220PB-2. Specifically, the conductive pattern 220PB-1 covers a portion of the top surface 214-1T of the gate 214-1, so that a portion of the gate 214-1 is exposed from the conductive pattern 220PB-1. The conductive pattern 220PB-2 covers a portion of the top surface 214-2T of the gate 214-2, so that a portion of the gate 214-2 is exposed from the conductive pattern 220PB-2. In some embodiments, the conductive patterns 220PB-1 and 220PB-2 may not overlap with the corresponding source region 208. As shown in FIG. 3, the gates 214-1 and 214-2 have a width W1 along the direction 100, and the portions of the gates 214-1 and 214-2 not covered by the conductive patterns 220PB-1 and 220PB-2 have a width W2 along the direction 100. In some embodiments, the width W2 is less than or equal to one-half of the width W1. If the width W2 is greater than half of the width W1, the conductive component 252B inserted between the gates 214-1 and 214-2 of the separated gate structure 250 may be reduced due to process errors, so that the gate-drain capacitance ( _Cgd,L ) in the lateral direction (along the direction 100) cannot be significantly reduced. As shown in FIG. 3, in some embodiments, the conductive patterns 220PB-1 and 220PB-2 of the conductive component 252B have lower surfaces 220PB-1B and 220PB-2B and upper surfaces opposite to the lower surfaces 220PB-1B and 220PB-2B and away from the top surface 204T of the epitaxial layer 204. Furthermore, the upper surfaces of the conductive patterns 220PB-1 and 220PB-2 are completely located above the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2. In some embodiments, the distance D1 between the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204 is greater than or equal to the distance D2B between the lower surfaces 220PB-1B and 220PB-2B of the conductive patterns 220PB-1 and 220PB-2 located between the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204.

In some embodiments, the conductive components 252, 252A, 252B of the semiconductor devices 500A, 500B, 500C are embedded in the gate dielectric layer 228 of the separated gate structure 250 and inserted between the gates 214-1 and 214-2 of the separated gate structure 250 along the direction 100, so that the bottom surface of the conductive component 252 located between the gates 214-1 and 214-2 is located between the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204. The conductive member 252 is electrically connected to the source contact 230, which can reduce the lateral (along the direction 100) gate-drain capacitance (C _gd,L ) without increasing the device size, thereby further reducing the overall gate-drain capacitance (C _gd ) and the feedback capacitance (C _rss =C _gd ) and maintaining substantially the same split gate on-resistance (R _on,sp ). Furthermore, since the conductive components 252, 252A, 252B are similar to field plate structures, the electric field distribution of the gate dielectric layer 228 near the inner edges of the gates 214-1, 214-2 (side surfaces 214-1S1, 214-2S1) can be more uniform, thereby improving the reliability of the gate dielectric layer 228. In addition, the semiconductor devices 500A, 500B, 500C are power metal oxide semiconductor field effect transistors formed on a silicon carbide substrate, which have the advantages of fast switching and high resistance voltage, and are therefore suitable for high frequency and high power applications.

FIG. 4 is a schematic top view of a semiconductor device 500D of some embodiments of the present invention, in which the same or similar element symbols as those in FIGS. 1 to 3 represent the same or similar elements. As shown in FIG. 4, the difference between the semiconductor device 500D and the semiconductor device 500A is that the semiconductor device 500D includes etch stop layers 320P1, 320P2 and a conductive component 230P. The etch stop layers 320P1, 320P2 are disposed in the gate dielectric layer 228 and are located above the gates 214-1, 214-2, respectively. In some embodiments, the etch stop layers 320P1, 320P2 are planar layers extending along the direction 100. That is, the distance D4 between the bottom surfaces 320P1B and 320P2B of the etch stop layers 320P1 and 320P2 and the top surface 204T of the epitaxial layer 204 is uniform. In some embodiments, the etch stop layers 320P1 and 320P2 have different materials and etching selectivity from the gate dielectric layer 228 to serve as etch stop layers in the selective etching process for removing a portion of the gate dielectric layer 228 between the gates 214-1 and 214-2. For example, when the gate dielectric layer 228 is silicon oxide, the etch stop layers 320P1 and 320P2 can be silicon nitride.

As shown in FIG. 4 , a conductive component 230P disposed above a portion of the epitaxial layer 204 between the well regions 210 and extending between the gates 214-1 and 214-2 along the direction 110 is a portion of the source contact 230. Opposite side surfaces 230PS1 and 230PS2 of the conductive component 230P contact the etch stop layers 320P1 and 320P2, respectively. As shown in FIG. 4 , in some embodiments, the conductive component 230P has a bottom surface 230PB and an upper surface opposite to the bottom surface 230PB and away from the top surface 204T of the epitaxial layer 204. Furthermore, the upper surface of the conductive pattern 230P is completely located above the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2. In some embodiments, the lower surface 230PB of the conductive component 230P is located between the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204. In other words, the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 are at a distance D1 from the top surface 204T of the epitaxial layer 204, and the bottom surface 230PB of the conductive component 230P is at a distance D2C from the top surface 204T of the epitaxial layer 204, and the distance D1 is greater than or equal to the distance D2C. In some embodiments, the bottom surface 230PB of the conductive component 230P is located between the bottom surfaces 320P1B and 320P2B of the etch stop layers 320P1 and 320P2 and the top surface 204T of the epitaxial layer 204. And because the etch stop layers 320P1 and 320P2 are located above the gates 214-1 and 214-2, the distance D4 between the bottom surfaces 320P1B and 320P2B of the etch stop layers 320P1 and 320P2 and the top surface 204T of the epitaxial layer 204 is greater than the distance D1 and the distance D2C.

In some embodiments, the conductive component 230P of the semiconductor device 500D is a part of the source contact 230 and is inserted between the gates 214-1 and 214-2 of the separated gate structure 250 along the direction 100 (lateral direction), so that the bottom surface 230PB of the conductive component 230P between the gates 214-1 and 214-2 is located between the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204. The provision of the conductive component 230P can reduce the lateral (along the direction 100) gate-drain capacitance ( _Cgd,L ) without increasing the size of the device. The overall gate-drain capacitance (C _gd ) and feedback capacitance (C _rss =C _gd ) are further reduced, and the gate on-resistance (R _on,sp ) is maintained substantially the same. In addition, since the conductive component 230P is similar to a field plate structure, the electric field distribution of the gate dielectric layer 328 near the inner edges of the gates 214 - 1 and 214 - 2 (side surfaces 214 - 1S1 and 214 - 2S1) can be made more uniform, thereby improving the reliability of the gate dielectric layer 228. In addition, the semiconductor device 500D is a power metal oxide semiconductor field effect transistor formed by a silicon carbide substrate, which has the advantages of fast switching and high resistance voltage, and is therefore suitable for high frequency and high power applications.

Figures 5-8A, 9-10 are cross-sectional schematic diagrams of the intermediate stages of forming the semiconductor device 500A of some embodiments of the present invention shown in Figure 1, and the same or similar element symbols as those in Figures 1 to 4 represent the same or similar elements. As shown in Figure 5, A silicon carbide substrate 200 having a first conductivity type is provided, for example, an N-type heavily doped (N+) silicon carbide substrate 200.

Next, an epitaxial growth process is performed to grow an epitaxial layer 204 having a first conductivity type on the top surface 200T of the silicon carbide substrate 200, such as an N-type lightly doped (N-) silicon carbide epitaxial layer 204. In some embodiments, the epitaxial process includes chemical vapor deposition (CVD) deposition, molecular beam epitaxy (MBE), other suitable epitaxial growth processes, or a combination thereof.

Next, several ion implantation processes are performed to form two well regions 206 separated from each other along the direction 100 and having the second conductivity type in the epitaxial layer 204, such as P-type well regions 206. Furthermore, two source regions 208 having the first conductivity type are formed on the corresponding well regions 206 and close to the top surface 204T of the epitaxial layer 204, such as N-type heavily doped (N+) source regions 208. In addition, the aforementioned ion implantation process forms two wiring doped regions 210 adjacent to the source region 208 and having the second conductivity type on the corresponding well region 210. After the aforementioned ion implantation process is performed, an annealing process may be performed to activate the dopants in the well region 206, the source region 208, and the wiring doping region 210. In some embodiments, the annealing process includes laser annealing, rapid thermal annealing (RTA), other suitable annealing processes, or a combination thereof. In some embodiments, since the silicon carbide substrate 200 and the epitaxial layer 204 are both made of silicon carbide, the process temperature of the aforementioned annealing process ranges from about 1600° C. to about 1700° C., which is much higher than the annealing process temperature of the silicon substrate. Furthermore, since the annealing process applicable to the silicon carbide substrate/epitaxial layer has a relatively high process temperature, the doped regions including the well region 206, the source region 208 and the wiring doped region 210 are formed first, and then the separated gate structure 250 and the conductive component 252 are formed, so as to avoid damage to the gates 214-1, 214-2 and the conductive component 252 made of, for example, polysilicon due to excessively high annealing process temperatures.

After forming the well region 206, the source region 208 and the wiring doped region 210, a deposition process and a subsequent patterning process are performed to form gate dielectric material layers 212-1, 212-2 and gates 214-1, 214-2 located on the gate dielectric material layers 212-1, 212-2 on the top surface 204T of the epitaxial layer 204. The gates 214-1, 214-2 overlap with the corresponding source region 208. In some embodiments, the gates 214-1, 214-2 include polysilicon, and the gate dielectric material layers 212-1, 212-2 include silicon oxide.

Next, as shown in FIG. 6 , a deposition process is performed to conformally form a dielectric material layer 218 on the gates 214-1 and 214-2. The dielectric material layer 218 covers the gates 214-1 and 214-2. The dielectric material layer 218 has a thickness T3 along the direction 110, which is smaller than a distance D1 between the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204. In other words, the upper surface 218T of the portion of the dielectric material layer 218 between the gates 214-1 and 214-2 is located between the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204. In some embodiments, the gate dielectric material layers 212-1 and 212-2 and the dielectric material layer 218 include the same or similar materials.

Next, as shown in FIG. 7 , a deposition process is performed to conformally form a conductive layer 220 on the dielectric material layer 218. In some embodiments, the conductive layer 220 has a thickness T1 along the direction 110. In some embodiments, the conductive layer 220 includes polysilicon.

Next, as shown in FIG. 8A , a patterning process is performed to remove a portion of the conductive layer 220 and a portion of the dielectric material layer 218 between the gates 214-1 and 214-2 and on the source region 208 outside the gates 214-1 and 214-2, so as to form dielectric material layers 218P-1 and 218P-2 extending from above the gates 214-1 and 214-2 to between the gates 214-1 and 214-2, respectively, and a conductive component 252 including conductive patterns 220P-1 and 220P-2. The conductive component 252 is formed on the dielectric material layers 218P-1 and 218P-2 and contacts the upper surface of the dielectric material layers 218P-1 and 218P-2 (the position is the same as the lower surface 220P-1B and 220P-2B of the conductive patterns 220P-1 and 220P-2). In addition, the above-mentioned patterning process exposes the top surface 204T of the epitaxial layer 204 between the gates 214-1 and 214-2 and the portion of the source region 208 not covered by the gates 214-1 and 214-2. In some embodiments, the distance D1 between the top surfaces 214-1T, 214-2T of the gates 214-1, 214-2 and the top surface 204T of the epitaxial layer 204 is greater than the distance D2 between the bottom surfaces 220P-1B, 220P-2B of the conductive patterns 220P-1, 220P-2 and the top surface 204T of the epitaxial layer 204.

In some other embodiments, the lateral size (size along direction 100) of the mask used in the patterning process can be adjusted to form conductive patterns of different lateral sizes above the gates 214-1 and 214-2. FIG. 8B is a cross-sectional schematic diagram of an intermediate stage of forming the semiconductor device 500B of some embodiments of the present invention shown in FIG. 2. FIG. 8C is a cross-sectional schematic diagram of an intermediate stage of forming the semiconductor device 500C of some embodiments of the present invention shown in FIG. 3. As shown in FIG. 8B , the patterning process can remove a portion of the conductive layer 220 and a portion of the dielectric material layer 218 on the source region 208 outside the gates 214-1 and 214-2 to form the patterned dielectric material layers 218PA-1 and 218PA-2 and the conductive component 252A including the conductive patterns 220PA-1 and 220PA-2 of the semiconductor device 500B as shown in FIG. 2 , and make a portion of the source region 208 contact the patterned dielectric material layers 218PA-1 and 218PA-2. As shown in FIG. 8C , the patterning process can remove part of the conductive layer 220 and part of the dielectric material layer 218 on the gates 214-1 and 214-2, exposing part of the gates 214-1 and 214-2 close to the source region 208, so as to form the patterned dielectric material layers 218PB-1 and 218PB-2 and the conductive component 252B including the conductive patterns 220PB-1 and 220PB-2 of the semiconductor device 500C as shown in FIG. 3 .

After forming the conductive patterns 220P-1 and 220P-2, a deposition process is performed to fully form a dielectric material layer 224 to cover the conductive patterns 220P-1 and 220P-2 and the top surface 204T of the epitaxial layer 204 between the gates 214-1 and 214-2, as shown in FIG9. In some embodiments, the thickness T4 of the dielectric material layer 224 along the direction 110 is greater than the distance D4 between the top surfaces 220P-1T and 220P-2T of the conductive patterns 220P-1 and 220P-2 and the top surface 204T of the epitaxial layer 204 to fill the gap between the gates 214-1 and 214-2. In some embodiments, the dielectric material layer 224 may be an interlayer dielectric layer (ILD), the material of which includes silicon oxide, silicon nitride, silicon oxynitride, phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or a combination thereof.

Next, as shown in FIG. 10 , a patterning process is performed to remove a portion of the dielectric material layer 224 on the source region 208 to form a patterned dielectric material layer 224P, and to expose a portion of the source region 208 and the wiring doping region 210. After the above process, a gate dielectric layer 228 is formed, and the formation position of the source contact 230 is defined. In some embodiments, the gate dielectric layer 228 is a composite layer including gate dielectric material layers 212-1, 212-2, dielectric material layers 218P-1, 218P-2, and dielectric material layer 224P.

Next, as shown in FIG. 1, multiple deposition processes and patterning processes are performed to form a source contact 230 on the dielectric material layers 218P-1, 218P-2, the conductive component 252 (conductive patterns 220P-1, 220P-2) and the patterned dielectric material layer 224P. The source contact 230 electrically connects the source region 208, the wiring doped region 210 and the conductive component 252 (conductive patterns 220P-1, 220P-2). In addition, a drain contact 240 is formed on the bottom surface 200B of the silicon carbide substrate 200. The drain contact 240 is electrically connected to the silicon carbide substrate 200. After the above process, a semiconductor device 500A is formed.

FIGS. 11-18 are cross-sectional schematic diagrams of intermediate stages of forming the semiconductor device 500D of some embodiments of the present invention shown in FIG. 4, wherein the same or similar element symbols as those in FIGS. 1-10 represent the same or similar elements. As shown in FIG. 11, a process same as or similar to that in FIG. 5 is performed to provide a silicon carbide substrate 200 having a first conductivity type, and then an epitaxial layer 204 having a first conductivity type is grown on the top surface 200T of the silicon carbide substrate 200. Thereafter, two well regions 206 are formed in the epitaxial layer 204, and two source regions 208 having a first conductivity type are formed on the corresponding well regions 206 and close to the top surface 204T of the epitaxial layer 204, respectively. In addition, two wiring doped regions 210 of the second conductivity type are formed adjacent to the source region 208 on the corresponding well region 210. After the well region 206, the source region 208 and the wiring doped region 210 are formed, gate dielectric material layers 212-1, 212-2 and gates 214-1, 214-2 located on the gate dielectric material layers 212-1, 212-2 are formed on the top surface 204T of the epitaxial layer 204.

Next, a deposition process is performed to form a dielectric material layer 318 on the gates 214-1 and 214-2. The dielectric material layer 318 covers the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204 between the gates 214-1 and 214-2. The dielectric material layer 318 has a thickness T5 along the direction 110, which is greater than the distance D1 between the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204. In some embodiments, the gate dielectric material layers 212-1, 212-2 and the dielectric material layers 218, 318 include the same or similar materials.

Next, as shown in FIG. 12 , a planarization process is performed on the dielectric material layer 318. The planarization process stops above the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 to form a dielectric material layer 318R covering the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2. The dielectric material layer 318R has a flat top surface 318RT, and a thickness T6 of the dielectric material layer 318R along the direction 110 is still greater than a distance D1 between the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

Next, as shown in FIG. 13 , a deposition process is performed to form an etch stop layer 320 on the flat top surface 318RT of the dielectric material layer 318R. The etch stop layer 320 is a planar layer and covers the gates 214-1, 214-2 and the top surface 204T of the epitaxial layer 204 between the gates 214-1, 214-2.

Next, as shown in FIG. 14 , a dielectric material layer 322 is formed on the etch stop layer 320 to cover the gates 214-1, 214-2 and the top surface 204T of the epitaxial layer 204 between the gates 214-1, 214-2. In some embodiments, the dielectric material layers 224 and 322 include the same or similar materials.

Next, as shown in FIG. 15 , a lithography process and a subsequent selective etching process are performed to remove a portion of the dielectric material layer 322 above the top surface 204T of the epitaxial layer 204 between the gates 214-1 and 214-2 to form an opening 324 that passes through the dielectric material layer 322E. In some embodiments, the etch stop layer 320 serves as an etch stop layer for the selective etching process, so that the bottom surface 324B of the opening 324 exposes a portion of the etch stop layer 320. In some embodiments, the opening 324 can use the same mask as the gate contact opening (not shown) formed on the gates 214-1 and 214-2.

Next, as shown in FIG. 16 , another selective etching process is performed to remove a portion of the etch stop layer 320 from the bottom surface 324B of the opening 324 to form an opening 325 that passes through the dielectric material layer 322E and the etch stop layer 320E. In some embodiments, the selective etching process for forming the openings 324 and 325 may use different etching gases. Furthermore, the selective etching process for forming the opening 325 uses the dielectric material layer 318R as the etch stop layer of the above-mentioned selective etching process, so that the bottom surface 325B of the opening 325 exposes a portion of the dielectric material layer 318R.

Next, as shown in FIG. 17 , an etching process is performed to remove a portion of the dielectric material layer 318R from the bottom surface 325B of the opening 325 to form an opening 326 that passes through the dielectric material layer 322E, the etch stop layer 320E, and a portion of the dielectric material layer 318E. In some embodiments, the etching end point can be determined by controlling the process time of the etching process, so that the bottom surface 326B of the opening 326 (i.e., the upper surface of the dielectric material layer 318E above the top surface 204T of the epitaxial layer 204 between the gates 214-1 and 214-2) is located between the top surfaces 214-1T and 214-2T of the gates 214-1 and 214-2 and the top surface 204T of the epitaxial layer 204, and is at a distance D2C from the top surface 204T of the epitaxial layer 204. In some embodiments, when the opening 326 is formed, a gate contact opening is formed on the gates 214-1 and 214-2 (not shown).

Next, as shown in FIG. 18 , a patterning process is performed to remove a portion of the dielectric material layer 322E, a portion of the etch stop layer 320E, and a portion of the dielectric material layer 318E on the source region 208, and expose a portion of the source region 208 and the wiring doped region 210 to form a dielectric material layer 318P, dielectric material layers 322P1, 322P2 separated from each other along the direction 100, and etch stop layers 320P1, 320P2. Through the above process, a gate dielectric layer 328 is formed, and a formation position of the source contact 230 is defined. In some embodiments, the gate dielectric layer 328 is a composite layer including gate dielectric material layers 212-1, 212-2, dielectric material layer 318P, etch stop layers 320P1, 320P2, and dielectric material layers 322P1, 322P2.

Next, as shown in FIG. 4 , a source contact 230 is formed on the dielectric material layer 318P, the etch stop layers 320P1, 320P2, and the dielectric material layers 322P1, 322P2. The source contact 230 fills the opening 326 (FIG. 18) and is electrically connected to the source region 208. In some embodiments, the portion of the source contact 230P that fills the opening 326 (FIG. 18) forms a conductive component 230P of the semiconductor device 500D. In addition, a drain contact 240 is formed on the bottom surface 200B of the silicon carbide substrate 200. The drain contact 240 is electrically connected to the silicon carbide substrate 200. After the above process, the semiconductor device 500D is formed.

The present invention provides a semiconductor device and a method for forming the same. The semiconductor device includes a silicon carbide substrate, an epitaxial layer, at least two well regions, at least two source regions, a separate gate structure, and a conductive component. The conductive component of the semiconductor device is inserted laterally between the gates of the separate gate structure and is electrically connected to the source contact. In some embodiments, a conductive component made of polysilicon is embedded in a gate dielectric layer (composite layer) and can conformally cover the top surface and adjacent side surfaces of the isolated gate, and by controlling the thickness of the dielectric material layer located between the conductive component and the gate, the lower surface of the conductive component between the isolated gates is located between the top surface of the isolated gate and the top surface of the epitaxial layer. In some embodiments, the conductive component is a part of the source contact. By forming an etch stop layer in the gate dielectric layer (composite layer) and a selective etching process, the bottom level of the opening formed in the gate dielectric layer between the separated gates can be controlled without increasing the number of process masks, so that a part of the source contact subsequently filled into the above opening forms the conductive component, and the bottom surface of the conductive component between the separated gates is located between the top surface of the separated gate and the top surface of the epitaxial layer. The conductive component of the semiconductor device can reduce the lateral (along the direction 100) gate-drain capacitance ( _Cgd,L ) without increasing the size of the device. The overall gate-drain capacitance (C _gd ) and feedback capacitance (C _rss =C _gd ) are further reduced, and the gate on-resistance (R _on,sp ) is maintained at approximately the same level. Furthermore, since the conductive component is similar to a field plate structure, the electric field distribution of the gate dielectric layer near the inner edge of the separation gate can be made more uniform, thereby improving the reliability of the gate dielectric layer. In addition, the semiconductor device is a power metal oxide semiconductor field effect transistor formed on a silicon carbide substrate, which has the advantages of fast switching and high resistance voltage, and is therefore suitable for high frequency and high power applications.

Although the present invention is disclosed as above by the aforementioned embodiments, it is not intended to limit the present invention. Those with common knowledge in the technical field to which the present invention belongs may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the patent application attached hereto.

500A:Semiconductor device

200: Silicon carbide substrate

200T, 204T, 214-1T, 214-2T, 250T: Top

200B: Bottom

204: Epitaxial layer

206: Well area

208: Source region

210: Wiring mixed area

214-1,214-2: Gate

214-1S1,214-1S2,214-2S1,214-2S2: Side

220P-1,220P-2: Conductive pattern

220P-1B, 220P-2B: Lower surface

228: Gate dielectric layer

230: Source contact

252: Conductive components

240: Drain contact

250: Split gate structure

D1,D2,D3:Distance

T1, T2: thickness

Claims (23)

A semiconductor device comprises: a silicon carbide substrate having a first conductivity type; an epitaxial layer disposed on a top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; at least two well regions located in the epitaxial layer, wherein the well regions are separated from each other along a first direction and have a second conductivity type; at least two source regions, respectively located on the corresponding well regions and close to a top surface of the epitaxial layer, wherein the source regions have the first conductivity type; a separated gate structure disposed on the top surface of the epitaxial layer, wherein the separated gate structure comprises: a first gate and a second gate separated from each other along the first direction; , respectively overlapping with the corresponding source regions; and a gate dielectric layer, surrounding the first gate and the second gate; and a conductive component, disposed above the portion of the epitaxial layer between the well regions and extending along a second direction to between the first gate and the second gate, wherein a lower surface of the portion of the conductive component between the first gate and the second gate is located between the multiple top surfaces of the first gate and the second gate and the top surface of the epitaxial layer, wherein the conductive component has an upper surface opposite to the lower surface and away from the top surface of the epitaxial layer, and the upper surface is completely located above the top surfaces of the first gate and the second gate. A semiconductor device as claimed in claim 1, wherein the conductive component is electrically connected to the source regions. A semiconductor device as claimed in claim 1, wherein the top surfaces of the first gate and the second gate are at a first distance from the top surface of the epitaxial layer, and the portion of the gate dielectric layer below the lower surface of the conductive component is at a second distance from the top surface of the epitaxial layer, wherein the first distance is greater than or equal to the second distance. A semiconductor device as claimed in claim 1, wherein the conductive component comprises: a first conductive pattern covering the top surface of the first gate and partially covering a first side surface of the first gate; and a second conductive pattern covering the top surface of the second gate and partially covering a second side surface of the second gate, wherein the first side surface of the first gate and the second side surface of the second gate are close to each other. A semiconductor device as claimed in claim 4, wherein the first conductive pattern on the top surface of the first gate has a first thickness in the second direction, wherein the portion of the gate dielectric layer between the first conductive pattern and the first gate along the first direction has a second thickness in the first direction, and wherein the first gate and the second gate are separated by a third distance in the first direction, wherein the first thickness is less than or equal to the difference between one-half of the third distance and the second thickness. A semiconductor device as claimed in claim 4, wherein the first conductive pattern and the second conductive pattern overlap with the corresponding source regions respectively. A semiconductor device as claimed in claim 4, wherein the first conductive pattern and the second conductive pattern are embedded in the gate dielectric layer. A semiconductor device as claimed in claim 4, wherein the first conductive pattern and the second conductive pattern include polysilicon. A semiconductor device as claimed in claim 4, wherein the first conductive pattern completely covers the top surface of the first gate and partially covers a third side of the first gate opposite to the first side. A semiconductor device as claimed in claim 9, wherein the portion of the first conductive pattern covering the third side of the first gate is located directly above the corresponding source region. A semiconductor device as claimed in claim 4, wherein the first gate has a first width along the first direction, and the portion of the first gate not covered by the first conductive pattern has a second width along the first direction, wherein the second width is less than or equal to one-half of the first width. The semiconductor device of claim 1 further comprises: a source contact disposed on the top surface of the separated gate structure and extending to cover the source regions, wherein the source contact is electrically connected to the source regions; and a drain contact disposed on a bottom surface of the silicon carbide substrate and electrically connected to the silicon carbide substrate. The semiconductor device of claim 12 further includes: a first etch stop layer and a second etch stop layer, which are disposed in the gate dielectric layer and are located above the first gate and the second gate, respectively, wherein the first etch stop layer and the second etch stop layer are planar layers extending along the first direction. A semiconductor device as claimed in claim 13, wherein the conductive component is part of the source contact. A semiconductor device as claimed in claim 14, wherein opposite sides of the conductive component contact the first etch stop layer and the second etch stop layer respectively. A semiconductor device as claimed in claim 14, wherein the lower surface of a portion of the conductive component between the first gate and the second gate is located between multiple bottom surfaces of the first etch stop layer and the second etch stop layer and the top surface of the epitaxial layer. A method for forming a semiconductor device includes: providing a silicon carbide substrate, the silicon carbide substrate having a first conductivity type; growing an epitaxial layer on a top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; forming at least two well regions in the epitaxial layer, wherein the well regions are separated from each other along a first direction and have a second conductivity type; and forming a plurality of semiconductor devices at the corresponding well regions. At least two source regions are formed on the epitaxial layer and close to a top surface of the epitaxial layer, wherein the source regions have the first conductivity type; after forming the well regions and the source regions, a first gate dielectric material layer, a second gate dielectric material layer, a first gate on the first gate dielectric material layer, and a second gate on the second gate dielectric material layer are formed on the top surface of the epitaxial layer. The first gate and the second gate overlap with the corresponding source regions respectively; a third dielectric material layer is formed on the first gate and the second gate, and an upper surface of the third dielectric material layer between the first gate and the second gate is located between the top surfaces of the first gate and the second gate and the top surface of the epitaxial layer; A conductive component is formed on the third dielectric material layer, wherein the conductive component contacts the upper surface of the third dielectric material layer, wherein the conductive component has a first upper surface away from the top surface of the epitaxial layer, and the first upper surface is completely above the top surfaces of the first gate and the second gate; and a source contact is formed on the third dielectric material layer, wherein the source contact is electrically connected to the conductive component. A method for forming a semiconductor device as claimed in claim 17, wherein the third dielectric material layer conformally covers the first gate and the second gate, wherein forming the conductive component comprises: conformally forming a conductive layer on the third dielectric material layer; and performing a first patterning process to remove a portion of the conductive layer to form a first conductive pattern and a second conductive pattern extending from above the first gate and the second gate to between the first gate and the second gate. The method for forming a semiconductor device as claimed in claim 18 further includes: forming a fourth dielectric material layer on the entire surface; performing a second patterning process to remove a portion of the fourth dielectric material layer on the source regions; and forming the source contact on the patterned fourth dielectric material layer, wherein the source contact is electrically connected to the source regions, the first conductive pattern, and the second conductive pattern; and forming a drain contact on a bottom surface of the silicon carbide substrate, wherein the drain contact is electrically connected to the silicon carbide substrate. A method for forming a semiconductor device as claimed in claim 18, wherein the first patterning process removes part of the conductive layer and part of the third dielectric material layer on the source regions, and makes part of the source regions contact the patterned third dielectric material layer. A method for forming a semiconductor device as claimed in claim 18, wherein the first patterning process removes a portion of the conductive layer and a portion of the third dielectric material layer on the first gate and the second gate, so that a portion of the first gate and a portion of the second gate close to the source regions are exposed. The method for forming a semiconductor device as claimed in claim 17, wherein after forming the third dielectric material layer, the method comprises: performing a planarization process on the third dielectric material layer so that the planarized third dielectric material layer covers the top surfaces of the first gate and the second gate; forming an etch stop layer on a top surface of the planarized third dielectric material layer; forming a fourth dielectric material on the etch stop layer; The method comprises: performing a first selective etching process to remove a portion of the fourth dielectric material layer between the first gate and the second gate to form a first opening, wherein a bottom surface of the first opening exposes a portion of the etch stop layer; performing a second selective etching process to remove a portion of the etch stop layer from the bottom surface of the first opening to form a second opening, wherein a bottom surface of the second opening exposes The method further comprises: performing a third etching process to remove a portion of the third dielectric material layer from the bottom surface of the second opening to form a third opening, wherein a bottom surface of the third opening is located between the top surfaces of the first gate and the second gate and the top surface of the epitaxial layer; performing a patterning process to remove a portion of the fourth dielectric material layer on the source regions, a portion of the etching The stop layer and a portion of the third dielectric material layer; and forming the source contact on the patterned fourth dielectric material layer, wherein the source contact fills the third opening and electrically connects the source regions, wherein the portion of the source contact filling the third opening forms the conductive component; and forming a drain contact on a bottom surface of the silicon carbide substrate, wherein the drain contact is electrically connected to the silicon carbide substrate. A method for forming a semiconductor device as claimed in claim 22, wherein while forming the third opening, a plurality of gate contact openings are formed on the first gate and the second gate.

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