TWI897397B - Semiconductor device and fabricating method thereof - Google Patents

Abstract

A semiconductor device includes a substrate and a trench disposed in the substrate. A first field plate and a second field plate are disposed in the trench, where the second field plate is located below and laterally separated from the first field plate. A first dielectric layer and a second dielectric layer are disposed on a sidewall of the trench. The first dielectric layer surrounds an outer side surface of the first field plate and has a first thickness. The second dielectric layer surrounds a side surface and a bottom surface of the second field plate and has a second thickness greater than the first thickness. The first field plate is located directly above the second dielectric layer. A gate electrode is disposed on the substrate and directly connected to the first field plate.

Description

Semiconductor device and manufacturing method thereof

This disclosure relates to semiconductor technology, and more particularly to semiconductor devices including vertically diffused metal oxide semiconductor (VDMOS) structures and methods for fabricating the same.

In power electronics systems, power transistors are commonly used as power components such as power switches and converters. Power transistors refer to transistors that operate under high voltage and high current conditions. The most common power transistors are metal-oxide-semiconductor field effect transistors (MOSFETs), which include horizontal structures such as laterally diffused metal oxide semiconductor (LDMOS) field effect transistors (FETs), and vertical structures such as planar gate MOSFETs and trench gate MOSFETs. Planar gate MOSFETs are vertically diffused metal oxide semiconductors (LDMOS). The VDMOS (VDMOS) structure has advantages such as fast switching speed and high voltage resistance. However, the conventional VDMOS structure still requires much improvement. For example, it is generally unable to simultaneously reduce on-resistance (Ron) and various parasitic capacitances.

In light of this, the present disclosure proposes a semiconductor device and a method for manufacturing the same. A trench is disposed beneath the gate of a vertical diffused metal oxide semiconductor (VDMOS) structure. By configuring a field plate and dielectric layer within the trench, the on-resistance (Ron) and various parasitic capacitances, such as gate-to-drain capacitance (Cgd), can be simultaneously reduced, thereby significantly improving the switching loss and figure of merit (FOM) of the semiconductor device.

According to one embodiment of the present disclosure, a semiconductor device is provided, comprising a substrate, a trench, a first field plate, a second field plate, a first dielectric layer, a second dielectric layer, and a gate electrode. The trench is disposed in the substrate, and the first and second field plates are disposed within the trench. The second field plate is located below the first field plate and laterally separated from the first field plate. The first and second dielectric layers are disposed on the sidewalls of the trench. The first dielectric layer surrounds the outer surface of the first field plate and has a first thickness. The second dielectric layer surrounds the side and bottom surfaces of the second field plate and has a second thickness greater than the first thickness. The first field plate is located directly above the second dielectric layer. The gate electrode is disposed on the substrate and connected to the first field plate.

According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising the following steps: providing a substrate; forming a trench in the substrate; forming a first field plate in the trench; forming a second field plate in the trench, located below and laterally separated from the first field plate; forming a first dielectric layer on the sidewalls of the trench, surrounding the outer surface of the first field plate, and having a first thickness; forming a second dielectric layer on the sidewalls of the trench, surrounding the side surfaces and bottom surface of the second field plate, and having a second thickness greater than the first thickness, wherein the first field plate is formed directly above the second dielectric layer; and forming a gate electrode on the substrate, connected to the first field plate.

To make the features of this disclosure more clearly understood, the following examples are given below, along with accompanying drawings, for a detailed description.

100: Semiconductor devices

101: Base

101F: First Surface

101B: Second surface

102: Epitaxial layer

103: Drain area

105: Groove

106: Well Area

107: Source lightly doped region

108: Source Region

109: Mixed Area

111: First board

111-1: Part 1

111-2: Part 2

112: Second board

113: Third Board

115: Gate electrode

117: spacer

119: Metal silicide layer

120: Dielectric material layer

121: First dielectric layer

122: Second dielectric layer

123: Third dielectric layer

124: Gate dielectric layer

125: Dielectric Materials

130: Interlayer dielectric layer

131: Source contact hole

132: Source Contact

134: Source electrode

136: Drain electrode

139: First semiconductor material layer

140: Initial Field Plate

140T: Upper part

141: Opening

143: Patterned Photoresist

150: Second semiconductor material layer

160: Junction Field Effect Transistor (JFET) Region

T1: First thickness

T2: Second thickness

T3: Third thickness

S101, S103, S105, S107, S109, S111, S113, S115, S117, S119, S121, S123, S125, S127, S129, S131: Steps

To facilitate understanding of the following, this disclosure may be read in conjunction with the accompanying drawings and detailed descriptions. This disclosure provides detailed explanations of the specific embodiments of this disclosure and illustrates the working principles of these specific embodiments through reference to the corresponding drawings. Furthermore, for the sake of clarity, the features in the drawings may not be drawn to scale; therefore, the dimensions of some features in some drawings may be intentionally exaggerated or reduced.

Figure 1 is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present disclosure.

Figures 2, 3, 4, 5, 6, 7, 8, 9, and 10 are schematic cross-sectional views illustrating certain stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

This disclosure provides several different embodiments that can be used to implement various features of the disclosure. For simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, a statement below regarding "a first feature formed on or above a second feature" may mean "the first feature and the second feature are directly in contact" or "an additional feature exists between the first and second features," such that the first and second features are not in direct contact. Furthermore, various embodiments in this disclosure may use repeated reference numerals and/or textual notations. This repetition is for simplicity and clarity and is not intended to indicate a relationship between different embodiments and/or configurations.

Furthermore, when spatially relative terms such as "below," "lower," "down," "above," "upper," "top," "bottom," and similar terms are used in this disclosure to describe the relative relationship of one element or feature to another (or multiple) elements or features in the drawings, for ease of description. In addition to the orientations shown in the drawings, these spatially relative terms are also used to describe possible orientations of the semiconductor device during use and operation. Spatially relative terms used to describe different orientations of the semiconductor device (rotated 90 degrees or other orientations) should be interpreted in a similar manner.

Although this disclosure uses terms such as first, second, and third to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and do not in themselves imply or represent any prior number of the elements, nor do they represent the order in which one element is arranged relative to another, or the order in which one element is manufactured. Therefore, without departing from the scope of the specific embodiments of this disclosure, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" used in this disclosure generally mean within 20%, preferably within 10%, and more preferably within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, meaning that even without the specific wording "about" or "substantially," the meaning of "about" or "substantially" may be implied.

The terms "couple," "coupled," and "electrically connected" mentioned in this disclosure include any direct and indirect electrical connection methods. For example, if a first component is described as being coupled to a second component, it means that the first component can be directly electrically connected to the second component or indirectly electrically connected to the second component through other devices or connection methods.

Although the following describes the present invention using specific embodiments, the principles of the present invention can also be applied to other embodiments. Furthermore, to avoid obscuring the spirit of the present invention, certain details may be omitted. Such omitted details are within the knowledge of a person of ordinary skill in the art.

This disclosure relates to a semiconductor device including a vertically diffused metal oxide semiconductor (VDMOS) structure and a method for fabricating the same. In one embodiment, an upper field plate and a lower field plate are disposed laterally spaced apart in a trench below a gate electrode. The upper and lower field plates are surrounded by dielectric layers of different thicknesses, with the dielectric layer surrounding the upper field plate being significantly thinner than the dielectric layer surrounding the lower field plate. The upper field plate is connected to the gate electrode, while the lower field plate is electrically connected to the source electrode and grounded. The thinner dielectric layer on the sidewalls of the upper field plate facilitates charge accumulation in the junction field-effect transistor (JFET) region, which helps reduce on-resistance (Ron). A thicker dielectric layer on the sidewalls of the lower field plate prevents electron accumulation, thereby reducing gate-to-drain capacitance (Cgd) and, in turn, gate-to-drain charge (Qgd). This significantly improves the switching loss and figure of merit (FOM) of the semiconductor device. The FOM is the product of the on-resistance (Ron) and the gate-to-drain charge (Qgd).

FIG1 is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. Semiconductor device 100 includes a substrate 101 having a first surface 101F (e.g., front surface) and a second surface 101B (e.g., back surface). Substrate 101 includes a drain region 103 disposed on second surface 110B. Drain region 103 has a first conductivity type, such as an N-type heavily doped region (N ⁺ ). Substrate 101 further includes an epitaxial layer 102 disposed on drain region 103. Epitaxial layer 102 also has a first conductivity type, such as an N-type epitaxial layer. The doping concentration of drain region 103 is significantly higher than that of epitaxial layer 102. In some embodiments, the drain region 103 is, for example, an N-type heavily doped silicon or silicon carbide substrate (N ⁺ SiC substrate), and the epitaxial layer 102 is, for example, an N-type lightly doped silicon or silicon carbide epitaxial layer (N ⁻ SiC epitaxial layer), but is not limited thereto.

As shown in FIG. 1 , semiconductor device 100 includes a gate electrode 115 disposed on a first surface 101F of a substrate 101, and spacers 117 disposed on sidewalls of gate electrode 115. In one embodiment, a metal silicide layer 119, such as cobalt silicide (CoSix), may be disposed on the top surface of gate electrode 115. Metal silicide layer 119 helps reduce the resistance of gate electrode 115. Furthermore, trench 105 is disposed in epitaxial layer 102 of substrate 101 and is located directly below gate electrode 115. A first field plate 111 is disposed within trench 105. First field plate 111 comprises a laterally separated first portion 111-1 and a laterally separated second portion 111-2. First field plate 111 is connected to gate electrode 115. A second field plate 112 is also disposed within trench 105, below and laterally separated from first field plate 111. The first and second field plates 111 and 112 do not overlap in a vertical projection direction, such as the Z-axis. Furthermore, a third field plate 113 is disposed within trench 105, directly above and connected to second field plate 112. In a first direction perpendicular to the sidewalls of trench 105, such as the X-axis, the width of third field plate 113 is smaller than the width of second field plate 112. The third field plate 113 is also laterally separated from the first field plate 111. The first portion 111-1 and the second portion 111-2 of the first field plate 111 are located on either side of the third field plate 113. The first field plate 111 and the third field plate 113 do not overlap in a vertical projection direction, such as the Z-axis.

Additionally, a first dielectric layer 121 is disposed on the sidewalls of the trench 105, surrounding the outer surface of the first field plate 111 and contacting the outer surface of the first portion 111-1 and the outer surface of the second portion 111-2. In a first direction, such as the X-axis, the first dielectric layer 121 has a first thickness T1. In some embodiments, the first thickness T1 is approximately 500 angstroms (Å) to 600 angstroms (Å), but is not limited thereto. A second dielectric layer 122 is also disposed on the sidewalls of the trench 105, surrounding the side surfaces and bottom surface of the second field plate 112. In the first direction, such as the X-axis, the second dielectric layer 122 has a second thickness T2 that is greater than the first thickness T1. In some embodiments, the second thickness T2 is approximately 2000 angstroms (Å) to 3000 angstroms (Å), but is not limited thereto. Furthermore, the first field plate 111 is positioned directly above the second dielectric layer 122. In some embodiments, the second thickness T2 of the second dielectric layer 122 may be greater than the widths of the first portion 111-1 and the second portion 111-2. Furthermore, a third dielectric layer 123 is disposed within the trench 105, surrounding the sides and top of the third field plate 113, and located between the first and third field plates 111, 113, and between the gate electrode 115 and the third field plate 113. In a first direction, such as the X-axis, the third dielectric layer 123 has a third thickness T3 that is greater than the first thickness T1 and may be less than or approximately equal to the second thickness T2. In some embodiments, the third thickness T3 is approximately 2.5 to 4 times the first thickness T1. In addition, the gate dielectric layer 124 is disposed between the gate electrode 115 and the substrate 101. The gate dielectric layer 124 is connected to the first dielectric layer 121, and the gate dielectric layer 124 may have the same first thickness T1 as the first dielectric layer 121.

Still referring to FIG. 1 , the semiconductor device 100 further includes a well region 106 disposed on the first surface 101F of the substrate 101. The well region 106 has a second conductivity type, such as a P-type well region, and is located on both sides of the trench 105. The well region 106 can serve as a body region (P-body), and the region between the well region 106 and the trench 105 is a junction field effect transistor (JFET) region 160. A source region 108 is disposed on the first surface 101F of the substrate 101, located in the well region 106. The source region 108 has a first conductivity type, such as an N-type heavily doped region (N ⁺ ), and is laterally separated from the gate electrode 115. In one embodiment, the semiconductor device 100 may further include a lightly doped source region 107 disposed in the well region 106 and adjacent to a side surface of the source region 108. The lightly doped source region 107 has a first conductivity type, such as an N-type lightly doped region ( ^N- ), and is located directly below a spacer 117 on a sidewall of the gate electrode 115. In a first direction, such as the X-axis, the lightly doped source region 107 is located between the source region 108 and the gate electrode 115. The lightly doped source region 107 can reduce the peak electric field intensity near the source region 108, thereby preventing or reducing leakage current and improving the reliability of the semiconductor device 100.

In addition, an interlayer dielectric layer (ILD) 130 is disposed on the first surface 101F of the substrate 101, covering the gate electrode 115, the spacer 117, the metal silicide layer 119, and the source region 108. A source electrode 134 is disposed on the first surface 101F of the substrate 101, located on the ILD 130, and electrically connected to the source region 108 via a source contact 132. The source contact 132 passes through the interlayer dielectric layer 130, the gate dielectric layer 124, and the source region 108, extending downward into the well region 106. A doped region 109 having a second conductivity type, such as a heavily doped P-type region (P ⁺ ), may be disposed in the well region 106 directly below the bottom of the source contact 132. The doped region 109 may serve as a bulk base region and be electrically connected to the source electrode 134 via the source contact 132. Furthermore, a drain electrode 136 is disposed below the second surface 101B of the substrate 101 and directly contacts the drain region 103.

The second field plate 112 and the third field plate 113 may be electrically connected to the source electrode 134 via an interconnect structure disposed in the interlayer dielectric layer 130 and a via penetrating the third dielectric layer 123 , while the first field plate 111 is directly connected to the gate electrode 115 . According to some embodiments of the present disclosure, the first thickness T1 of the first dielectric layer 121 surrounding the outer side of the first field plate 111 is very thin relative to the second thickness T2 of the second dielectric layer 121 surrounding the side of the second field plate 112, and the first field plate 111 is electrically connected to the gate electrode 115. This can help increase the charge accumulation in the junction field effect transistor (JFET) region 160, thereby significantly reducing the on-resistance (Ron). Furthermore, because the second thickness T2 of the second dielectric layer 121 is significantly thicker than the first thickness T1 of the first dielectric layer 121, and the second field plate 112 is electrically connected to the source electrode 134 and thus grounded, electron accumulation is prevented, effectively reducing the gate-to-drain capacitance (Cgd), thereby reducing the gate-to-drain charge (Qgd). Simultaneously, the gate-to-source capacitance (Cgd) is also reduced. Therefore, the disclosed embodiments can significantly improve switch loss and figure of merit (FOM), thereby enhancing the electrical performance of the semiconductor device.

Figures 2, 3, 4, 5, 6, 7, 8, 9, and 10 are schematic cross-sectional views illustrating certain stages of a method for fabricating a semiconductor device 100 according to an embodiment of the present disclosure. Referring to Figure 2, in step S101, a substrate 101 is first provided, comprising a drain region 103 and an epitaxial layer 102 epitaxially grown on the drain region 103. The substrate 101 has a first surface 101F and a second surface 101B opposite to each other. In one embodiment, the drain region 103 is, for example, a heavily N-type doped silicon carbide substrate, and the epitaxial layer 102 is, for example, a lightly N-type doped silicon carbide epitaxial layer. Continuing with FIG. 2 , in step S103 , trenches 105 are formed in the epitaxial layer 102 of the substrate 101 . In one embodiment, a hard mask layer is first deposited on the first surface 101F of the substrate 101. The hard mask layer is then patterned using photolithography and etching processes. The epitaxial layer 102 is then etched through the openings in the patterned hard mask to form the trenches 105. The patterned hard mask is then removed, and a sacrificial oxide layer may be formed within the trenches 105 . The sacrificial oxide layer is then removed to eliminate defects caused by the etching process used to form the trenches 105 .

Next, referring to FIG. 3 , in step S105 , a dielectric material layer 120 , such as silicon oxide, can be conformally formed within the trench 105 and on the first surface 101F of the substrate 101 using a thermal oxidation or deposition process. In one embodiment, the deposition process in step S105 can be a sub-atmospheric undoped silicon glass (SAUSG) deposition process using tetraethoxysilane (TEOS) and ozone (O ₃ ) as reaction precursors. A first semiconductor material layer 139 is then deposited on the first surface 101F of the substrate 101 using a deposition process to fill the trench 105 . During the deposition process, conductive dopants may be added to form a doped first semiconductor material layer, such as doped polysilicon. A chemical mechanical planarization (CMP) process is then used to remove the first semiconductor material layer on top of the dielectric material layer 120, leaving the top surface of the remaining first semiconductor material layer 139 flush with the top surface of the dielectric material layer 120. Continuing with FIG. 3 , in step S107 , an etch-back process is used to remove a portion of the first semiconductor material layer 139 to form an initial field plate 140. The top surface of the initial field plate 140 is substantially level with the first surface 101F of the substrate 101.

Then, referring to FIG. 4 , in step S109 , a deposition process is used to deposit dielectric material 125 on the initial field plate 140 . The dielectric material 125 has a surface that is slightly recessed relative to the top surface of the dielectric material layer 120 . The dielectric material 125 can protect the top surface of the initial field plate 140 during the subsequent etching process. In one embodiment, the dielectric material 125 is composed of silicon oxide, for example, and the deposition process in step S109 can be a low-pressure chemical vapor deposition (LPCVD) process using tetraethoxysilane (TEOS) as a reaction precursor. Continuing with FIG. 4 , in step S111, a wet etching process is used to remove a portion of the dielectric material layer 120 to form a second dielectric layer 122 within the trench 105, exposing the upper portion 140T of the initial field plate 140. The lower portion of the initial field plate 140 constitutes the second field plate 112, and the second dielectric layer 122 surrounds the side and bottom surfaces of the second field plate 112. Furthermore, openings 141 are formed within the trench 105, located on both sides of the upper portion 140T of the initial field plate 140.

Next, referring to FIG. 5 , in step S113, a thermal oxidation process is used to oxidize the exposed surfaces of both the epitaxial layer 102 of the substrate 101 and the upper portion 140T of the initial field plate 140. The upper portion 140T of the initial field plate 140 is oxidized to form a third dielectric layer 123, while the remaining unoxidized portion of the upper portion 140T of the initial field plate 140 forms the third field plate 113. The width of the third field plate 113 is smaller than that of the second field plate 112, and the third field plate 113 is connected to the second field plate 112. The third dielectric layer 123 surrounds the side surfaces and top surface of the third field plate 113. At the same time, the surface of the epitaxial layer 102 adjacent to the sidewalls of the trench 105 and exposed by the opening 141 is also oxidized to form a first dielectric layer 121. The surface of the epitaxial layer 102 located on the first surface 101F of the substrate 101 is also oxidized to form a gate dielectric layer 124. The gate dielectric layer 124 and the first dielectric layer 121 are connected and have the same first thickness T1.

In some embodiments, the epitaxial layer 102 is composed of, for example, silicon carbide (SiC) or silicon (Si), and the initial field plate 140 is composed of, for example, polysilicon. Since the oxidation rate of polysilicon is approximately 3 to 4 times that of silicon carbide (SiC), and the oxidation rate of polysilicon is approximately 2.5 to 3 times that of silicon (Si), the oxidation rate of the initial field plate 140 is higher than that of the epitaxial layer 102. As a result, the third thickness T3 of the third dielectric layer 123 formed by oxidation is greater than the first thickness T1 of the first dielectric layer 121. The third thickness T3 may be approximately 2.5 to 4 times the first thickness T1 of the first dielectric layer 121.

Referring to FIG. 6 , in step S115 , a deposition process is used to deposit a second semiconductor material layer 150 on the first surface 101F of the substrate 101 and fill the opening 141 within the trench 105 . Conductive dopants may be added during the deposition process to form a doped second semiconductor material layer, such as doped polysilicon. Second semiconductor material layer 150 filling the opening 141 forms a first field plate 111 , comprising a first portion 111 - 1 and a second portion 111 - 2 , respectively, located on either side of a third field plate 113 . A third dielectric layer 123 is disposed between the first field plate 111 and the third field plate 113 , with the third field plate 113 laterally separated from the first field plate 111 . Next, a chemical mechanical planarization (CMP) process can be used to planarize the top surface of the second semiconductor material layer 150. Continuing with FIG. 6 , in step S117 , a patterned photoresist 143 is formed on the second semiconductor material layer 150 as a mask, and then an etching process is performed to pattern the second semiconductor material layer 150 to form the gate electrode 115.

Referring to FIG. 7 , in step S119 , the patterned photoresist 143 is removed, and an ion implantation process is performed on the first surface 101F of the substrate 101 to form a well region 106 having the second conductivity type, such as a P-type well region, in the epitaxial layer 102. The well region 106 is located on both sides of the trench 105, and a portion of the well region 106 may extend laterally below the gate electrode 115. Next, another ion implantation process is performed using the gate electrode 115 as a mask to form a lightly doped source region 107 having the first conductivity type, such as a lightly doped N-type region, in the well region 106. Continuing with FIG. 7 , in step S121 , a rapid thermal annealing (RTA) process may be performed to activate the dopants in the well region 106 and the lightly doped source region 107 . Subsequently, a spacer material layer is deposited on the sidewalls and top surface of the gate electrode 115 . An anisotropic dry etching process is then performed on the spacer material layer to remove the spacer material layer on the top surface of the gate electrode 115 , thereby forming spacers 117 on the sidewalls of the gate electrode 115 .

Referring to FIG. 8 , in step S123, an ion implantation process is performed using spacers 117 as a mask to form a source region 108 of the first conductivity type, such as a heavily N-type doped region, within the well region 106 . The source region 108 is adjacent to the lightly doped source region 107 . Subsequently, in one embodiment, a patterned resist protection oxide (RPO) layer may be formed on the first surface 101F of the substrate 101, covering the region outside the gate electrode 115 to serve as a self-aligned silicide barrier layer. Then, a metal layer, such as cobalt, is deposited on the top surface of the gate electrode 115. A heat treatment is performed to allow the metal to react with the silicon in the gate electrode 115 to form a metal silicide layer 119 on the top surface of the gate electrode 115. The metal silicide layer 119 is composed of, for example, cobalt silicide (CoSix), which helps reduce the resistance of the gate electrode 115.

Then, referring to FIG. 9 , in step S125 , an interlayer dielectric layer 130 is formed entirely on the first surface 101F of the substrate 101 using a deposition process and a chemical mechanical planarization (CMP) process, covering the gate electrode 115 , the spacer 117 , the metal silicide layer 119 , the gate dielectric layer 124 , and the source region 108 . Continuing with FIG. 9 , in step S127 , a patterned photoresist and etching process are used to form a source contact hole 131 . The source contact hole 131 penetrates the interlayer dielectric layer 130 , the gate dielectric layer 124 , and the source region 108 , extending downward into the well region 106 . The bottom surface of the source contact hole 131 exposes the well region 106 , and the sidewalls of the source contact hole 131 expose the source region 108 .

Next, referring to FIG. 10 , in step S129 , an ion implantation process is performed through source contact hole 131 to form a doped region 109 in well region 106 directly below source contact hole 131 . Doped region 109 can serve as the bulk base region. Doped region 109 has the same conductivity type as well region 106 , and its doping concentration is higher than that of well region 106 . Doped region 109 is, for example, a heavily P-type doped region (P ⁺ ). Continuing with FIG. 10 , in step S131 , a conductive material, such as tungsten (W), copper (Cu), or other suitable metal, is filled into the source contact hole 131 to form a source contact 132. Furthermore, before filling the conductive material, a diffusion barrier layer may be formed longitudinally on the sidewalls and bottom surface of the source contact hole 131 to prevent the metal of the source contact 132 from diffusing outward. The diffusion barrier layer may be composed of, for example, titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), zirconium nitride (ZrN), or other suitable diffusion barrier materials. Then, a source electrode 134 is formed on the interlayer dielectric layer 130 and the source contact 132 using deposition, photolithography, and etching processes. The source electrode 134 is composed of, for example, aluminum copper (AlCu) or other suitable metal materials. The source electrode 134 is electrically connected to the source region 108 and the doped region 109 via the source contact 132. In addition, the second field plate 112 and the third field plate 113 can be electrically connected to the source electrode 134 via other vias and wiring layers. Thereafter, a drain electrode 136 is formed below the second surface 101B of the substrate 101 using a deposition process, directly contacting the drain region 103, thereby completing the semiconductor device 100 of FIG. 1 .

According to some embodiments of the present disclosure, a second dielectric layer with the largest thickness and a first dielectric layer with the smallest thickness can be formed in a trench below the gate electrode. The first dielectric layer surrounds the outer surface of a first field plate in the trench and is electrically connected to the gate electrode. This facilitates charge accumulation in the junction field-effect transistor (JFET) region, thereby significantly reducing the on-resistance (Ron). Furthermore, a second dielectric layer surrounds the second field plate in the trench and is electrically connected to the source electrode and grounded, thereby preventing electron accumulation and effectively reducing the gate-to-drain capacitance (Cgd), thereby reducing the gate-to-drain charge (Qgd). Therefore, the embodiments disclosed herein can significantly improve switch loss and figure of merit (FOM), thereby enhancing the electrical performance of semiconductor devices.

The above description is merely a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention should fall within the scope of the present invention.

100: Semiconductor devices

101: Base

101F: First Surface

101B: Second surface

102: Epitaxial layer

103: Drain area

105: Groove

106: Well Area

107: Source lightly doped region

108: Source Region

109: Mixed Area

111: First board

111-1: Part 1

111-2: Part 2

112: Second board

113: Third Board

115: Gate electrode

117: spacer

119: Metal silicide layer

121: First dielectric layer

122: Second dielectric layer

123: Third dielectric layer

124: Gate dielectric layer

130: Interlayer dielectric layer

132: Source Contact

134: Source electrode

136: Drain electrode

160: Junction Field Effect Transistor (JFET) Region

T1: First thickness

T2: Second thickness

T3: Third thickness

Claims (20)

A semiconductor device includes: a substrate; a trench disposed in the substrate; a first field plate disposed in the trench; a second field plate disposed in the trench, below the first field plate and laterally separated from the first field plate, wherein a bottom surface of the first field plate and a top surface of the second field plate are at the same level; a first dielectric layer disposed on a sidewall of the trench, surrounding an outer surface of the first field plate, and having a first thickness; a second dielectric layer disposed on the sidewall of the trench, surrounding a side surface and a bottom surface of the second field plate, and having a second thickness greater than the first thickness, wherein the first field plate is located directly above the second dielectric layer; and a gate electrode disposed on the substrate and connected to the first field plate. The semiconductor device of claim 1 further comprises: a third field plate disposed in the trench, connected to the second field plate, and laterally separated from the first field plate; and a third dielectric layer disposed in the trench, between an inner side surface of the first field plate and an outer side surface of the third field plate. The semiconductor device of claim 2, wherein the third dielectric layer has a third thickness that is greater than the first thickness and less than the second thickness. The semiconductor device of claim 2, wherein the first field plate includes a first portion and a second portion that are laterally separated and are located on both sides of the third field plate, respectively. The semiconductor device of claim 2, wherein the third dielectric layer surrounds the side surfaces and the top surface of the third field plate, and the third dielectric layer is located between the gate electrode and the third field plate. The semiconductor device of claim 2, wherein the third field plate is located directly above the second field plate, and a width of the third field plate is smaller than a width of the second field plate. The semiconductor device of claim 1, wherein the first field plate and the second field plate do not overlap in a vertical projection direction. The semiconductor device as described in claim 1 further includes: a source region disposed on a first surface of the substrate and laterally separated from the gate electrode; a drain region disposed on a second surface of the substrate; a source electrode disposed above the first surface of the substrate and electrically connected to the source region; and a drain electrode disposed below the second surface of the substrate and directly contacting the drain region, wherein the second field plate is electrically connected to the source electrode. The semiconductor device of claim 1 further comprises a metal silicide layer disposed on a top surface of the gate electrode. The semiconductor device as described in claim 1 further includes a gate dielectric layer disposed between the gate electrode and the substrate, the gate dielectric layer being connected to the first dielectric layer and having the first thickness. A method for manufacturing a semiconductor device includes: providing a substrate; forming a trench in the substrate; forming a first field plate in the trench; forming a second field plate in the trench, located below and laterally separated from the first field plate, wherein a bottom surface of the first field plate and a top surface of the second field plate are at the same level; forming a first dielectric layer on a sidewall of the trench, surrounding an outer surface of the first field plate, and having a first thickness; forming a second dielectric layer on the sidewall of the trench, surrounding a side surface and a bottom surface of the second field plate, and having a second thickness greater than the first thickness, wherein the first field plate is formed directly above the second dielectric layer; and forming a gate electrode on the substrate, connected to the first field plate. The method for manufacturing a semiconductor device as described in claim 11 further includes: forming a third field plate in the trench, connected to the second field plate and laterally separated from the first field plate; and forming a third dielectric layer in the trench, between the first field plate and the third field plate. A method for manufacturing a semiconductor device as described in claim 12, wherein forming the second field plate and the second dielectric layer includes: forming a dielectric material layer longitudinally in the trench; depositing a first semiconductor material layer to fill the trench to form an initial field plate; and removing a portion of the dielectric material layer to form the second dielectric layer and expose an upper portion of the initial field plate, wherein a lower portion of the initial field plate forms the second field plate and is surrounded by the second dielectric layer. A method for manufacturing a semiconductor device as described in claim 13, wherein forming the first dielectric layer, the third field plate and the third dielectric layer includes: performing an oxidation process on the substrate and the upper portion of the initial field plate, wherein the upper portion of the initial field plate is oxidized to form the third dielectric layer, a remaining portion of the upper portion of the initial field plate forms the third field plate, the width of the third field plate is less than the width of the second field plate, the third dielectric layer surrounds the third field plate, and a portion of the substrate adjacent to the trench is oxidized to form the first dielectric layer. A method for manufacturing a semiconductor device as described in claim 14, wherein the surface of the substrate is oxidized to form a gate dielectric layer, the gate dielectric layer is connected to the first dielectric layer and has the first thickness. The method for manufacturing a semiconductor device as described in claim 14, wherein the oxidation rate of the initial field plate is higher than the oxidation rate of the substrate, and the third dielectric layer has a third thickness greater than the first thickness. A method for manufacturing a semiconductor device as described in claim 14, wherein forming the first field plate and the gate electrode includes: depositing a second semiconductor material layer on the substrate and filling the trench, wherein the second semiconductor material layer in the trench forms the first field plate, and the first field plate includes a first portion and a second portion, respectively located on both sides of the third field plate; and patterning the second semiconductor material layer on the substrate to form the gate electrode. The method for manufacturing a semiconductor device as described in claim 11 further includes forming a metal silicide layer on the top surface of the gate electrode. The method for manufacturing a semiconductor device as described in claim 11 further includes: forming a source region on a first surface of the substrate, and the source region is laterally separated from the gate electrode; forming a drain region on a second surface of the substrate; forming a source electrode above the first surface of the substrate and electrically connected to the source region; and forming a drain electrode below the second surface of the substrate and directly contacting the drain region, wherein the second field plate is electrically connected to the source electrode. The method for manufacturing a semiconductor device as described in claim 19 further includes: forming a well region on the first surface of the substrate, the well region having a conductivity type opposite to that of the source region; forming a lightly doped source region in the well region using the gate electrode as a mask; forming a spacer on a sidewall of the gate electrode; forming the source region in the well region using the spacer as a mask; forming an interlayer dielectric layer covering the gate electrode; forming a source contact hole passing through the interlayer dielectric layer and the source region and extending downward into the well region; forming a doped region directly below the source contact hole, having the same conductivity type as the well region; and A conductive material is filled in the source contact hole to form a source contact, electrically connecting the source electrode and the source region.