TWI897291B - Semiconductor device and methods of formation - Google Patents

Abstract

A multiple-layer hydrogen barrier stack may be included between a non-volatile memory structure and conductive structures in an interconnect structure in a semiconductor device. The multiple-layer hydrogen barrier stack may minimize and/or prevent hydrogen diffusion into one or more layers of the non-volatile memory structure such as a metal-oxide channel of the non-volatile memory structure. The multiple-layer hydrogen barrier stack may include a hydrogen absorption layer and a hydrogen blocking layer on the hydrogen absorption layer. The hydrogen blocking layer blocks or resists diffusion of hydrogen through the conductive structures into the non-volatile memory structure. The hydrogen absorption layer may absorb any hydrogen atoms that might diffuse through the hydrogen blocking layer.

Description

Semiconductor device and method of forming the same

Embodiments of the present invention relate to a ferroelectric non-volatile memory and a method for forming the same.

A ferroelectric random access memory (FeRAM) cell is a type of random access memory cell that utilizes a ferroelectric field-effect transistor (FeFET) including a ferroelectric (FE) layer to selectively store information based on the polarization of the ferroelectric layer. For example, a first voltage can be applied to the gate structure of the FeFET to polarize the ferroelectric layer in a first polarization configuration corresponding to the programmed state of the FeRAM cell, and a second voltage can be applied to the gate structure to polarize the ferroelectric layer in a second polarization configuration corresponding to the erased state of the FeRAM cell.

Embodiments of the present invention provide a semiconductor device. The semiconductor device includes an interconnect structure located above a substrate of the semiconductor device, the interconnect structure comprising a plurality of dielectric layers and a plurality of conductive structures within the plurality of dielectric layers. The semiconductor device includes a non-volatile memory structure located within a dielectric layer within the plurality of dielectric layers of the interconnect structure, wherein the non-volatile memory structure includes a metal oxide channel layer and is electrically coupled to at least one of the plurality of conductive structures. The semiconductor device also includes a hydrogen barrier layer located between the non-volatile memory structure and the at least one conductive structure.

An embodiment of the present invention provides a method. The method includes forming a bottom gate of a non-volatile memory structure. The method includes forming a ferroelectric layer of the non-volatile memory structure above the bottom gate. The method includes forming a metal oxide channel layer of the non-volatile memory structure above the ferroelectric layer. The method includes forming a dielectric layer above the metal oxide channel layer. The method includes forming a source/drain of the non-volatile memory structure at least near or above the metal oxide channel layer. The method includes forming a hydrogen absorption layer on the source/drain. The method includes forming a hydrogen blocking layer on the hydrogen absorption layer. The method includes forming a conductive structure on the hydrogen blocking layer.

An embodiment of the present invention provides a method. The method includes forming a first portion of an interconnect structure of a semiconductor device over a substrate. The method includes forming a non-volatile memory structure over the first portion of the interconnect structure. The method includes forming a second portion of the interconnect structure over the first portion of the interconnect structure and over the non-volatile memory structure. Forming the second portion of the interconnect structure includes forming one or more dielectric layers over the first portion of the interconnect structure. A recess is formed in the one or more dielectric layers of the interconnect structure, wherein a first conductive structure in the first portion of the interconnect structure is exposed through the recess. A hydrogen barrier layer is formed over the first conductive structure in the recess. A second conductive structure is formed over the hydrogen barrier layer in the recess.

100: Example Environment/Semiconductor Processing Tools

102: Deposition Tools/Semiconductor Processing Tools

104: Exposure Tools/Semiconductor Processing Tools

106: Development Tools/Semiconductor Processing Tools

108: Etching Tools/Semiconductor Processing Tools

110: Planarization Tools/Semiconductor Processing Tools

112: Plating Tools/Semiconductor Processing Tools

114: Wafer/Die Transfer Tools/Semiconductor Processing Tools

200, 208: Semiconductor devices

202: Device layer

204: Internal connection structure

206: Base

210: Dielectric layer

212: Interlayer dielectric layer

214: Etch stop layer

216:Conductive structure

218: Connection structure

220: Non-volatile memory structure

222: Hydrogen barrier layer

222a: Hydrogen absorption layer

222b: Hydrogen barrier layer

300, 400, 500, 600, 608, 612, 616, 618, 620, 800, 900, 920, 1000: Example embodiments

302: Bottom Gate

304: Interface layer

306: Seed layer

308: Ferroelectric Layer

310: Barrier layer

312: Metal oxide channel layer

314, 316: Source/Drain

402: Gap Wall

602, 604, 606: Titanium nitride layer

610: Titanium layer

614: Ruthenium layer

700, 706, 708: Examples

702: Hydrogen concentration

704: Depth

802, 1002, 1004, 1006, 1008, 1010: Depression

902: Time

904: ALD Cycle

906: Oxygen-containing gas

908: First Metal Material Precursor

910: Second metal material front driver

912: Semiconductor material precursors

914a, 914b, 914c, 914d, 916a, 916b, 916c, 916d: Metal oxide part

918, 918a, 918b: Oxide semiconductor part

922: ALD Super Cycle

924a, 924b: First metal material precursor cycle

926a, 926b: Second metal material precursor cycle

928: Semiconductor Material Precursor Cycle

1100: Device

1110: Bus

1120: Processor

1130: Memory

1140: Input component

1150: Output component

1160: Communication Components

1200, 1300: Process

1210, 1220, 1230, 1240, 1250, 1260, 1270, 1280, 1310, 1320, 1330: Blocks

D1, D10, D2, D3, D4, D5, D6, D7, D8, D9: Dimensions

X, Z: Direction

Various aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

Figure 1 is a diagram of an example environment in which the systems and/or methods described herein may be implemented.

Figure 2 is a diagram of an example semiconductor device described herein.

Figure 3 is a diagram of an example embodiment of a non-volatile memory structure as described herein.

Figure 4 is a diagram of an example embodiment of a non-volatile memory structure as described herein.

Figure 5 is a diagram of an example embodiment of a hydrogen barrier layer as described herein.

Figures 6A to 6F are diagrams of example embodiments of the hydrogen barrier layer described herein.

7A to 7C are graphs of exemplary hydrogen concentrations in a semiconductor device in accordance with the exemplary embodiment of the hydrogen barrier layer shown and described in conjunction with FIG. 6A to 6F .

Figures 8A to 8K are diagrams of example embodiments of forming the semiconductor devices described herein.

Figures 9A and 9B are diagrams of example embodiments of a hydrogen absorbing layer that forms the hydrogen barrier layer described herein.

Figures 10A to 10N are diagrams of example embodiments of forming the non-volatile memory structure described herein.

Figure 11 is a diagram of example components of the apparatus described herein.

Figure 12 is a flow chart of an example process associated with forming the non-volatile memory structure described herein.

FIG13 is a flow chart of an example process associated with forming the semiconductor devices described herein.

The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature being formed on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing the first and second features from directly contacting each other. Furthermore, this disclosure may reuse reference numbers and/or letters throughout the various examples. This repetition is for the sake of brevity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar terms may be used herein to describe the relationship of one element or feature to another element or feature as depicted in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Unless expressly stated otherwise, each element having the same reference number is assumed to be of the same material composition and have a thickness within the same thickness range.

In some cases, a ferroelectric random access memory (FeRAM) structure may include a metal oxide channel layer (e.g., a channel layer comprising a metal oxide material or a metal oxide semiconductor material such as indium gallium zinc oxide (IGZO)) above a ferroelectric layer, and a plurality of source/drain electrodes adjacent to the metal oxide channel layer. The use of a metal oxide channel layer may enable reduced current leakage in the FeRAM structure compared to elemental semiconductor channels, III-V semiconductor channels, or II-VI semiconductor channels.

However, metal oxide materials are highly susceptible to hydrogen contamination. If hydrogen diffuses into the metal oxide channel of the FeRAM structure, it can increase the carrier concentration in the metal oxide channel. Due to the low zinc-oxygen (ZO) bond dissociation energy of the metal oxide material in the metal oxide channel, the charge carrier concentration can increase. In particular, due to the low ZO bond dissociation energy, the bonds between zinc (Zn) and oxygen (O) in the metal oxide material are easily broken, resulting in zinc with oxygen vacancies (Zn-VO). The free oxygen that bonds with the diffused hydrogen forms water ( _H2O ) in the metal oxide channel. Water and zinc oxide can promote charge retention in the metal oxide channel, leading to an increase in carrier concentration. Among other things, increased carrier concentration can lead to increased off-state current leakage, increased positive bias temperature instability (PBTI), and/or increased negative bias temperature instability (NBTI) in the FeRAM structure. Additionally and/or alternatively, hydrogen contamination in the metal oxide semiconductor channel can increase the charge carrier concentration to the point where the FeRAM structure becomes stuck in a normally-on configuration, rendering the FeRAM structure inoperable.

In some implementations described herein, an FeRAM structure is included in an interconnect structure of a semiconductor device. A multi-layer hydrogen barrier stack is included between the FeRAM structure and a conductive structure within the interconnect structure, to which the source/drain of the FeRAM structure is connected. The multi-layer hydrogen barrier stack can minimize and/or prevent hydrogen diffusion into one or more layers of the FeRAM structure, such as a metal oxide channel within the FeRAM structure. The multi-layer hydrogen barrier stack can include a hydrogen absorbing layer and a hydrogen blocking layer disposed above the hydrogen absorbing layer. The hydrogen blocking layer blocks or prevents hydrogen from diffusing into the FeRAM structure via the conductive structure. The hydrogen absorbing layer absorbs any hydrogen atoms that may diffuse through the hydrogen barrier layer.

In this manner, the combination of the hydrogen absorber and hydrogen barrier layers minimizes and/or prevents hydrogen diffusion into one or more layers of the FeRAM structure, such as the metal oxide channel of the FeRAM structure. This can reduce the likelihood of charge carrier concentration in the metal oxide channel of the FeRAM structure, which enables the FeRAM structure to achieve low PBTI and/or low NBTI. Additionally and/or alternatively, the combination of the hydrogen absorber and hydrogen barrier layers can enable the FeRAM structure to achieve low off-state current leakage and/or reduce the likelihood of the FeRAM structure becoming inoperable due to carrier concentration.

FIG1 is a diagram of an example environment 100 in which the systems and/or methods described herein may be implemented. As shown in FIG1 , the example environment 100 may include a plurality of semiconductor processing tools 102-112 and a wafer/die transport tool 114. The plurality of semiconductor processing tools 102-112 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, and/or another type of semiconductor processing tool. The tools included in the example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and/or a fabrication facility, among other examples.

Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 comprises a spin-on tool capable of depositing a photoresist layer on a substrate, such as a wafer. In some embodiments, deposition tool 102 comprises a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric pressure CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, deposition tool 102 comprises a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, deposition tool 102 comprises an epitaxial tool configured to form device layers and/or regions by epitaxial growth. In some embodiments, example environment 100 comprises multiple types of deposition tools 102.

Sputtering (or sputtering) is a PVD technique that includes one or more techniques for depositing a material (such as a metal, dielectric, or another type of material) onto a substrate or wafer. For example, a sputtering process may involve placing a substrate on an anode in a processing chamber, where a gas (such as argon or another chemically inert gas) is supplied and ignited to form a plasma of gas ions. Ions in the plasma are accelerated from the cathode to a sputtering target, causing the ions to strike the target and release particles of the deposited material. The anode attracts the particles, causing them to migrate toward the wafer and deposit onto it.

ALD is a deposition technique used in semiconductor manufacturing to form conformal thin films with atomically controlled thickness. An ALD operation involves the use of a series of vapor-phase precursors (or reactants), each of which reacts independently with a material surface in a self-limiting manner. A first vapor-phase precursor is introduced into a process chamber to react with the material surface. The first vapor-phase precursor is then removed from the process chamber, and a second vapor-phase precursor is introduced to react with the material surface, and so on. This alternating process is repeated to grow or otherwise form a thin film on the surface in a highly controlled manner. Additional vapor-phase precursors can be included in the ALD operation to deposit different atomic layers of the material.

Exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., a deep ultraviolet (EUV) source, an extreme ultraviolet (EUV) source, and/or similar UV sources), an X-ray source, an electron beam (e-beam) source, and/or the like. Exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. This pattern can include a pattern for forming one or more structures of a semiconductor device, a pattern for etching various portions of the semiconductor device, and so on. In some implementations, exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

Development tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source, thereby developing the pattern transferred from exposure tool 104 to the photoresist layer. In some exemplary embodiments, development tool 106 develops the photoresist layer by removing unexposed portions of the photoresist layer to form a pattern. In some exemplary embodiments, development tool 106 forms a pattern by removing exposed portions of the photoresist layer. In some exemplary embodiments, development tool 106 forms a pattern by using a chemical developer to dissolve exposed or unexposed portions of the photoresist layer.

The etch tool 108 is a semiconductor processing tool capable of etching various types of materials, such as substrates, wafers, or semiconductor devices. For example, the etch tool 108 may include a wet etch tool, a dry etch tool, or the like. In some embodiments, the etch tool 108 includes a chamber filled with an etchant, in which a substrate is placed for a specific amount of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etch tool 108 may use plasma etching or plasma-assisted etching to etch the one or more portions of the substrate, which may involve using an ionized gas to etch the one or more portions isotropically or directionally.

Planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing layers of a wafer or semiconductor device. For example, planarization tool 110 may include a chemical mechanical planarization (CMP) tool and/or another type of planarization tool that polishes or planarizes layers or surfaces of deposited or plated materials. Planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free-abrasive polishing) to polish or planarize the surface of a semiconductor device. Planarization tool 110 may utilize an abrasive and corrosive chemical slurry in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and semiconductor device may be pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head can rotate along different axes of rotation to remove material and smooth out any irregular topography on the semiconductor device, thereby making the semiconductor device flat or planar.

The plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., a wafer, a semiconductor device, etc.) or a portion thereof with one or more metals. For example, the plating tool 112 may include a copper plating tool, an aluminum plating tool, a nickel plating tool, a tin plating tool, a compound material or alloy (e.g., tin-silver, tin-lead, etc.) plating tool, and/or a plating tool for one or more other types of conductive materials, metals, and/or similar types of materials.

The wafer/die transport tool 114 includes a mobile robot, a robotic arm, a trolley or rail car, an overhead crane transport (OHT) system, an automated material handling system (AMHS), and/or is configured to transport substrates and/or semiconductor devices between semiconductor processing tools 102-112, to transport substrates and/or semiconductor devices between processing chambers of the same semiconductor processing tool, and/or to and from other locations, such as wafer racks, storage rooms, etc. In some embodiments, the wafer/die transport tool 114 can be a programmed device configured to travel a specific path and/or can operate semi-autonomously or autonomously. In some embodiments, the example environment 100 includes multiple wafer/die transport tools 114.

For example, the wafer/die transport tool 114 may be included in a cluster tool or another type of tool including multiple processing chambers and may be configured to transfer substrates and/or semiconductor devices between the multiple processing chambers, between a processing chamber and a buffer zone, between a processing chamber and an interface tool such as an equipment front-end module (EFEM), and/or between a processing chamber and a transport carrier (e.g., a front-opening uniform pod (FOUP)). In some embodiments, the wafer/die transport tool 114 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-clean process chamber (e.g., for cleaning or removing oxides, oxidation, and/or deposits). Deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations). In these embodiments, the wafer/die transport tool 114 is configured to transfer substrates and/or semiconductor devices between process chambers of the deposition tool 102 without disrupting or removing the vacuum (or at least partial vacuum) of the process chambers and/or during processing operations in the deposition tool 102, as described herein.

In some embodiments, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may be used to perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may be used to form a bottom gate of a non-volatile memory structure; form a ferroelectric layer of the non-volatile memory structure above the bottom gate; form a metal oxide channel layer of the non-volatile memory structure above the ferroelectric layer; ; forming a dielectric layer above the metal oxide channel layer; forming at least one of the source/drain of the non-volatile memory structure adjacent to or located above the metal oxide channel layer; forming a hydrogen absorption layer on the source/drain; forming a hydrogen barrier layer on the hydrogen absorption layer; and/or forming a conductive structure on the hydrogen barrier layer, etc.

As another example, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may be used to form a first portion of an interconnect structure of a semiconductor device over a substrate; the first portion of the interconnect structure forms a non-volatile memory structure; and/or a second portion of the interconnect structure is formed over the first portion of the interconnect structure and over the non-volatile memory structure, wherein forming the second portion of the interconnect structure includes: forming one or more dielectric layers over the first portion of the interconnect structure; forming recesses in the one or more dielectric layers, wherein a first conductive structure in the first portion of the interconnect structure is exposed through the recesses; forming a hydrogen barrier layer over the first conductive structure in the recesses; and/or forming a second conductive structure over the hydrogen barrier layer in the recesses, etc.

In some embodiments, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may be used to perform one or more semiconductor processing operations described in conjunction with FIG. 8A to FIG. 8K , FIG. 9A , FIG. 9B , FIG. 10A to FIG. 10N , FIG. 12 , and/or FIG. 13 .

The number and arrangement of devices shown in FIG1 are provided as one or more examples. In practice, there may be more devices, fewer devices, different devices, or devices arranged differently than shown in FIG1 . Furthermore, two or more devices shown in FIG1 may be on a single device, or a single device may be implemented as multiple distributed devices as shown in FIG1 . Additionally or alternatively, one group of devices (e.g., one or more devices) of example environment 100 may perform one or more functions described as being performed by another group of devices in example environment 100.

FIG2 is a diagram of an example semiconductor device 200 described herein. Semiconductor device 200 may include a system-on-chip (SoC) device, a logic device such as a central processing unit (CPU) or a graphics processing unit (GPU), a memory device (e.g., a high-bandwidth memory (HBM) device), and/or another type of semiconductor device.

As shown in FIG. 2 , semiconductor device 200 may include a device layer 202 and an interconnect structure 204 located above device layer 202 in the z-direction within semiconductor device 200 . Device layer 202 includes a substrate 206 . Substrate 206 may correspond to a portion of a semiconductor wafer on which semiconductor device 200 is formed. Substrate 206 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or another type of semiconductor substrate. Substrate 206 may extend in the x-direction and/or the y-direction within semiconductor device 200 .

Semiconductor devices 208 may be included in and/or on substrate 206 in device layer 202 of semiconductor device 200. Semiconductor devices 208 include transistors (e.g., planar transistors, fin field-effect transistors (finFETs), gate-all-around (GAA) transistors), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, and/or other types of semiconductor devices.

A dielectric layer 210 is included over substrate 206. Dielectric layer 210 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and/or another type of dielectric layer. Dielectric layer 210 includes a dielectric material that enables portions of substrate 206 and/or semiconductor device 208 to be selectively etched or prevented from being etched, and/or electrically isolates semiconductor device 208 from device layer 202. Dielectric layer 210 includes silicon nitride (SixNy), an oxide (e.g., silicon oxide (SiOx) and/or another oxide material), and/or another type of dielectric material. Dielectric layer 210 may extend in the x-direction and/or the y-direction within semiconductor device 200.

The interconnect structure 204 of the semiconductor device 200 is included above a substrate 206 of the semiconductor device 200 and above a semiconductor device 208 in the z-direction. The interconnect structure 204 includes a plurality of dielectric layers arranged in a direction approximately perpendicular to the substrate 206 (e.g., in the z-direction). The dielectric layers may include interlayer dielectric layers 212 and electrolytic layer slits 214 arranged in an alternating pattern. The ILD layers 212 and the electrolytic layer slits 214 may extend in the x-direction and/or the y-direction within the semiconductor device 200.

The ILD layers 212 may each include an oxide (e.g., silicon oxide (SiOx) and/or another oxide material), undoped silicate glass (USG), borosilicate glass (BSG), fluorosilicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogenated silsesquioxane (HSQ), and/or other suitable dielectric materials. In some embodiments, the ILD layers 212 include an extremely low-k dielectric material (ELK) having a dielectric constant less than approximately 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiOx), amorphous fluorinated carbon (a-CxFy), parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbon (SiOC) polymer, porous hydrosilsesquioxane (HSQ), porous methylsilsesquioxane (MSQ), porous polyarylene ether (PAE), and/or porous silicon oxide (SiOx).

The ESL 214 can each include silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and/or another suitable dielectric material. In some embodiments, the ILD layer 212 and the ESL 214 include different dielectric materials to provide etch selectivity, enabling the formation of various structures in the interconnect structure 204.

The interconnect structure 204 includes a plurality of conductive structures 216. The conductive structures 216 are electrically and/or physically coupled to one or more semiconductor devices 208 in the device layer 202 and/or in the interconnect structure 204. The conductive structures 216 correspond to circuits capable of providing signals and/or power to and from the semiconductor devices 208. The conductive structures 216 may include vias, trenches, contacts, plugs, interconnects, metallization layers, conductive traces, and/or other types of conductive structures. Conductive structure 216 may be one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and/or combinations thereof, as well as other examples of conductive materials. In some exemplary embodiments, one or more liner layers are included between conductive structure 216 and ILD layer 212 and/or between conductive structure 216 and ESL 214. The one or more liner layers may include a blocking liner, a barrier liner, and/or other types of liner layers. Examples of materials for the one or more liner layers include tantalum nitride (TaN) and/or titanium nitride (TiN), among others.

In some embodiments, the conductive structures 216 of the interconnect structure 204 can be arranged vertically (e.g., along the z-direction). In other words, multiple stacked conductive structures 216 extend between the device layer 202 and the connection structure 218 above the interconnect structure 204 to facilitate routing of electrical signals and/or power between the device layer 202 and the connection structure 218. Multiple layers of stacked conductive structures 216 can be referred to as M layers. For example, a metal 0 (M0) layer can be located at the bottom of the interconnect structure 204 and can be directly coupled to the device layer 202 (e.g., coupled to contacts or interconnects of semiconductor devices 208 in the device layer 202), a metal 1 (M1) layer can be located above the M0 layer in the interconnect structure 204, a metal 2 (M2) layer can be located above the M1 layer, and so on. In some embodiments, the interconnect structure 204 includes nine (9) stacked conductive structures 216 (e.g., M0-M8). In some embodiments, the interconnect structure 204 includes another number of stacked conductive structures 216.

Connection structures 218 include solder balls, solder bumps, contact pads (e.g., land grid array (LGA) pads), contact pins (e.g., pin grid array (PGA) pins), under-bump metallization (UBM) connectors, microbumps, ball grid array (BGA), controlled collapse die connect (C4) bumps, and/or other types of connection structures. Connection structures 218 enable semiconductor device 200 to be connected to a semiconductor device package substrate (e.g., an interposer, a redistribution wiring layer (RDL) structure, a printed circuit board (PCB)) and/or attached to another semiconductor device.

The interconnect structure 204 of the semiconductor device 200 further includes one or more semiconductor devices. For example, the ILD layer 212 of the interconnect structure 204 includes a non-volatile memory structure 220. In other examples, the interconnect structure 204 includes a resistor, a capacitor, a radio frequency (RF) switch, an optical modulator, a waveguide, and/or another type of semiconductor device. The non-volatile memory structure 220 is electrically and/or physically coupled to one or more conductive structures 216 in the interconnect structure 204.

In some embodiments, the non-volatile memory structure 220 includes an FeRAM structure and/or another type of non-volatile memory structure including a ferroelectric field effect transistor (FeFET). The FeRAM structure (or non-volatile memory structure including a FeFET) includes a metal oxide channel layer. In some embodiments, non-volatile memory structure 220 includes a non-volatile memory structure including a thin film transistor (TFT), a dynamic random access memory (DRAM) structure, a metal-ferroelectric-metal (MFM) memory structure, a metal-ferroelectric-metal-insulator (MFMI) memory structure, and/or another type of memory structure including a metal-oxide channel layer.

As further shown in FIG. 2 , the interconnect structure 204 of the semiconductor device 200 includes one or more hydrogen barrier layers 222. The hydrogen barrier layer 222 minimizes and/or prevents hydrogen from diffusing into the non-volatile memory structure 220. In some embodiments, the hydrogen barrier layer 222 is included between vertically adjacent conductive structures 216 in the interconnect structure 204 (e.g., adjacent in the z-direction within the semiconductor device 200). In some embodiments, the hydrogen barrier layer 222 is included between the conductive structure 216 and the non-volatile memory structure 220.

A hydrogen barrier layer 222 may be included above the non-volatile memory structure 220 (e.g., the hydrogen barrier layer 222 is located at a greater z-direction height within the semiconductor device 200 than the non-volatile memory structure 220). Hydrogen diffusion may occur during and/or as a result of one or more semiconductor processing operations performed after forming the non-volatile memory structure 220. For example, hydrogen may diffuse from one or more ILD layers 212 and/or ESL 214 formed above the non-volatile memory structure 220 into the conductive structure 216. As another example, after forming the non-volatile memory structure 220 and/or forming one or more layers over the non-volatile memory structure, a high pressure anneal (or another type of annealing operation) may be performed on the semiconductor device 200. The high pressure anneal may involve the use of a hydrogen process gas, and hydrogen from the hydrogen process gas may diffuse through the conductive structure 216. Including the hydrogen barrier layer 222 on the non-volatile memory structure 220 enables the hydrogen barrier layer 222 to minimize and/or prevent hydrogen from diffusing downwardly through the conductive structure 216 into the non-volatile memory structure 220 , which may otherwise be generated by these subsequent semiconductor processing operations.

The hydrogen barrier layer 222 may include a multi-layer stack comprising multiple layers. For example, the hydrogen barrier layer 222 may include a hydrogen absorbing layer 222a and a hydrogen barrier layer 222b on and/or above the hydrogen absorbing layer 222a. In some embodiments, the hydrogen barrier layer 222 includes only the hydrogen absorbing layer 222a or only the hydrogen barrier layer 222b.

The hydrogen barrier layer 222b includes one or more materials that prevent hydrogen from diffusing into and through the hydrogen barrier layer 222b, thereby resisting hydrogen diffusion. Examples of such hydrogen barrier materials include various types of hydrogen-blocking metal-containing materials and/or hydrogen-blocking conductive metal nitrides and/or hydrogen-blocking dielectrics. Examples of hydrogen-blocking metals that can be used in the hydrogen barrier layer 222b include ruthenium (Ru), silver (Ag), aluminum (Al), titanium (Ti), gold (Au), platinum (Pt), cobalt (Co), iron (Fe), tin (Sn), and/or nickel (Ni). Examples of hydrogen-blocking conductive metal nitrides include titanium nitride (TiN), etc. Examples of _hydrogen -blocking dielectrics include aluminum oxide (AlxOy such as _Al2O3 ), silicon nitride (SixNy such as _Si3N4 ), titanium oxide (TiOx such as _TiO2 ), and/or _titanium carbide (TiC).

The hydrogen-absorbing layer 222a includes one or more materials that resist the diffusion of hydrogen by absorbing it before it can pass through the hydrogen-absorbing layer 222a. Consequently, hydrogen that passes through the hydrogen-barrier layer 222b above the hydrogen-absorbing layer 222a can be absorbed by the hydrogen-absorbing layer 222a, thereby minimizing and/or preventing hydrogen from passing through both the hydrogen-barrier layer 222b and the hydrogen-absorbing layer 222a. Examples of hydrogen-absorbing materials that can be used for the hydrogen-absorbing layer 222a include one or more materials with a high propensity to absorb hydrogen. For example, the hydrogen-absorbing layer 222a can include one or more metal oxide-containing materials and/or one or more metal oxide semiconductor materials that readily absorb hydrogen. Therefore, the metal oxide material and/or metal oxide semiconductor material of the hydrogen absorption layer 222a can absorb hydrogen before the hydrogen diffuses into the oxide material and/or metal oxide semiconductor material of the channel layer of the non-volatile memory structure 220 and is absorbed by the metal. Examples of the metal oxide material and/or metal oxide semiconductor material that can be included in the hydrogen absorption layer 222a include conductive metal oxide materials and/or conductive metal oxide semiconductor materials containing one or more metals, such as titanium (Ti), zirconium (Zr), vanadium (V), copper (Cu), tungsten (W), thorium (Th), tin (Sn), indium (In), zinc (Zn), and/or palladium (Pd). For example, the hydrogen absorption layer 222a may include highly nitrided indium gallium zinc oxide (InGaZnO or IGZO), indium gallium oxide (InGaO or IGO), indium zinc oxide (InZnO or IZO), indium oxide (InO), zinc tin oxide (InGaZnO or IGZO). Other examples include zinc tin oxide (ZnSnO or ZSO), gallium zinc oxide (GaZnO or GZO), indium tin oxide (InSnO or ISO), and/or zinc oxide (ZnO).

As described above, Figure 2 is provided as an example. Other examples may differ from what is described with respect to Figure 2.

FIG3 is a diagram of an example embodiment 300 of a non-volatile memory structure 220 as described herein. As described herein, one or more hydrogen barrier layers 222 are included between the non-volatile memory structure 220 and one or more conductive structures 216 in the interconnect structure 204 of the semiconductor device 200. Including the hydrogen barrier layer 222 above the non-volatile memory structure 220 can minimize and/or prevent hydrogen from diffusing downwardly through the conductive structure 216 into the non-volatile memory structure 220.

As shown in FIG3 , a nonvolatile memory structure 220 may be included in an ILD layer 212 of an interconnect structure 204 of a semiconductor device 200. The nonvolatile memory structure 220 may include a bottom gate 302. Bottom gate 302 may also be referred to as a buried electrode and may be a gate structure of the nonvolatile memory structure 220. Bottom gate 302 may be electrically coupled to a word line of a nonvolatile memory array included in the nonvolatile memory structure 220. Bottom gate 302 may include one or more conductive metal materials having a relatively low coefficient of thermal expansion (CTE). Examples of such conductive metal-containing materials include platinum (Pt), titanium (Ti), titanium nitride (TiN), tungsten (Ta), tungsten nitride (TaN), tungsten (W), iron (Fe), nickel (Ni), cobalt (Co), chromium (Cr), curium (Be), antimony (Sb), iridium (Ir), molybdenum (Mo), benzene (Os), thorium (Th), vanadium (V), and/or their alloys.

Non-volatile memory structure 220 may include an interface layer 304 on and/or over bottom gate 302. Interface layer 304 may include an oxide-containing material configured to reduce stress induction in non-volatile memory structure 220. Examples of oxide-containing materials for the interface layer 304 include tantalum pentoxide (Ta ₂ O ₅ ), potassium oxide (K ₂ O), riboside oxide (Rb ₂ O), strontium oxide (SrO), barium oxide (BaO), zirconium oxide (ZrO or ZrO ₂ ), yttrium oxide (Y ₂ O ₃ ), yttrium oxide (HfO ₂ ), yttrium silicon dioxide (HfSiO ₂ ), amorphous vanadium oxide (α-V ₂ O ₃ ), amorphous chromium oxide (α-Cr ₂ O ₃ ), amorphous gallium oxide (α-Ga ₂ O ₃ ), amorphous iron oxide (α-Fe ₂ O ₃ ), amorphous titanium oxide (α-Ti ₂ O ₃ ), amorphous indium oxide (α-In ₂ O _{3 )} , and the like. ), yttrium aluminum garnet (YAlO ₃ or YAP), bismuth oxide (Bi ₂ O ₃ ), yttrium oxide (Yb ₂ O ₃ ), daphnia oxide (Dy ₂ O ₃ ), gadolinium oxide (Gd ₂ O ₃ ), strontium titanium oxide (SrTiO ₃ ), daphnia oxide (DyScO ₃ ), tantalum plutonium oxide (TbScO ₃ ), gadolinium plutonium oxide (GdScO ₃ ), plutonium neodymium oxide (NdScO ₃ ), neodymium gallium oxide (NdGaO ₃ ), and/or strontium tantalum aluminate (LaSrAlTaO ₃ or LSAT), etc. In some embodiments, interface layer 304 comprises a bilayer epitaxial structure comprising lumen strontium manganese oxide ( _LaSrMnO3 or LSMO) and _SrTiO3 , LSMO and _DyScO3 , LSMO and _TbScO3 , LSMO and GdScO3, LSMO and _NdScO3 , LSMO and _NdGaO3 , and/or LSMO and LSAT. In some embodiments, the thickness _of interface layer 304 is within a range of approximately 0.5 nm to approximately 5 nm. However, other values within this range are also within the scope of the present disclosure.

Non-volatile memory structure 220 may include a seed layer 306 on and/or above interface layer 304. Seed layer 306 may provide a base on which ferroelectric layer 308 of non-volatile memory structure 220 is formed. Seed layer 306 may include a single-layer structure or a multi-layer structure. Seed layer 306 may primarily have a cubic phase, a tetragonal phase, and/or an orthorhombic phase (e.g., wherein the cubic phase, the tetragonal phase, and/or the orthorhombic phase is greater than the monoclinic phase). Seed layer 306 may include one or more oxide materials, such as tantalum (Ta), tantalum pentoxide (Ta ₂ O ₅ ), zirconium (Zr), zirconium oxide (ZrO or ZrO ₂ ), yttrium oxide (Y ₂ O ₃ ), yttrium (Hf), yttrium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (Hf _x Zr _1-x O _y ), and/or another oxide material. In some embodiments, the thickness of seed layer 306 is within a range of approximately 0.1 nm to approximately 10 nm. However, other values within this range are also within the scope of the present disclosure.

Ferroelectric layer 308 may be included on and/or above seed layer 306. Ferroelectric layer 308 may include a layer having oxygen vacancies and/or primarily including a cubic phase, a tetragonal phase, and/or an orthorhombic phase (e.g., wherein the cubic phase, the tetragonal phase, and/or the orthorhombic phase is greater than the monoclinic phase). Examples include zirconium oxide (e.g., HfO or HfO ₂ ), zirconium oxide (e.g., ZrO ₂ ), aluminum nitride (AlN), aluminum nitride (e.g., AlScN), PBT (e.g., PbZrO ₃ ), PZT (e.g., Pb[Zr _x Ti _1-x ]O ₃ , (0 x 1)), PLZT (e.g., _{Pb1- xLaxZr1 - yTiyO3} ), barium titanate (e.g., _BaTiO3 ), lead titanate (e.g., _PbTiO3 ), lead metaniobate (e.g., _PbNb2O6 ), lithium niobate (e.g., _LiNbO3 ), lithium niobate ₍ e.g., _LiTaO3 ), PMN (e.g., _{PbMg1-3Nb2 / 3O3} ), PST (e.g., PbSc1 _{/2Ta1 / 2O3 )} , _{SBT (e.g., SrBi2Ta2O9 )} , BNT (e.g., Bi1 _{/ 2Na1 / 2TiO3} ), and/or combinations thereof. In some embodiments, the ferroelectric material may include dopants such as Sc, La, Ca, Ba, Yt, Sr, Zr, Si, Al, Sc, In, and/or Gd. For example, the ferroelectric material may include zirconium-doped bismuth oxide (e.g., Zr:HfO ₂ ), silicon-doped bismuth oxide (e.g., Si:HfO ₂ ), lumen-doped bismuth oxide (e.g., La:HfO ₂ ), aluminum-doped bismuth oxide (e.g., Al:HfO ₂ ), tantalum-doped bismuth oxide (e.g., Ta:HfO ₂ ), argon-doped bismuth oxide (e.g., Sc:HfO ₂ ), yttrium-doped bismuth oxide (e.g., Y:HfO ₂ ), strontium-doped bismuth oxide (e.g., Sr:HfO ₂ ), indium-doped bismuth oxide (e.g., In:HfO ₂ ), or amorphous metal oxide. ), and/or gadolinium-doped ferroelectric oxide (e.g., Gd:HfO ₂ ). In some exemplary embodiments, the thickness of the ferroelectric layer 308 is within a range of about 0.1 nm to about 100 nm. However, other values within this range are also within the scope of the present disclosure.

Non-volatile memory structure 220 may include a barrier layer 310 on and/or above ferroelectric layer 308. Barrier layer 310 may include a combination of silicon (Si) and helium oxide (HfO ₂ ). Barrier layer 310 may have a silicon to helium oxide ratio greater than about 1:10. However, other values are also within the scope of the present disclosure. Additionally and/or alternatively, barrier layer 310 may include silicon (Si), magnesium (Mg), aluminum (Al), lumen (La), yttrium oxide (Y ₂ O ₃ ), nitrogen (N), calcium (Ca), styril (Sc), strontium (Sr), gadolinium (Gd), titanium nitride (TiN), tungsten carbonitride (WCN), tungsten nitride (WN), and/or tantalum nitride (TaN), among others. In some exemplary embodiments, the oxygen-to-zirconium concentration or oxygen-to-arsenic concentration at the interface between barrier layer 310 and ferroelectric layer 308 may be greater than or equal to approximately 1:1. However, other values are also within the scope of the present disclosure. In some embodiments, the thickness of barrier layer 310 is within a range of approximately 0.1 nm to approximately 10 nm. However, other values within this range are also within the scope of the present disclosure.

Non-volatile memory structure 220 may include a metal oxide channel layer 312 located on and/or over blocking layer 310. Metal oxide channel layer 312 may include one or more metal oxide materials or metal oxide semiconductor materials. Examples include indium gallium zinc oxide (InGaZnO or IGZO), amorphous IGZO (α-IGZO), gallium zinc oxide (GaZnO or GZO), tin gallium zinc oxide (SnGaZnO or SGZO), silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon germanium carbon (SiGeC), gallium arsenide (GaAs), indium phosphide (InP), gallium phosphate (GaP), gallium nitride (GaN), gallium antimony (GaSb), aluminum arsenide (AlAs), indium arsenide (InAs), indium antimony (In Sb), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphate (GaInP), aluminum aluminum arsenide (InAlAs), aluminum indium gallium phosphate (AlInGaP), cadmium sulfide (CdS), cadmium selenide (CdSe), zinc sulfide (ZnS), zinc selenide (ZnSe), zinc sulfide (ZnTe), lead sulfide (PbS), lead sulfide (PbTe), mercury telluride (HgTe), indium gallium tin oxide (InGaSnO) and/or indium gallium tin zinc oxide (InGASnZnO), etc. In some embodiments, tantalum (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), tantalum (Ta), strontium (Sr), barium (Ba), stygium (Sc), magnesium (Mg), lumber (La), and/or gadolinium (Gd) may be used in place of gallium in metal oxide channel layer 312 to achieve a lower concentration of oxygen vacancies and/or lower surface states. Additionally and/or alternatively, II-VI compound semiconductor materials and/or III-V compound semiconductor materials may be used in the channel layer of non-volatile memory structure 220. In some exemplary embodiments, the thickness of metal oxide channel layer 312 is within a range of approximately 1 nm to approximately 100 nm. However, other values within this range are also within the scope of the present disclosure.

The non-volatile memory structure 220 may include source/drain electrodes 314 and 316 on and/or above the blocking layer 310. The source/drain electrodes may be referred to individually or collectively as source regions or drain electrodes, depending on the context. In some example embodiments, a metal oxide channel layer 312 is located between the source/drain electrodes 314 and 316, as shown in the example embodiment 300 in FIG3 . In some example embodiments, the source/drain electrodes 314 and 316 are included on the metal oxide channel layer 312, which is located between the blocking layer 310 and the source/drain electrodes 314 and 316. The source/drain electrodes 314 and 316 may each include one or more metal materials, such as aluminum (Al), titanium (Ti), tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), and/or gold (Au).

Bottom gate 302, ferroelectric layer 308, metal oxide channel layer 312, and source/drain electrodes 314 and 316 may correspond to a FeFET of non-volatile memory structure 220. Source/drain electrodes 314 and/or 316 may each be included in ILD layer 212. In some exemplary embodiments, the height or thickness of source/drain electrodes 314 and/or 316 may be within a range of approximately 10 nm to approximately 600 nm. However, other values within this range are also within the scope of the present disclosure.

To transition the non-volatile memory structure 220 to a programmed state, a first gate voltage (e.g., a positive gate voltage of +V _G ) may be applied to the bottom gate 302. This causes the electron charge carriers in the electron/hole pairs of the ferroelectric layer 308 to bias toward the bottom gate 302. A zero voltage (0V) may be applied to the source/drain 314, and the source/drain 316 may be grounded. This causes the metal oxide channel layer 312 to be in a non-conductive state, thereby causing the electron charge carriers in the electron/hole pairs of the ferroelectric layer 308 to bias toward the metal oxide channel layer 312.

To transition the non-volatile memory structure 220 to an erased state, a second gate voltage (e.g., a negative gate voltage of -V _G ) may be applied to the bottom gate 302. A zero voltage (0V) may be applied to the bottom gate 302. The source/drain 314 and 316 may be grounded. This places the metal oxide channel layer 312 in a conductive state. This causes the electron charge carriers in the electron/hole pairs in the ferroelectric layer 308 to bias toward the bottom gate 302, and causes the electron charge carriers in the electron/hole pairs in the ferroelectric layer 308 to bias toward the metal oxide channel layer 312.

Source/drain electrodes 314 and 316 can each be electrically coupled to conductive structure 216 in interconnect structure 204 of semiconductor device 200. This allows an electrical input (e.g., voltage, current) to be applied to source/drain electrodes 314 and/or 316, and/or allows source/drain electrodes 314 and/or 316 to be electrically grounded.

As further shown in FIG. 3 , hydrogen blocking layer 222 may be included between source/drain 314 and conductive structure 216, and/or hydrogen blocking layer 222 may be included between source/drain 316 and conductive structure 216. For example, hydrogen absorbing layer 222a of hydrogen blocking layer 222 may be included on source/drain 314, hydrogen blocking layer 222b of hydrogen blocking layer 222 may be included on hydrogen absorbing layer 222a, and conductive structure 216 may be included on hydrogen blocking layer 222b. As another example, the hydrogen absorbing layer 222 a of the hydrogen blocking layer 222 may be included on the source/drain 316 , the hydrogen blocking layer 222 b of the hydrogen blocking layer 222 may be included on the hydrogen absorbing layer 222 a , and the conductive structure 216 may be included on the hydrogen blocking layer 222 b . In some embodiments, the hydrogen blocking layer 222 omits the hydrogen absorbing layer 222 a , and the hydrogen blocking layer 222 b of the hydrogen blocking layer 222 is included on the source/drain 314 and/or the source/drain 316 . In some exemplary embodiments, the hydrogen barrier layer 222 omits the hydrogen absorption layer 222a, and the conductive structure 216 is included on the hydrogen barrier layer 222b of the hydrogen barrier layer 222.

As described above, Figure 3 is provided as an example. Other examples may differ from what is described with respect to Figure 3.

4 is a diagram of an example embodiment 400 of the non-volatile memory structure 220 described herein. The example embodiment 400 of the non-volatile memory structure 220 includes a similar combination and arrangement of layers and/or structures as the example embodiment 400 of the non-volatile memory structure 220. For example, the example embodiment 400 of the non-volatile memory structure 220 includes a bottom gate 302, an interface layer 304, a seed layer 306, a ferroelectric layer 308, a blocking layer 310, a metal oxide channel layer 312, and source/drain electrodes 314 and 316. In addition, a hydrogen blocking layer 222 (including a hydrogen absorption layer 222a and/or a hydrogen blocking layer 222b) may be included between the source/drain 314 and the conductive structure 216 and/or between the source/drain 316 and the conductive structure 216.

Additionally, the exemplary embodiment 400 of the non-volatile memory structure 220 includes a spacer 402 between the source/drain electrodes 314 and 316. The spacer 402 may include one or more dielectric materials, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and/or another suitable dielectric material. The spacer 402 may provide electrical isolation between the source/drain electrodes 314 and 316 and may provide a pedestal on which the source/drain electrodes 314 and 316 are formed. Source/drain electrodes 314 and 316 are included on portions of the top surface of metal oxide channel layer 312, on opposing sidewalls of spacer 402, and/or on portions of the top surface of spacer 402. Hydrogen barrier layer 222 (including hydrogen absorber layer 222a and/or hydrogen barrier layer 222b) conforms to the shape and/or contour of source/drain electrodes 314 and 316.

As described above, Figure 4 is provided as an example. Other examples may differ from what is described with respect to Figure 4.

FIG5 is a diagram of an example embodiment 500 of a hydrogen barrier layer 222 as described herein. As shown in FIG5 , the hydrogen barrier layer 222 may include a hydrogen absorbing layer 222a and a hydrogen barrier layer 222b on the hydrogen absorbing layer 222a.

The z-direction thickness of the hydrogen absorbing layer 222a corresponds to dimension D1. In some exemplary embodiments, dimension D1 is within a range of approximately 10 angstroms to approximately 1000 nanometers. If dimension D1 is less than approximately 10 angstroms, the hydrogen absorbing layer 222a may not provide sufficient hydrogen absorption to prevent hydrogen absorption and carrier concentration in the metal oxide channel layer 312 of the non-volatile memory structure 220. A dimension D1 greater than approximately 1000 nanometers may result in high contact resistance between the non-volatile memory structure 220 and the conductive structure 216 (and/or between the conductive structures 216), which may increase resistance-capacitance (RC) delay. If dimension D1 is within a range of approximately 10 angstroms to approximately 1000 nanometers, the hydrogen absorption layer 222a may be thick enough to effectively absorb hydrogen in the semiconductor device 200, and low RC delay may be achieved in the semiconductor device 200. However, other values of dimension D1 and ranges other than approximately 10 angstroms to approximately 1000 nanometers are also within the scope of the present disclosure.

The z-direction thickness of hydrogen barrier layer 222b is dimension D2. In some exemplary embodiments, dimension D2 is within a range of approximately 10 angstroms to approximately 1000 nanometers. If dimension D2 is less than approximately 10 angstroms, hydrogen barrier layer 222b may not provide sufficient hydrogen diffusion resistance to prevent hydrogen absorption and carrier concentration in metal oxide channel layer 312 of non-volatile memory structure 220. Values of dimension D2 greater than approximately 1000 nanometers may result in high contact resistance between non-volatile memory structure 220 and conductive structure 216 (and/or between conductive structures 216), which may lead to increased RC delay in semiconductor device 200. If dimension D2 is within a range of approximately 10 angstroms to approximately 1000 nanometers, the hydrogen barrier layer 222b may be thick enough to effectively block hydrogen diffusion in the semiconductor device 200, and low RC delay may be achieved in the semiconductor device 200. However, other values of dimension D2 and ranges other than approximately 10 angstroms to approximately 1000 nanometers are also within the scope of the present disclosure.

As described above, Figure 5 is provided as an example. Other examples may differ from the description of Figure 5.

Figures 6A through 6F illustrate example embodiments of a hydrogen barrier layer 222b described herein. In some embodiments, the hydrogen barrier layer 222b comprises a single layer structure, such as a ruthenium (Ru) layer or a titanium (Ti) layer. Exemplary embodiments of the hydrogen barrier layer 222b shown and described in conjunction with Figures 6A through 6F include a multi-layer stack, wherein the hydrogen barrier layer 222b comprises multiple layers. Including multiple layers in the hydrogen barrier layer 222b enables the hydrogen barrier properties of the hydrogen barrier layer 222b to be tailored to the specific type of material and/or thickness of the hydrogen barrier layer 222b.

As shown in FIG6A , an exemplary embodiment 600 of the hydrogen barrier layer 222 b includes a plurality of titanium nitride (TiN) layers, such as a titanium nitride layer 602, a titanium nitride layer 604 on the titanium nitride layer 602, and a titanium nitride layer 606 on the titanium nitride layer 604. Thus, the titanium nitride layers 602-606 are arranged along the z-direction in the semiconductor device 200. The titanium nitride layer 602 has a dimension D3 corresponding to the z-direction thickness of the titanium nitride layer 602. The titanium nitride layer 604 has a dimension D4 corresponding to the z-direction thickness of the titanium nitride layer 604. The titanium nitride layer 606 has a dimension D5 corresponding to the z-direction thickness of the titanium nitride layer 606. In example embodiment 600, dimension D3, dimension D4, and dimension D5 are approximately equal. In some example embodiments, dimension D3, dimension D4, and dimension D5 are all within a range of approximately 150 angstroms to approximately 250 angstroms. However, other values within this range are also within the scope of the present disclosure.

6B , an exemplary embodiment 608 of the hydrogen barrier layer 222 b includes a titanium nitride layer 602, a titanium (Ti) layer 610 (e.g., a metal layer) on the titanium nitride layer 602, and a titanium nitride layer 606 on the titanium layer 610. Thus, the titanium nitride layer 602, the titanium layer 610, and the titanium nitride layer 606 are arranged along the z-direction in the semiconductor device 200. The titanium nitride layer 602 has a dimension D3 corresponding to the z-direction thickness of the titanium nitride layer 602. The titanium layer 610 has a dimension D6 corresponding to the z-direction thickness of the titanium layer 610. Titanium nitride layer 606 has a dimension D5 corresponding to the z-direction thickness of titanium nitride layer 606 . In exemplary embodiment 608 , dimensions D3, D6, and D5 are approximately equal. In some exemplary embodiments, dimensions D3, D6, and D5 are all within a range of approximately 150 angstroms to approximately 250 angstroms. However, other values within this range are also within the scope of the present disclosure.

As shown in FIG6C , an exemplary embodiment 612 of the hydrogen barrier layer 222 b includes a titanium nitride layer 602, a ruthenium (Ru) layer 614 (e.g., a metal layer) on the titanium nitride layer 602, and a titanium nitride layer 606 on the ruthenium layer 614. Thus, the titanium nitride layer 602, the ruthenium layer 614, and the titanium nitride layer 606 are arranged along the z-direction in the semiconductor device 200. The titanium nitride layer 602 has a dimension corresponding to a dimension of a thickness of the titanium nitride layer 602 in the z-direction. The ruthenium layer 614 has a dimension D7 corresponding to a thickness of the ruthenium layer 614 in the z-direction. Titanium nitride layer 606 has a dimension D5 corresponding to the z-direction thickness of titanium nitride layer 606 . In exemplary embodiment 612 , dimension D3 and dimension D5 are approximately equal and are both within the range of approximately 150 angstroms to approximately 250 angstroms. However, other values within this range are also within the scope of the present disclosure. Dimension D7 is greater than dimension D3 and dimension D5. For example, dimension D7 may be within the range of approximately 210 angstroms to approximately 290 angstroms. However, other values within this range are also within the scope of the present disclosure.

As shown in FIG6D , example embodiment 616 of hydrogen barrier layer 222b includes titanium nitride layers 602-606, similar to example embodiment 600. However, in example embodiment 616, titanium nitride layer 604 has dimension D8. Dimension D8 corresponds to the z-direction thickness of titanium nitride layer 604 and is greater than dimensions D3 and D5. In some example embodiments, dimension D8 is within a range of approximately 550 angstroms to approximately 650 angstroms. However, other values within this range are also within the scope of the present disclosure. In some example embodiments, the ratio of dimension D8 to dimension D3 and the ratio of dimension D8 to dimension D5 are within a range of approximately 2:1 to approximately 4:1. However, other values within this range are also within the scope of the present disclosure.

As shown in FIG6E , example embodiment 618 of hydrogen barrier layer 222b includes titanium nitride layer 602, titanium layer 610, and titanium nitride layer 606, similar to example embodiment 608. However, in example embodiment 618, as shown, titanium layer 610 has dimension D9 corresponding to the z-direction thickness of titanium layer 610, and dimension D9 is greater than dimensions D3 and D5. In some example embodiments, dimension D9 is within a range of approximately 550 angstroms to approximately 650 angstroms. However, other values within this range are also within the scope of the present disclosure. In some example embodiments, the ratio of dimension D9 to dimension D3 and the ratio of dimension D9 to dimension D5 are within a range of approximately 2:1 to approximately 4:1. However, other values within this range are also within the scope of the present disclosure.

As shown in FIG6F , example embodiment 620 of hydrogen barrier layer 222b includes titanium nitride layer 602, ruthenium layer 614, and titanium nitride layer 606, similar to example embodiment 612. However, in example embodiment 620, as shown, ruthenium layer 614 has dimension D10 corresponding to the z-direction thickness of ruthenium layer 614, and dimension D10 is greater than dimensions D3 and D5. In some example embodiments, dimension D10 is within a range of approximately 430 angstroms to approximately 530 angstroms. However, other values within this range are also within the scope of the present disclosure. In some example embodiments, the ratio of dimension D10 to dimension D3 and the ratio of dimension D10 to dimension D5 are within a range of approximately 1.75:1 to approximately 3.5:1. However, other values within this range are also within the scope of the present disclosure.

As described above, Figures 6A to 6F are provided as examples. Other examples may differ from those described with respect to Figures 6A to 6F.

7A through 7C are graphs of exemplary hydrogen concentrations in semiconductor device 200 for the exemplary embodiments of hydrogen barrier layer 222 b shown and described in conjunction with FIG6A through FIG6F . FIG7A is an example 700 of hydrogen concentration 702 of hydrogen barrier layer 222 b with different layer arrangements as a function of depth 704 within semiconductor device 200. For example, example 700 includes hydrogen concentration 702 for exemplary embodiment 600 of hydrogen barrier layer 222 b, exemplary embodiment 608 of hydrogen barrier layer 222 b, and exemplary embodiment 612 of hydrogen barrier layer 222 b. Hydrogen concentration 702 is shown in the ILD layer 212, hydrogen barrier layer 222b, spacer 402, and metal oxide channel layer 312 above the non-volatile memory structure 220.

In example 700, the hydrogen concentration 702 of each of the example embodiments 600, 608, and 612 of the hydrogen barrier layer 222b results in blocking hydrogen diffusion from the ILD layer 212 into the metal oxide channel layer 312, as the hydrogen concentration 702 in the metal oxide channel layer 312 is less than the hydrogen concentration shown in the ILD layer 212. In the example embodiment 608 of the hydrogen barrier layer 222b, the hydrogen concentration 702 peaks near the top of the titanium layer 610 because the titanium layer 610 absorbs hydrogen in addition to blocking hydrogen diffusion. The ruthenium layer 614 in the exemplary embodiment 612 of the hydrogen barrier layer 222b absorbs less hydrogen than the titanium layer 610 and the titanium nitride layer 604 in the exemplary embodiment 600 of the hydrogen barrier layer 222b. Therefore, the hydrogen concentration 702 in the exemplary embodiment 612 of the hydrogen barrier layer 222b is less than the hydrogen concentration 702 in the exemplary embodiments 600 and 608 of the hydrogen barrier layer 222b.

FIG7B illustrates an example 706 of hydrogen concentrations 702 for example embodiments 616, 618, and 620 of the hydrogen barrier layer 222 b. As shown in FIG7B , example embodiments 616, 618, and 620 of the hydrogen barrier layer 222 b have similar hydrogen barrier properties to example embodiments 600, 608, and 612 of the hydrogen barrier layer 222 b, respectively.

As shown in example 708 in FIG. 7C , the greater thickness of the titanium layer 610 in example embodiment 618 of the hydrogen barrier layer 222 b may provide greater hydrogen barrier performance than the titanium layer 610 in example embodiment 608 of the hydrogen barrier layer 222 b because the hydrogen concentration 702 at the greater depth 704 in the metal oxide channel layer 312 of example embodiment 618 of the hydrogen barrier layer 222 b is lower than that of example embodiment 608 of the hydrogen barrier layer 222 b. Similarly, the greater thickness of the ruthenium layer 614 in the example embodiment 620 of the hydrogen barrier layer 222b can provide greater hydrogen barrier performance than the ruthenium layer 614 in the example embodiment 612 of the hydrogen barrier layer 222b because the depth of the hydrogen concentration 702 at the greater depth 704 in the metal oxide channel layer 312 of the example embodiment 620 of the hydrogen barrier layer 222b is less than that of the example embodiment 612 of the hydrogen barrier layer 222b.

As described above, Figures 7A to 7C are provided as examples. Other examples may differ from those described with respect to Figures 7A to 7C.

8A through 8K illustrate an example embodiment 800 for forming the semiconductor device 200 described herein. In some embodiments, one or more of the semiconductor processing operations described in FIG. 8A through FIG. 8K may be performed using one or more of the semiconductor processing tools 102 - 112 described herein. In some embodiments, another type of semiconductor processing tool may be used to perform one or more of the semiconductor processing operations described in FIG. 8A through FIG. 8K .

Turning to FIG. 8A , a substrate 206 is provided. The substrate 206 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, an SOI wafer, and/or another type of semiconductor workpiece.

As shown in FIG8B , semiconductor devices 208 can be formed in and/or on substrate 206 in device layer 202 of semiconductor device 200. One or more semiconductor processing tools 102-114 can be used to form one or more semiconductor devices 208. For example, deposition tool 102 can be used to perform various deposition operations to deposit layers of semiconductor device 208 and/or deposit a photoresist layer for etching portions of substrate 206 and/or semiconductor device 208. As another example, exposure tool 104 can be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, development tool 106 can develop the pattern in the photoresist layer. As another example, the etching tool 108 may be used to etch portions of the substrate 206 and/or deposited layers to form the semiconductor device 208. As another example, the planarization tool 110 may be used to planarize portions of the semiconductor device 208. As another example, the plating tool 112 may be used to deposit metal structures and/or layers of the semiconductor device 208.

As shown in FIG8C , deposition tool 102 is used to deposit dielectric layer 210 on and/or over substrate 206 and on and/or over semiconductor device 208. Deposition tool 102 may be used to deposit dielectric layer 210 using a PVD technique, an ALD technique, a CVD technique, an oxidation technique, another type of deposition technique described in conjunction with FIG1 , and/or another suitable deposition technique. In some example embodiments, planarization tool 110 may be used to planarize dielectric layer 210 after dielectric layer 210 is deposited.

As shown in FIG8D , a first portion of the interconnect structure 204 of the semiconductor device 200 is formed over the dielectric layer 210. The deposition tool 102 is used to deposit alternating layers of an ILD layer 212 and an ESL layer 214 in the first portion of the interconnect structure 204 of the semiconductor device 200. In this manner, the ILD layers 212 and the ESL layers 214 are arranged in the z-direction within the semiconductor device 200. The deposition tool 102 can be used to deposit each ILD layer 212 and each ESL layer 214 using a PVD technique, an ALD technique, a CVD technique, an oxidation technique, another type of deposition technique described in conjunction with FIG1 , and/or another suitable deposition technique. In some embodiments, the planarization tool 110 may be used to planarize the ILD layer 212 and/or the ESL 214 after depositing the ILD layer 212 and/or the ESL 214.

8D , the deposition tool 102, the exposure tool 104, the development tool 106, the etching tool 108, the planarization tool 110, and/or the plating tool 112 are used to perform various operations to form a conductive structure 216 located at a first portion of the interconnect structure 204 of the semiconductor device 200. The conductive structure 216 may be included in the ILD layer 212 and/or the ESL 214 and may be electrically coupled to the semiconductor device 208 in the device layer 202. In some exemplary embodiments, the ILD layer 212, the ESL 214, and the conductive structure 216 may be constructed in the metallization layer in the z-direction. For example, a first ESL 214 and a first ILD layer 212 may be formed, a recess may be formed in the first ESL 214 and/or the first ILD layer 212, and a first conductive structure 216 (e.g., an M0 metallization layer) may be formed in the recess. A second ESL 214 and a second ILD layer 212 may be formed over the first ESL 214 and the first ILD layer 212, a recess may be formed in the second ESL 214 and/or the second ILD layer 212, and a second conductive structure 216 (e.g., an M1 metallization layer) may be formed in the recess. The remaining metallization layers of the first portion of the interconnect structure 204 may be formed in a similar manner.

As shown in FIG8E , a second portion of interconnect structure 204 of semiconductor device 200 is formed on and/or over the first portion of interconnect structure 204. Techniques similar to those described in conjunction with FIG8D may be performed to form the second portion of interconnect structure 204. Furthermore, a non-volatile memory structure 220 is formed in ILD layer 212 in the second portion of interconnect structure 204. A conductive structure 216 may be formed on non-volatile memory structure 220 to electrically connect non-volatile memory structure 220 in interconnect structure 204. Example embodiments for forming non-volatile memory structure 220 are shown and described in conjunction with FIG10A through FIG10N .

As further shown in FIG8E , one or more hydrogen blocking layers 222 may be formed on the non-volatile memory structure 220, and a conductive structure 216 coupled to the non-volatile memory structure 220 may be formed on the one or more hydrogen blocking layers 222. In some embodiments, forming the hydrogen blocking layer 222 includes forming a hydrogen absorbing layer 222a on the non-volatile memory structure 220 and forming a hydrogen blocking layer 222b on the hydrogen absorbing layer 222a. The conductive structure 216 may then be formed on the hydrogen blocking layer 222b. In some embodiments, forming the hydrogen blocking layer 222 includes forming a hydrogen absorbing layer 222a on the non-volatile memory structure 220, and forming the conductive structure 216 on the hydrogen absorbing layer 222a. In some embodiments, forming the hydrogen blocking layer 222 includes forming a hydrogen blocking layer 222b on the non-volatile memory structure 220, and forming the conductive structure 216 on the hydrogen blocking layer 222b.

The hydrogen gettering layer 222a can be formed using a deposition tool 102. In some exemplary embodiments, the deposition tool 102 is configured to deposit the hydrogen gettering layer 222a using an ALD technique (such as the ALD technique shown and described in conjunction with FIG. 9A and/or FIG. 9B ). In some embodiments, the deposition tool 102 is configured to deposit the hydrogen gettering layer 222a using another deposition technique, such as a PVD technique, a CVD technique, an oxidation technique, another type of deposition technique described in conjunction with FIG. 1 , and/or another suitable deposition technique.

The hydrogen barrier layer 222b may be formed using a deposition tool 102. In some exemplary embodiments, the deposition tool 102 is configured to deposit the hydrogen barrier layer 222b using a PVD technique, such as a sputtering technique. In some exemplary embodiments, the deposition tool 102 is configured to deposit the hydrogen barrier layer 222b using another deposition technique, such as a PLD technique, an ALD technique, a CVD technique, an oxidation technique, another type of deposition technique described in connection with FIG. 1 , and/or another suitable deposition technique. In some exemplary embodiments, forming the hydrogen barrier layer 222b includes forming one or more of the exemplary embodiments of the multi-layer stack shown and described in connection with FIG. 6A through FIG. 6F .

As shown in Figures 8F and 8I , the third portion of interconnect structure 204 is formed over the second portion of interconnect structure 204 and over non-volatile memory structure 220. As shown in Figure 8F , ESL 214 and ILD layer 212 are formed over non-volatile memory structure 220. Deposition tool 102 may be used to deposit ILD layer 212 and/or ESL 214 using PVD technology, ALD technology, CVD technology, oxidation technology, a combination of the technology described in Figure 1 , and/or another suitable deposition technology. In some embodiments, planarization tool 110 may be used to planarize ILD layer 212 and/or ESL 214 after deposition.

As shown in FIG8G , a recess 802 is formed in and/or through the ILD layer 212 and the ESL 214. The recess 802 may be formed above one or more conductive structures 216, such that the one or more conductive structures 216 are exposed through the recess 802. In some embodiments, a pattern in the photoresist layer is used to etch the ILD layer 212 and/or the ESL 214 to form the recess 802. In these exemplary embodiments, a deposition tool 102 may be used to form the photoresist layer on the ILD layer 212. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to reveal the pattern. The etch tool 108 can be used to etch the ILD layer 212 and/or the ESL 214 based on a pattern to form the recess 802. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and/or another type of etching operation. In some embodiments, a photoresist stripping tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-etching the ILD layer 212 and/or the ESL 214.

As further shown in FIG8H , one or more hydrogen barrier layers 222 may be formed on the top surface of the conductive structure 216 exposed by the recess 802. In some example embodiments, forming the hydrogen barrier layer 222 includes forming a hydrogen absorbing layer 222a on the conductive structure 216 in the recess 802 and forming a hydrogen barrier layer 222b on the hydrogen absorbing layer 222a. In some embodiments, forming the hydrogen barrier layer 222 includes forming only the hydrogen absorbing layer 222a on the conductive structure 216 in the recess 802. In some embodiments, forming the hydrogen barrier layer 222 includes forming only the hydrogen absorbing layer 222b on the conductive structure 216 in the recess 802.

The hydrogen gettering layer 222a can be formed using a deposition tool 102. In some exemplary embodiments, the deposition tool 102 is used to deposit the hydrogen gettering layer 222a using an ALD technique (such as the ALD technique shown and described in conjunction with FIG. 9A and/or FIG. 9B ). In some exemplary embodiments, the deposition tool 102 is used to deposit the hydrogen gettering layer 222b using another deposition technique, such as a PVD technique, a CVD technique, an oxidation technique, another type of deposition technique described in conjunction with FIG. 1 , and/or another suitable deposition technique.

The hydrogen barrier layer 222b may be formed using a deposition tool 102. In some exemplary embodiments, the deposition tool 102 is configured to deposit the hydrogen barrier layer 222b using a PVD technique, such as a sputtering technique. In some exemplary embodiments, the deposition tool 102 is configured to deposit the hydrogen barrier layer 222b using another deposition technique, such as a PLD technique, an ALD technique, a CVD technique, an oxidation technique, another type of deposition technique described in connection with FIG. 1 , and/or another suitable deposition technique. In some exemplary embodiments, forming the hydrogen barrier layer 222b includes forming one or more of the exemplary embodiments of the multi-layer stack shown and described in connection with FIG. 6A through FIG. 6F .

As shown in FIG8I , the conductive structure 216 is formed in the recess 802 . Specifically, the conductive structure 216 is formed on the hydrogen barrier layer 222 in the recess 802 such that the hydrogen barrier layer 222 is included between vertically adjacent conductive structures 216 (e.g., conductive structures 216 adjacent in the z-direction) in the interconnect structure 204 .

Deposition tool 102 and/or plating tool 112 may deposit conductive structure 216 in recess 802 using a CVD technique, a PVD technique, an ALD technique, a plating technique, another deposition technique described above in conjunction with FIG. 1 , and/or a deposition technique in addition to the deposition technique described above in conjunction with FIG. 1 . In some embodiments, planarization tool 110 may perform a CMP operation after depositing conductive structure 216 to planarize conductive structure 216 .

As shown in FIG8J , the fourth portion of the interconnect structure 204 can be formed over the third portion of the interconnect structure 204. The fourth portion of the interconnect structure 204 can be formed using a similar combination of techniques as described in conjunction with FIG8F through FIG8I , such that the hydrogen barrier layer 222 is included between the conductive structure 216 in the third portion of the interconnect structure 204 and the conductive structure 216 in the fourth portion of the interconnect structure 204.

As shown in FIG8K , a connection structure 218 is formed on the interconnect structure 204 such that the connection structure 218 is electrically and/or physically coupled to one or more conductive structures 216 in the interconnect structure 204. The deposition tool 102 and/or the plating tool 112 may be used to deposit the connection structure 218 using a CVD technique, a PVD technique, an ALD technique, a plating technique, another deposition technique described above in conjunction with FIG1 , and/or a deposition technique other than that described above in conjunction with FIG1 . In some exemplary embodiments, a semiconductor packaging tool connects the connection structure 218 to the semiconductor device 200.

As described above, Figures 8A to 8K are provided as examples. Other examples may differ from those described with respect to Figures 8A to 8K.

9A and 9B illustrate an example embodiment of a hydrogen absorbing layer 222a forming a hydrogen barrier layer 222 described herein. The processes described in FIG. 9A and 9B can be performed using one or more of the semiconductor processing tools 102 - 112 described herein, such as deposition tool 102 (e.g., an ALD tool).

FIG9A illustrates an example embodiment 900 for forming a hydrogen absorbing layer 222a of the hydrogen barrier layer 222 described herein. Example embodiment 900 includes an example ALD technique in which a layer-by-layer crystalline structure of the hydrogen absorbing layer 222a is formed. Various operations in the ALD technique are performed as a function of time 902.

As shown in FIG9A , multiple ALD cycles 904 are performed to form the hydrogen gettering layer 222 a. The ALD cycles 904 in the exemplary embodiment 900 include the use of a continuous gaseous precursor (or reactant). The semiconductor device 200 is placed in a processing chamber of the deposition tool 102, and an oxygen-containing gas 906 is pulsed during the ALD cycle 904 to perform an oxygen treatment on the semiconductor device 200. The oxygen-containing gas 906 may include ozone (O ₃ ), oxygen (O ₂ ), water vapor (H ₂ O), and/or other oxygen-containing gases. The duration of the pulse of the oxygen-containing gas 906 may be in the range of about 0.1 seconds to about 3 seconds. However, other values within this range are also within the scope of the present disclosure.

The pulse of oxygen-containing gas 906 is followed by a first pulse of a first metal material precursor 908, wherein the first metal material precursor 908 is provided to the process chamber of the deposition tool 102. The first metal material precursor 908 may include an indium (In) vapor phase precursor for the IGZO hydrogen absorber layer 222a. Examples of indium precursors include _{99.99% trace metal basis indium (III) acetate (C6H9InO6 ) ,} 99.99% trace metal basis indium (III) _acetate hydrate _{(C6H9InO6xH2O ) ,} and/or 99.99% trace metal indium (III) _{acetylacetonate} ( _C15H21InO6 ), etc. The duration of the first pulse of the first metal precursor 908 can be within the range of about 0.1 seconds _to about 3 seconds. However, other values within this range are also within the scope of the present disclosure.

The first metal precursor 908 is then purged from the process chamber, and another pulse of an oxygen-containing gas 906 is provided to the process chamber. The pulse of the oxygen-containing gas 906 is followed by a pulse of a second metal precursor 910, which is provided to the process chamber of the deposition tool 102. The second metal precursor 910 may include a zinc (Zn) vapor-phase precursor for the IGZO hydrogen absorber layer 222a. Examples of zinc precursors include approximately 99.9999% pure zinc, 97% bis(pentafluorophenyl)zinc ((C ₆ F ₅ ) ₂ Zn), 97% bis(2,2,6,6-tetramethyl-3,5-heptanedione)zinc(II) (Zn(OCC(CH ₃ ) ₃ CHCOC(CH ₃ ) ₃ ) ₂ ), diethylzinc 52 wt% Zn-based (C ₂ H ₅ ) ₂ Zn), and/or 92% diphenyl zinc ((C ₆ H ₅ ) ₂ Zn), etc. The duration of the pulse of the second metal material precursor 910 can be included in the range of about 0.1 seconds to about 3 seconds. However, other values within this range are also within the scope of the present disclosure.

The second metal material precursor 910 is then purged from the process chamber, and another pulse of an oxygen-containing gas 906 is provided to the process chamber. The pulse of oxygen-containing gas 906 is followed by a pulse of a semiconductor material precursor 912, which is provided to the process chamber of deposition tool 102. Semiconductor material precursor 912 may include a gallium (Ga) vapor-phase precursor for the IGZO hydrogen absorber layer 222a. Examples of gallium precursors include _{triethylgallium ((CH₃CH₂)₃Ga ) ,} trimethylgallium (Ga( _CH₃ ) _₃ ), and/or _tris ( _{dimethylamino} )gallium(III) ₉₈ % ( _{C₁₂H₃Ga₂N₆} ). The pulse duration of the semiconductor material precursor 912 may be within a range of about 0.1 seconds to about 3 seconds. However, other values within this range are also within the scope of the present disclosure.

Semiconductor material precursor 912 is then purged from the process chamber, and another pulse of oxygen-containing gas 906 is provided to the process chamber. This pulse of oxygen-containing gas 906 is followed by back-to-back pulses of second metal material precursor 910 and first metal material precursor 908. In other words, a second pulse of second metal material precursor 910 is provided to the process chamber of deposition tool 102, second metal material precursor 910 is subsequently removed from the process chamber, and a second pulse of first metal material precursor 908 is provided to the process chamber without an intervening pulse of oxygen-containing gas 906.

Alternatively, a tin (Sn) vapor phase precursor may be used to replace the first metal precursor 908 (eg, to form a ZnSnO hydrogen absorber layer 222a) or the second metal precursor 910 (eg, to form an InSnO hydrogen absorber layer). Examples of tin precursors include bis[bis(trimethylsilyl)amino]tin(II) ([[(CH ₃ ) ₃ Si] ₂ N] ₂ Sn), tetraallyltin 97% ((H ₂ C=CHCH ₂ ) ₄ Sn), tetrakis(diethylamino)tin(IV) ([(C ₂ H ₅ ) ₂ N] ₄ Sn), tetrakis(dimethylamino)tin(IV) 99.9% trace metal ([(CH ₃ ) ₂ N] ₄ Sn), tetramethyltin 95% green substitute (SN(CH ₃ ) ₄ ), tetravinyltin 97% (Sn(CH=CH ₂ ) ₄ ), tin(II) acetylacetonate 99.9% trace metal (C ₁₀ H ₁₄ O ₄ Sn), trimethyl(phenylethynyl)tin 97% (C ₆ H ₅ C═CSn(CH ₃ ) ₃ ) and/or trimethyl(phenyl)tin 98% (C ₆ H ₅ Sn(CH ₃ ) ₃ ), and the like.

The first pulse of the first metal precursor 908 may react with the oxygen-containing gas 906 to form a metal oxide portion 914a of the hydrogen absorbing layer 222a. The metal oxide portion 914a includes an oxygen-containing metal material (e.g., a metal oxide material) that includes the metal of the first metal precursor 908. The first pulse of the second metal precursor 910 may react with the oxygen-containing gas 906 to form a metal oxide portion 916a of the hydrogen absorbing layer 222a on the metal oxide portion 914a. The metal oxide portion 916a includes an oxygen-containing metal material (e.g., a metal oxide material) that includes the metal of the second metal precursor 910. The pulse of semiconductor material precursor 912 can react with oxygen-containing gas 906 to form an oxide semiconductor portion 918 of hydrogen absorbing layer 222a located on metal oxide portion 916a. Oxide semiconductor portion 918 includes an oxygen-containing semiconductor material, which includes the semiconductor material of semiconductor material precursor 912. A second pulse of a second metal material precursor 910 can react with oxygen-containing gas 906 to form a metal oxide portion 916b of hydrogen absorbing layer 222a located on oxide semiconductor portion 918. Metal oxide portion 916b includes an oxidized metal material (e.g., a metal oxide material), which includes the metal of second metal material precursor 910. The second pulse of the first metal precursor 908 can react with the oxygen-containing gas 906 to form a metal oxide portion 914b of the hydrogen absorbing layer 222a on the metal oxide portion 916b. The metal oxide portion 914b includes an oxidized metal material (e.g., a metal oxide material) including the metal of the first metal precursor 908.

Additional ALD cycles 904 may be performed to form the repeating layer-by-layer crystal structure shown in FIG. 9A . The number of ALD cycles 904 performed may be based on the desired thickness of the hydrogen getter layer 222 a. In some exemplary embodiments, the deposition rate of each ALD cycle 904 is within a range of approximately 0.5 angstroms per ALD cycle 904 to approximately 2 angstroms per ALD cycle 904 . However, other values within this range are also within the scope of the present disclosure. The duration of each ALD cycle 904 may be within a range of approximately 3 seconds to approximately 6 seconds. However, other values within this range are also within the scope of the present disclosure.

In some exemplary embodiments, the repeating layer-by-layer crystal structure shown in FIG. 9A is visible in the final structure of semiconductor device 200. In some exemplary embodiments, portions 914a, 916a, 918, 916b, and/or 914b are at least partially intermixed due to subsequent thermal processing. ALD cycle 904 may each include pulses of the first metal precursor 908 and the second metal precursor 910 in greater quantities than the pulses of the semiconductor precursor 912 to achieve a high nitrogen concentration in hydrogen absorber layer 222a.

FIG9B illustrates an example embodiment 920 of forming a hydrogen absorbing layer 222a of the hydrogen barrier layer 222 described herein. In example embodiment 920, an ALD supercycle 922 is performed, wherein multiple precursor cycles are performed to form portions of the hydrogen absorbing layer 222a to a greater thickness than in example embodiment 900. This results in a layer-by-layer crystalline structure of the hydrogen absorbing layer 222a that is more clearly visible in the final structure.

As shown in FIG9B , a first metal precursor cycle 924a is performed, wherein a first pulse of the oxygen-containing gas 906, a first pulse of the first metal precursor 908, a second pulse of the oxygen-containing gas 906, and a second pulse of the first metal precursor 908 are sequentially performed. The first metal precursor cycle 924a in the ALD super cycle 922 is performed to deposit metal oxide portions 914a and 914b of the hydrogen getter layer 222a.

After the first metal precursor cycle 924a, a second metal precursor cycle 926a is executed. In the second metal precursor cycle 926a, a first pulse of the oxygen-containing gas 906, a first pulse of the second metal precursor 910, a second pulse of the oxygen-containing gas 906, and a second pulse of the second metal precursor 910 are sequentially performed. The second metal precursor cycle 926a in the ALD super cycle 922 is executed to deposit metal oxide portions 916a and 916b of the hydrogen gettering layer 222a on the metal oxide portions 914a and 914b.

After the second metal material precursor cycle 926a, a semiconductor material precursor cycle 928 is performed. In semiconductor material precursor cycle 928, a first pulse of oxygen-containing gas 906, a first pulse of semiconductor material precursor 912, a second pulse of oxygen-containing gas 906, and a second pulse of semiconductor material precursor 912 are sequentially performed. Semiconductor material precursor cycle 928 in ALD super cycle 922 is performed to deposit oxide semiconductor portions 918a and 918b of hydrogen gettering layer 222a on metal oxide portions 916a and 916b.

After semiconductor material precursor cycle 928, another second metal material precursor cycle 926b is executed. In second metal material precursor cycle 926b, a first pulse of oxygen-containing gas 906, a first pulse of second metal material precursor 910, a second pulse of oxygen-containing gas 906, and a second pulse of second metal material precursor 910 are sequentially executed. The second metal material precursor cycle 926b in ALD super cycle 922 is executed to deposit metal oxide portions 916c and 916d of hydrogen gettering layer 222a on oxide semiconductor portions 918a and 918b.

Another first metal precursor cycle 924b is performed after second metal precursor cycle 926b. In first metal precursor cycle 924b, a first pulse of oxygen-containing gas 906, a first pulse of first metal precursor 908, a second pulse of oxygen-containing gas 906, and a second pulse of first metal precursor 908 are sequentially performed. First metal precursor cycle 924b in ALD super cycle 922 is performed to deposit metal oxide portions 914c and 914d of hydrogen gettering layer 222a on metal oxide portions 916c and 916d.

As described above, FIG. 9A and FIG. 9B are provided as examples. Other examples may differ from those described with respect to FIG. 9A and FIG. 9B .

Figures 10A through 10N are diagrams of an example embodiment 1000 for forming a non-volatile memory structure 220 described herein. In some embodiments, one or more semiconductor processing operations described in Figures 10A through 10N may be performed using one or more of the semiconductor processing tools 102-112 described herein. In some embodiments, another type of semiconductor processing tool may be used to perform one or more semiconductor processing operations described in Figures 10A through 10N.

As shown in FIG. 10A , the operations described in example embodiment 1000 may be performed in conjunction with the ILD layer 212 of the interconnect structure 204 of the semiconductor device 200 .

As shown in FIG10B and FIG10C , the bottom gate 302 may be formed in the ILD layer 212 . The bottom gate 302 may be formed in a recess 1002 in the ILD layer 212 . Alternatively, the bottom gate 302 may be formed on the ILD layer 212 .

In some embodiments, the pattern in the photoresist layer is used to etch the ILD layer 212 to form the recess 1002. In these embodiments, a deposition tool 102 may be used to form the photoresist layer on the ILD layer 212. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to reveal the pattern. An etching tool 108 may be used to etch the ILD layer 212 based on the pattern to form the recess 1002 in the ILD layer 212. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and/or another type of etching operation. In some embodiments, a photoresist stripping tool may be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the ILD layer 212.

The deposition tool 102 and/or the electroplating tool 112 may deposit the bottom gate 302 in the recess 1002 using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in conjunction with FIG. 1 , and/or a deposition technique in addition to the deposition technique described above in conjunction with FIG. 1 . In some embodiments, the planarization tool 110 may perform a CMP operation after depositing the bottom gate 302 to planarize the bottom gate 302 .

As shown in FIG10D , interface layer 304 may be formed on and/or over ILD layer 212 and on and/or over bottom gate 302. As further shown in FIG10D , seed layer 306 may be formed on and/or over interface layer 304. In some embodiments, deposition tool 102 may be configured to perform an in-situ thermal annealing operation, which may include thermally annealing interface layer 304 and/or seed layer 306 while being deposited. Tool 102 may be configured to deposit interface layer 304 and/or seed layer 306. The thermal annealing operation may increase the crystallinity of interface layer 304 and/or seed layer 306. Deposition tool 102 may be configured to deposit interface layer 304 and/or seed layer 306. Interface layer 304 and/or seed layer 306 are formed using an ALD technique or a pulsed layer deposition (PLD) technique. Deposition tool 102 may heat interface layer 304 and/or seed layer 306 to a temperature within a range of approximately 300 degrees Celsius to approximately 700 degrees Celsius for a duration of approximately 30 seconds to approximately 10 minutes to achieve crystallinity in interface layer 304 and/or seed layer 306. However, other values within these ranges are also within the scope of the present disclosure. Furthermore, interface layer 304 may be formed as a quasi-single crystalline metal oxide.

As shown in FIG10E , ferroelectric layer 308 may be formed on and/or over seed layer 306. Seed layer 306 promotes the growth of ferroelectric layer 308 with a specific crystal structure and/or to a specific grain size. Deposition tool 102 may be used to deposit ferroelectric layer 308 using an ALD technique, a CVD technique, a PVD technique, another deposition technique described above in conjunction with FIG1 , and/or a deposition technique other than the deposition technique described above in conjunction with FIG1 . In some embodiments, planarization tool 110 may perform a CMP operation after depositing ferroelectric layer 308 to planarize ferroelectric layer 308.

As shown in FIG10F , barrier layer 310 may be formed on and/or over ferroelectric layer 308. Deposition tool 102 may be used to utilize an ALD technique, a CVD technique, a PVD technique, another deposition technique described above in conjunction with FIG1 , and/or a deposition technique in addition to the deposition technique described above in conjunction with FIG1 . In some example embodiments, planarization tool 110 may perform a CMP operation after depositing barrier layer 310 to planarize barrier layer 310 .

As shown in FIG10G , metal oxide channel layer 312 may be formed on and/or over barrier layer 310. Deposition tool 102 may be used to deposit metal oxide channel layer 312 using an ALD technique, a CVD technique, a PVD technique, another deposition technique described above in conjunction with FIG1 , and/or a deposition technique in addition to the deposition technique described above in conjunction with FIG1 . In some embodiments, planarization tool 110 may perform a CMP operation to planarize metal oxide channel layer 312 after depositing metal oxide channel layer 312. In some example embodiments, a mixture of precursor gases used to deposit metal oxide channel layer 312 (which may be referred to as a “mixture”) may be selected to achieve a suitable electron mobility and surface state for metal oxide channel layer 312. This mixture may include a mixture of solid metal precursors. A low-pressure vessel (LPV) may be used to vaporize the mixture, and the resulting vaporized precursor mixture may be introduced (e.g., pulsed) into an ALD reaction chamber containing non-volatile memory structure 220. The vaporized precursor mixture may react with barrier layer 310 and/or ferroelectric layer 308 when depositing metal oxide channel layer 312.

As shown in FIG10H , additional material of ILD layer 212 may be formed on and/or over metal oxide channel layer 312. Furthermore, additional material of ILD layer 212 may be formed such that non-volatile memory structure 220 is encapsulated by ILD layer 212. Deposition tool 102 may be used to deposit additional material of ILD layer 212 using an ALD technique, a CVD technique, a PVD technique, an oxidation technique, another deposition technique described above in conjunction with FIG1 , and/or a deposition technique in addition to the deposition technique described above in conjunction with FIG1 . In some example embodiments, planarization tool 110 may perform a CMP operation to planarize ILD layer 212 after depositing the additional material of ILD layer 212.

As shown in FIG10I , recesses 1004 and 1006 may be formed in and/or through the ILD layer 212, such that the sidewalls of the metal oxide channel layer 312 are exposed through the recesses 1004 and 1006. In some exemplary embodiments, a photoresist layer is used to etch the ILD layer 212 to form the recesses 1004 and 1006. In these embodiments, a deposition tool 102 may be used to form the photoresist layer on the ILD layer 212. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to reveal a pattern. The etch tool 108 may be used to etch the ILD layer 212 based on a pattern to form the recesses 1004 and 1006 in the ILD layer 212. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and/or another type of etching operation. In some embodiments, a photoresist stripping tool may be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-etching the ILD layer 212.

As shown in FIG10J , source/drain electrodes 314 and 316 are formed in recesses 1004 and 1006, respectively. Source/drain electrodes 314 and 316 can be deposited using deposition tool 102 and/or electroplating tool 112, including using CVD techniques, PVD techniques, ALD techniques, electroplating techniques, another deposition technique described above in conjunction with FIG1 , and/or another suitable deposition technique. In some embodiments, planarization tool 110 can be used to planarize source/drain electrodes 314 and 316 after deposition. Planarization of the source/drain electrodes 314 and 316 results in the top surfaces of the source/drain electrodes 314 and 316 being substantially coplanar with the top surface of the ILD layer 212.

As shown in FIG10K , additional material for ILD layer 212 may be formed on and/or over source/drain electrodes 314 and 316. Deposition tool 102 may be used to deposit the additional material for ILD layer 212 using an ALD technique, a CVD technique, a PVD technique, an oxidation technique, another deposition technique described above in conjunction with FIG1 , and/or a deposition technique in addition to the deposition technique described above in conjunction with FIG1 . Planarization tool 110 may perform a CMP operation after depositing the additional material for ILD layer 212 to planarize ILD layer 212.

As shown in FIG10L , recesses 1008 and 1010 may be formed in and/or through the ILD layer 212, such that the top surfaces of the source/drain electrodes 314 and 316 are exposed through the recesses 1008 and 1010, respectively. In some embodiments, a pattern in the photoresist layer is used to etch the ILD layer 212 to form the recesses 1008 and 1010. In these embodiments, a deposition tool 102 may be used to form the photoresist layer on the ILD layer 212. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to reveal the pattern. The etch tool 108 may be used to etch the ILD layer 212 based on a pattern to form recesses 1008 and 1010 in the ILD layer 212. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and/or another type of etching operation. In some embodiments, a photoresist stripping tool may be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-etching the ILD layer 212.

10M , a hydrogen blocking layer 222 is formed on the top surfaces of the source/drain electrodes 314 and 316 in the recesses 1008 and 1010, respectively. For example, a hydrogen absorbing layer 222 a of the hydrogen blocking layer 222 may be formed on the top surface of the source/drain electrode 314 in the recess 1008, and a hydrogen blocking layer 222 b of the hydrogen blocking layer 222 may be formed on the hydrogen absorbing layer 222 a of the hydrogen blocking layer 222. The hydrogen absorbing layer 222 a is located on the top surface of the source/drain electrode 314 in the recess 1008. As another example, the hydrogen blocking layer 222b of the hydrogen blocking layer 222 can be formed on the top surface of the source/drain. The hydrogen absorbing layer 222a of the hydrogen blocking layer 222 can be formed on the hydrogen blocking layer 222b on the top surface of the source/drain 316 in the recess 1010. In some embodiments, the hydrogen absorbing layer 222a is formed using one or more of the techniques described in conjunction with FIG. 9A and/or FIG. 9B.

As shown in FIG. 10N , conductive structure 216 is formed on hydrogen barrier layer 222 above source/drain electrodes 314 and 316 in recesses 1008 and 1010, respectively. Deposition tool 102 and/or plating tool 112 may be used to deposit conductive structure 216 using CVD, PVD, ALD, plating, another deposition technique described above in conjunction with FIG. 1 , and/or another suitable deposition technique. In some exemplary embodiments, planarization tool 110 may be used to planarize conductive structure 216 after depositing conductive structure 216.

As described above, Figures 10A to 10N are provided as examples. Other examples may differ from those described with respect to Figures 10A to 10N.

FIG11 is a diagram of example components of an apparatus 1100 described herein. In some embodiments, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may include one or more apparatuses 1100 and/or one or more parts of apparatus 1100. As shown in FIG11 , apparatus 1100 may include a bus 1110, a processor 1120, a memory 1130, an input component 1140, an output component 1150, and/or a communication component 1160.

The bus 1110 may include one or more components that implement wired and/or wireless communication between components of the device 1100. The bus 1110 may couple two or more components of Figure 11 together, for example, via operational coupling, communicative coupling, electronic coupling, coupling, and/or electrical coupling. For example, the bus 1110 may include electrical connections (e.g., wires, traces, and/or leads) and/or a wireless bus. The processor 1120 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, a dedicated integrated circuit, and/or another type of processing unit. The processor 1120 may be implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 1120 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

Memory 1130 may include volatile and/or non-volatile memory. For example, memory 1130 may include random access memory (RAM), read-only memory (ROM), a hard drive, and/or other types of memory (e.g., flash memory, magnetic memory, and/or optical memory). Memory 1130 may include internal memory (e.g., RAM, ROM, or a hard drive) and/or removable memory (e.g., removable via a Universal Serial Bus connection). Memory 1130 may be a non-transitory computer-readable medium. Memory 1130 may store information related to the operation of device 1100, one or more instructions, and/or software (e.g., one or more software applications). In some implementations, memory 1130 may include one or more memories coupled, for example, via bus 1110 (e.g., communicatively coupled) to one or more processors (e.g., processor 1120). The communicative coupling between processor 1120 and memory 1130 may enable processor 1120 to read and/or store information in memory 1130 and/or process information stored in processor 1120.

Input components 1140 may enable device 1100 to receive input, such as user input and/or sensory input. For example, input components 1140 may include a touch screen, a keyboard, a keypad, a mouse, buttons, a microphone, a switch, a sensor, a GPS sensor, a GPS sensor, an accelerometer, a gyroscope, and/or an actuator. Output components 1150 may enable device 1100 to provide output, such as via a display, a speaker, and/or an LED. Communication components 1160 may enable device 1100 to communicate with other devices via wired and/or wireless connections. For example, the communication component 1160 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.

The device 1100 can perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1130) can store a set of instructions (e.g., one or more instructions or program codes) for execution by the processor 1120. The processor 1120 can execute this set of instructions to perform one or more operations or processes described herein. In some implementations, execution of the set of instructions by the one or more processors 1120 causes the one or more processors 1120 and/or the device 1100 to perform one or more operations or processes described herein. In some implementations, hard-wired circuitry can be used in place of or in combination with instructions to perform one or more operations or processes described herein. Additionally or alternatively, the processor 1120 may be configured to perform one or more of the operations or processes described herein. Therefore, the implementations described herein are not limited to any specific combination of hardware circuitry and software.

The number and arrangement of components shown in FIG11 are provided as examples. Device 1100 may include more components, fewer components, different components, or components arranged differently than shown in FIG11 . Additionally or alternatively, a component (e.g., one or more components) of device 1100 may perform one or more functions described as being performed by another component of device 1100.

FIG12 is a flow chart of an example process 1200 associated with forming a non-volatile memory structure described herein. In some implementations, one or more processing blocks of FIG12 are performed using one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-112). Additionally or alternatively, one or more processing blocks of FIG12 may be performed using one or more components of device 1100, such as processor 1120, memory 1130, input component 1140, output component 1150, and/or communication component 1160.

As shown in FIG12 , process 1200 may include forming a bottom gate of the non-volatile memory structure (block 1210 ). For example, one or more of semiconductor processing tools 102 - 112 may be used to form bottom gate 302 of non-volatile memory structure 220 , as described herein.

As further shown in FIG. 12 , process 1200 may include forming a ferroelectric layer 308 of the non-volatile memory structure above the bottom gate (block 1220 ). For example, one or more of semiconductor processing tools 102 - 112 may be used to form the ferroelectric layer 308 of the non-volatile memory structure 220 above the bottom gate 302 , as described herein.

As further shown in FIG. 12 , process 1200 may include forming a metal oxide channel layer of the non-volatile memory structure above the ferroelectric layer (block 1230 ). For example, one or more of semiconductor processing tools 102 - 112 may be used to form metal oxide channel layer 312 of the non-volatile memory structure 220 above the ferroelectric layer 308 , as described herein.

As further shown in FIG. 12 , process 1200 may include forming a dielectric layer over the metal oxide channel layer (block 1240 ). For example, one or more of semiconductor processing tools 102 - 112 may be used to form a dielectric layer (e.g., ILD layer 212 ) over the metal oxide channel layer 312 , as described herein.

As further shown in FIG. 12 , process 1200 may include forming a source/drain of the non-volatile memory structure at least one of adjacent to or above the metal oxide channel layer (block 1250 ). For example, one or more of semiconductor processing tools 102 - 112 may be used to form the source/drain (e.g., source/drain 314 , 316 ) of the non-volatile memory structure 220 at at least one of adjacent to or above the metal oxide channel layer 312 , as described herein.

As further shown in FIG. 12 , process 1200 may include forming a hydrogen absorber layer 222 a on the source/drain (block 1260 ). For example, one or more of semiconductor processing tools 102 - 112 may be used to form the hydrogen absorber layer 222 a on the source/drain, as described herein.

As further shown in FIG. 12 , process 1200 may include forming a hydrogen barrier layer on the hydrogen absorbing layer (block 1270 ). For example, one or more of semiconductor processing tools 102 - 112 may be used to form hydrogen barrier layer 222 b on hydrogen absorbing layer 222 a , as described herein.

As further shown in FIG. 12 , process 1200 may include forming a conductive structure on the hydrogen barrier layer (block 1280 ). For example, one or more of semiconductor processing tools 102 - 112 may be used to form conductive structure 216 on hydrogen barrier layer 222 b , as described herein.

Process 1200 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in combination with one or more other processes described elsewhere herein.

In a first exemplary embodiment, forming the source/drain includes forming a first recess (e.g., recess 1004, recess 1006) in a dielectric layer, and forming the source/drain in the first recess. Forming the hydrogen absorbing layer 222a includes forming a second recess (e.g., recess 1008, recess 1010) in the dielectric layer, such that the source/drain is exposed through the second recess, and forming the hydrogen absorbing layer 222a in the second recess over the source/drain.

In the second exemplary embodiment, alone or in combination with the first exemplary embodiment, forming the hydrogen barrier layer 222b includes forming the hydrogen barrier layer 222b on the hydrogen absorption layer 222a in the second recess, wherein forming the conductive structure 216 includes forming the conductive structure 216 on the hydrogen barrier layer 222b in the second recess.

In a third exemplary embodiment, alone or in combination with one or more of the first and second exemplary embodiments, forming the hydrogen gettering layer 222a includes performing a plurality of ALD cycles 904 to deposit the hydrogen gettering layer 222a, wherein performing the plurality of ALD cycles 904 includes depositing a first portion (e.g., a metal oxide portion 914a) of the hydrogen gettering layer 222a using a first metal material precursor 908, depositing a second portion (e.g., a metal oxide portion 916a) on the first portion of the hydrogen gettering layer 222a using a second metal material precursor 910, and depositing a third portion (e.g., an oxide semiconductor portion 918) of the hydrogen gettering layer 222a located on the second portion of the hydrogen gettering layer 222a using a semiconductor material precursor 912.

In a fourth exemplary embodiment, alone or in combination with one or more of the first to third exemplary embodiments, performing the ALD cycle 904 further includes depositing a fourth portion of the hydrogen gettering layer 222a (e.g., metal oxide portion 916b) on the third portion of the hydrogen gettering layer 222a using the second metal material precursor 910, and depositing a fifth portion of the hydrogen gettering layer 222a (e.g., metal oxide portion 914b) on the fourth portion of the hydrogen gettering layer 222a using the first metal material precursor 908.

In a fifth exemplary embodiment, alone or in combination with one or more of the first to fourth exemplary embodiments, forming the hydrogen gettering layer includes performing a plurality of ALD cycles (e.g., ALD super cycle 922) to deposit the hydrogen gettering layer 222a, wherein performing one ALD cycle (e.g., ALD super cycle 922) of the plurality of ALD cycles (e.g., ALD super cycle 922) includes depositing a first portion (e.g., metal oxide portion 914a) of the hydrogen gettering layer 222a using a first metal material precursor 908, depositing a second portion (e.g., metal oxide portion 914b) of the hydrogen gettering layer 222a on the first portion of the hydrogen gettering layer 222a using a second metal material precursor 908, and depositing a second portion (e.g., metal oxide portion 914b) of the hydrogen gettering layer 222a using a second metal material precursor 908. A third portion of the hydrogen absorbing layer 222a (e.g., metal oxide portion 916a) is deposited on the second portion of the hydrogen absorbing layer 222a using a metal material precursor 910. A fourth portion of the hydrogen absorbing layer 222a (e.g., metal oxide portion 916b) is deposited on the third portion of the hydrogen absorbing layer 222a using a second metal material precursor 910. A fifth portion of the hydrogen absorbing layer 222a (e.g., oxide semiconductor portion 918a) is deposited on the fourth portion of the hydrogen absorbing layer 222a using a semiconductor material precursor 912. Furthermore, a sixth portion of the hydrogen absorbing layer 222a (e.g., oxide semiconductor portion 918b) is deposited on the fifth portion of the hydrogen absorbing layer 222a using the semiconductor material precursor 912.

Although FIG12 illustrates example blocks of process 1200, in some implementations, process 1200 includes more blocks, fewer blocks, different blocks, or a different arrangement of blocks than depicted in FIG12. Additionally or alternatively, two or more blocks of process 1200 may be executed in parallel.

FIG13 is a flow chart of an example process 1300 associated with forming a semiconductor device described herein. In some implementations, one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-112) are used to perform one or more processing blocks of FIG13. Additionally or alternatively, one or more processing blocks of FIG13 may be performed using one or more components of device 1100, such as processor 1120, memory 1130, input component 1140, output component 1150, and/or communication component 1160.

As shown in FIG13 , process 1300 may include forming a first portion of an interconnect structure of a semiconductor device over a substrate (block 1310 ). For example, one or more of semiconductor processing tools 102 - 112 may be used to form a first portion of the interconnect structure 204 of the semiconductor device 200 over a substrate 206 , as described herein.

As further shown in FIG. 13 , process 1300 may include forming a non-volatile memory structure on the first portion of the interconnect structure (block 1320 ). For example, one or more of semiconductor processing tools 102 - 112 may be used to form the non-volatile memory structure 220 on the first portion of the interconnect structure 204 , as described herein.

As further shown in FIG13 , process 1300 may include forming a second portion of the interconnect structure over the first portion of the interconnect structure and over the non-volatile memory structure (block 1330). For example, one or more of semiconductor processing tools 102-112 may be used to form the second portion of the interconnect structure 204 over the first portion of the interconnect structure 204 and over the non-volatile memory structure 220, as described herein. In some exemplary embodiments, forming the second portion of the interconnect structure 204 includes forming one or more dielectric layers (e.g., one or more ILD layers 212, one or more ESL layers 214) over the first portion of the interconnect structure 204. In some embodiments, forming the second portion of the interconnect structure 204 includes forming a recess 802 in one or more dielectric layers, wherein the first conductive structure 216 in the first portion of the interconnect structure 204 is exposed through the recess 802. The second portion of the interconnect structure 204 includes forming a hydrogen barrier layer 222 on the first conductive structure 216 in the recess 802; and forming the second conductive structure 216 on the hydrogen barrier layer 222 in the recess 802.

Process 1300 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in combination with one or more other processes described elsewhere herein.

In the first exemplary embodiment, forming the hydrogen barrier layer 222 includes forming a hydrogen absorbing layer 222a of the hydrogen barrier layer 222 on the first conductive structure 216 in the recess 802, and forming a hydrogen barrier layer 222b of the hydrogen barrier layer 222 on the hydrogen absorbing layer 222a in the recess 802.

In the second exemplary embodiment, alone or in combination with the first exemplary embodiment, forming the second conductive structure 216 includes forming the second conductive structure 216 on the hydrogen barrier layer 222b.

In the third exemplary embodiment, alone or in combination with one or more of the first and second exemplary embodiments, forming the hydrogen absorbing layer 222a includes forming the hydrogen absorbing layer 222a to a thickness (e.g., dimension D1) within the following range: approximately 10 angstroms to approximately 1000 nanometers.

In a fourth exemplary embodiment, alone or in combination with one or more of the first to third exemplary embodiments, forming the hydrogen barrier layer 222b includes forming the hydrogen barrier layer 222b to a thickness (e.g., dimension D2) within the following range: approximately 10 angstroms to approximately 1000 nanometers.

In a fifth exemplary embodiment, either alone or in combination with one or more of the first to fourth exemplary embodiments, process 1300 includes forming another hydrogen barrier layer 222 on the non-volatile memory structure 220 in the first portion of the interconnect structure 204 before forming the second portion of the interconnect structure 204.

Although FIG13 illustrates example blocks of process 1300, in some implementations, process 1300 includes more blocks, fewer blocks, different blocks, or a different arrangement of blocks than those depicted in FIG13. Additionally or alternatively, two or more blocks of process 1300 may be executed in parallel.

In this manner, a multi-layer hydrogen barrier stack can be included between a non-volatile memory structure and a conductive structure within an interconnect structure within a semiconductor device. The multi-layer hydrogen barrier stack can minimize and/or prevent hydrogen diffusion into one or more layers of the non-volatile memory structure, such as a metal oxide channel within the non-volatile memory structure. The multi-layer hydrogen barrier stack can include a hydrogen absorbing layer and a hydrogen barrier layer positioned above the hydrogen absorbing layer. The hydrogen barrier layer blocks or prevents hydrogen from diffusing through the conductive structure into the non-volatile memory structure. The hydrogen absorber layer absorbs any hydrogen atoms that might diffuse through the hydrogen barrier layer. The combination of the hydrogen absorber layer and the hydrogen barrier layer minimizes and/or prevents hydrogen from diffusing into one or more layers of the FeRAM structure, such as the metal oxide channel of the non-volatile memory structure. This can potentially reduce the concentration of electric carriers in the metal oxide channel of the non-volatile memory structure, which can enable the non-volatile memory structure to achieve low PBTI and/or low NBTI. Additionally and/or alternatively, the combination of the hydrogen absorption layer and the hydrogen blocking layer can enable the non-volatile memory structure to achieve low off-current leakage and/or can reduce the likelihood of the non-volatile memory structure failing due to carrier concentration, which could cause it to become inoperable.

As described in more detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes an interconnect structure located above a substrate of the semiconductor device, the interconnect structure comprising a plurality of dielectric layers and a plurality of conductive structures within the plurality of dielectric layers. The semiconductor device includes a non-volatile memory structure located within a dielectric layer within the plurality of dielectric layers of the interconnect structure, wherein the non-volatile memory structure comprises a metal oxide channel layer, and wherein the non-volatile memory structure is electrically coupled to at least one conductive structure within the plurality of conductive structures. The semiconductor device includes a hydrogen barrier layer located between the non-volatile memory structure and the at least one conductive structure.

In some embodiments, the hydrogen barrier layer comprises a metal oxide semiconductor material.

In some embodiments, the hydrogen barrier layer includes at least one of the following: ruthenium (Ru), aluminum (Al), silver (Ag), platinum (Pt), gold (Au), titanium (Ti), or titanium nitride (TiN).

In some embodiments, the hydrogen barrier layer includes: a hydrogen absorbing layer comprising a metal oxide material; and a hydrogen barrier layer located on the hydrogen absorbing layer and comprising a metal material.

In some embodiments, the hydrogen barrier layer includes: a first titanium nitride (TiN) layer; a metal layer disposed on the first titanium nitride layer; and a second titanium nitride layer disposed on the metal layer.

In some embodiments, the thickness of the metal layer is greater than the thickness of the first titanium nitride layer; and wherein the thickness of the metal layer is greater than the thickness of the second titanium nitride layer.

In some embodiments, the thickness of the metal layer is approximately equal to the thickness of the first titanium nitride layer; and the thickness of the metal layer is approximately equal to the thickness of the second titanium nitride layer.

In some embodiments, the hydrogen barrier layer includes: a first titanium nitride (TiN) layer; a second titanium nitride layer disposed on the first titanium nitride layer; and a third titanium nitride layer disposed on the second titanium nitride layer.

As described in more detail above, some example embodiments described herein provide a method. The method includes forming a bottom gate of a non-volatile memory structure. The method includes forming a ferroelectric layer of the non-volatile memory structure above the bottom gate. The method includes forming a metal oxide channel layer of the non-volatile memory structure above the ferroelectric layer. The method includes forming a dielectric layer above the metal oxide channel layer. The method includes forming a source/drain of the non-volatile memory structure at least near or above the metal oxide channel layer. The method includes forming a hydrogen absorption layer on the source/drain. The method includes forming a hydrogen blocking layer on the hydrogen absorption layer. The method includes forming a conductive structure on the hydrogen blocking layer.

In some embodiments, forming the source/drain includes: forming a first recess in the dielectric layer; and forming the source/drain in the first recess; and forming the hydrogen absorption layer includes: forming a second recess in the dielectric layer, wherein the source/drain is exposed through the second recess; and forming the hydrogen absorption layer in the second recess on the source/drain.

In some embodiments, forming the hydrogen barrier layer includes forming the hydrogen barrier layer on the hydrogen absorption layer in the second recess; and forming the conductive structure includes forming the conductive structure on the hydrogen barrier layer in the second recess.

In some embodiments, forming the hydrogen absorbing layer includes performing a plurality of atomic layer deposition (ALD) cycles to deposit the hydrogen absorbing layer, wherein performing one of the plurality of ALD cycles includes: depositing a first portion of the hydrogen absorbing layer using a first metal material precursor; depositing a second portion of the hydrogen absorbing layer on the first portion of the hydrogen absorbing layer using a second metal material precursor; and depositing a third portion of the hydrogen absorbing layer on the second portion of the hydrogen absorbing layer using a semiconductor material precursor.

In some embodiments, performing the ALD cycle further includes: depositing a fourth portion of the hydrogen absorbing layer on the third portion of the hydrogen absorbing layer using the second metal precursor; and depositing a fifth portion of the hydrogen absorbing layer on the fourth portion of the hydrogen absorbing layer using the first metal precursor.

In some embodiments, the step of forming the hydrogen absorbing layer includes: performing a plurality of atomic layer deposition (ALD) cycles to deposit the hydrogen absorbing layer, wherein performing one of the plurality of ALD cycles includes: depositing a first portion of the hydrogen absorbing layer using a first metal material precursor; depositing a second portion of the hydrogen absorbing layer on the first portion of the hydrogen absorbing layer using the first metal material precursor; and depositing a second portion of the hydrogen absorbing layer on the second portion of the hydrogen absorbing layer using a second metal material precursor. The third portion of the hydrogen absorbing layer is deposited on the second portion of the hydrogen absorbing layer; the fourth portion of the hydrogen absorbing layer is deposited on the third portion of the hydrogen absorbing layer using the second metal material precursor; the fifth portion of the hydrogen absorbing layer is deposited on the fourth portion of the hydrogen absorbing layer using a semiconductor material precursor; and the sixth portion of the hydrogen absorbing layer is deposited on the fifth portion of the hydrogen absorbing layer using the semiconductor material precursor.

As described in more detail above, some example embodiments described herein provide a method. The method includes forming a first portion of an interconnect structure of a semiconductor device over a substrate. The method includes forming a non-volatile memory structure over the first portion of the interconnect structure. The method includes forming a second portion of the interconnect structure over the first portion of the interconnect structure and over the non-volatile memory structure, wherein forming the second portion of the interconnect structure includes forming one or more dielectric layers over the first portion of the interconnect structure. A recess is formed in the one or more dielectric layers of the interconnect structure, wherein a first conductive structure in the first portion of the interconnect structure is exposed through the recess, a hydrogen barrier layer is formed over the first conductive structure in the recess, and a second conductive structure is formed over the hydrogen barrier layer in the recess.

In some embodiments, the step of forming the hydrogen barrier layer includes: forming a hydrogen absorbing layer of the hydrogen barrier layer on the first conductive structure in the recess; and forming a hydrogen barrier layer of the hydrogen barrier layer on the hydrogen absorbing layer in the recess.

In some embodiments, forming the second conductive structure includes forming the second conductive structure on the hydrogen barrier layer.

In some embodiments, the step of forming the hydrogen absorption layer includes forming the hydrogen absorption layer to a thickness ranging from about 10 angstroms to about 1000 nanometers.

In some embodiments, forming the hydrogen barrier layer includes forming the hydrogen barrier layer to a thickness ranging from about 10 angstroms to about 1000 nanometers.

In some embodiments, the method further includes forming another hydrogen barrier layer on the non-volatile memory structure in the first portion of the interconnect structure before forming the second portion of the interconnect structure.

As used herein, "meets a threshold" may refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, or not equal to a threshold, depending on the context.

The foregoing summarizes the features of several embodiments to help those skilled in the art better understand the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and/or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they may make various changes, substitutions, and alterations thereto without departing from the spirit and scope of this disclosure.

200, 208: Semiconductor devices

202: Device layer

204: Internal connection structure

206: Base

210: Dielectric layer

212: Interlayer dielectric layer

214: Etch stop layer

216:Conductive structure

218: Connection structure

220: Non-volatile memory structure

222: Hydrogen barrier layer

222a: Hydrogen absorption layer

222b: Hydrogen barrier layer

X, Z: Direction

Claims (10)

A semiconductor device includes: an interconnect structure located above a substrate of the semiconductor device, comprising: a plurality of dielectric layers; and a plurality of conductive structures in the plurality of dielectric layers; a non-volatile memory structure located in a dielectric layer in the plurality of dielectric layers of the interconnect structure, wherein the non-volatile memory structure includes a metal oxide channel layer, and wherein the non-volatile memory structure electrically coupled to at least one of the plurality of conductive structures; and a hydrogen barrier layer located between the non-volatile memory structure and the at least one conductive structure, the hydrogen barrier layer comprising: a hydrogen absorbing layer comprising a metal oxide material; and a hydrogen barrier layer located on the hydrogen absorbing layer and comprising a metal material, wherein the material of the hydrogen absorbing layer is different from the material of the hydrogen barrier layer. The semiconductor device of claim 1, wherein the hydrogen barrier layer comprises: a first titanium nitride (TiN) layer; a metal layer located on the first titanium nitride layer; and a second titanium nitride layer located on the metal layer. A method for forming a semiconductor device, comprising: forming a bottom gate of a non-volatile memory structure; forming a ferroelectric layer of the non-volatile memory structure above the bottom gate; forming a metal oxide channel layer of the non-volatile memory structure above the ferroelectric layer; forming a dielectric layer above the metal oxide channel layer; forming the non-volatile memory structure; forming a dielectric layer ... The source/drain of the memory structure is at least adjacent to or located above the metal oxide channel layer; a hydrogen absorption layer is formed above the source/drain; a hydrogen barrier layer is formed on the hydrogen absorption layer; and a conductive structure is formed on the hydrogen barrier layer, wherein the material of the hydrogen absorption layer is different from the material of the hydrogen barrier layer. A method as described in claim 3, wherein the step of forming the source/drain includes: forming a first recess in the dielectric layer; and forming the source/drain in the first recess; and wherein forming the hydrogen absorption layer includes: forming a second recess in the dielectric layer, wherein the source/drain is exposed through the second recess; and forming the hydrogen absorption layer in the second recess on the source/drain. The method of claim 4, wherein forming the hydrogen barrier layer comprises: forming the hydrogen barrier layer on the hydrogen absorption layer in the second recess; and wherein forming the conductive structure comprises: forming the conductive structure on the hydrogen barrier layer in the second recess. A method as described in claim 3, wherein the step of forming the hydrogen absorbing layer includes: performing multiple atomic layer deposition (ALD) cycles to deposit the hydrogen absorbing layer, wherein performing one of the multiple ALD cycles includes: depositing a first portion of the hydrogen absorbing layer using a first metal material precursor; depositing a second portion of the hydrogen absorbing layer on the first portion of the hydrogen absorbing layer using a second metal material precursor; and depositing a third portion of the hydrogen absorbing layer on the second portion of the hydrogen absorbing layer using a semiconductor material precursor. A method as described in claim 6, wherein performing the ALD cycle further includes: depositing a fourth portion of the hydrogen absorbing layer on the third portion of the hydrogen absorbing layer using the second metal material precursor; and depositing a fifth portion of the hydrogen absorbing layer on the fourth portion of the hydrogen absorbing layer using the first metal material precursor. The method of claim 3, wherein the step of forming the hydrogen absorbing layer comprises: performing a plurality of atomic layer deposition (ALD) cycles to deposit the hydrogen absorbing layer, wherein performing one of the plurality of ALD cycles comprises: depositing a first portion of the hydrogen absorbing layer using a first metal material precursor; depositing a second portion of the hydrogen absorbing layer on the first portion of the hydrogen absorbing layer using the first metal material precursor; and depositing a second portion of the hydrogen absorbing layer on the first portion of the hydrogen absorbing layer using a second metal material precursor. depositing a third portion of the hydrogen absorbing layer on the second portion of the hydrogen absorbing layer using a precursor of a second metal material; depositing a fourth portion of the hydrogen absorbing layer on the third portion of the hydrogen absorbing layer using a precursor of a semiconductor material; and depositing a sixth portion of the hydrogen absorbing layer on the fifth portion of the hydrogen absorbing layer using a precursor of a semiconductor material. A method for forming a semiconductor device comprises: forming a first portion of an interconnect structure of the semiconductor device over a substrate; forming a non-volatile memory structure in the first portion of the interconnect structure; and forming a second portion of the interconnect structure over the first portion of the interconnect structure and over the non-volatile memory structure, wherein forming the second portion of the interconnect structure comprises: forming one or more dielectric layers over the first portion of the interconnect structure; forming a dielectric layer over the one or more dielectric layers; and forming a dielectric layer over the one or more dielectric layers. A recess is formed in one or more dielectric layers, wherein the first conductive structure in the first portion of the interconnect structure is exposed through the recess; a hydrogen barrier layer is formed on the first conductive structure in the recess; and a second conductive structure is formed on the hydrogen barrier layer in the recess, wherein the hydrogen barrier layer includes: a hydrogen absorbing layer including a metal oxide material; and a hydrogen barrier layer located on the hydrogen absorbing layer and including a metal material, wherein the material of the hydrogen absorbing layer is different from the material of the hydrogen barrier layer. The method of claim 9 further comprises: forming another hydrogen barrier layer on the non-volatile memory structure in the first portion of the interconnect structure before forming the second portion of the interconnect structure.